diff options
-rw-r--r-- | drivers/gpu/drm/radeon/rs780_dpm.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770_dpm.c | 10 |
2 files changed, 14 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/rs780_dpm.c b/drivers/gpu/drm/radeon/rs780_dpm.c index 625d6ea1f0d1..828a7764660c 100644 --- a/drivers/gpu/drm/radeon/rs780_dpm.c +++ b/drivers/gpu/drm/radeon/rs780_dpm.c | |||
@@ -726,14 +726,18 @@ static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev, | |||
726 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { | 726 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { |
727 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); | 727 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); |
728 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); | 728 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); |
729 | } else if (r600_is_uvd_state(rps->class, rps->class2)) { | ||
730 | rps->vclk = RS780_DEFAULT_VCLK_FREQ; | ||
731 | rps->dclk = RS780_DEFAULT_DCLK_FREQ; | ||
732 | } else { | 729 | } else { |
733 | rps->vclk = 0; | 730 | rps->vclk = 0; |
734 | rps->dclk = 0; | 731 | rps->dclk = 0; |
735 | } | 732 | } |
736 | 733 | ||
734 | if (r600_is_uvd_state(rps->class, rps->class2)) { | ||
735 | if ((rps->vclk == 0) || (rps->dclk == 0)) { | ||
736 | rps->vclk = RS780_DEFAULT_VCLK_FREQ; | ||
737 | rps->dclk = RS780_DEFAULT_DCLK_FREQ; | ||
738 | } | ||
739 | } | ||
740 | |||
737 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) | 741 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) |
738 | rdev->pm.dpm.boot_ps = rps; | 742 | rdev->pm.dpm.boot_ps = rps; |
739 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | 743 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |
diff --git a/drivers/gpu/drm/radeon/rv770_dpm.c b/drivers/gpu/drm/radeon/rv770_dpm.c index 8cbb85dae5aa..7282ce7dab76 100644 --- a/drivers/gpu/drm/radeon/rv770_dpm.c +++ b/drivers/gpu/drm/radeon/rv770_dpm.c | |||
@@ -2147,14 +2147,18 @@ static void rv7xx_parse_pplib_non_clock_info(struct radeon_device *rdev, | |||
2147 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { | 2147 | if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { |
2148 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); | 2148 | rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); |
2149 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); | 2149 | rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); |
2150 | } else if (r600_is_uvd_state(rps->class, rps->class2)) { | ||
2151 | rps->vclk = RV770_DEFAULT_VCLK_FREQ; | ||
2152 | rps->dclk = RV770_DEFAULT_DCLK_FREQ; | ||
2153 | } else { | 2150 | } else { |
2154 | rps->vclk = 0; | 2151 | rps->vclk = 0; |
2155 | rps->dclk = 0; | 2152 | rps->dclk = 0; |
2156 | } | 2153 | } |
2157 | 2154 | ||
2155 | if (r600_is_uvd_state(rps->class, rps->class2)) { | ||
2156 | if ((rps->vclk == 0) || (rps->dclk == 0)) { | ||
2157 | rps->vclk = RV770_DEFAULT_VCLK_FREQ; | ||
2158 | rps->dclk = RV770_DEFAULT_DCLK_FREQ; | ||
2159 | } | ||
2160 | } | ||
2161 | |||
2158 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) | 2162 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) |
2159 | rdev->pm.dpm.boot_ps = rps; | 2163 | rdev->pm.dpm.boot_ps = rps; |
2160 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) | 2164 | if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) |