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-rw-r--r--arch/arm/mach-shmobile/clock-r8a7791.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index fda7c6cb6921..ff2d60d55bd5 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -124,6 +124,7 @@ static struct clk *main_clks[] = {
124enum { 124enum {
125 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720, 125 MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
126 MSTP719, MSTP718, MSTP715, MSTP714, 126 MSTP719, MSTP718, MSTP715, MSTP714,
127 MSTP522,
127 MSTP216, MSTP207, MSTP206, 128 MSTP216, MSTP207, MSTP206,
128 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, 129 MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
129 MSTP124, 130 MSTP124,
@@ -140,6 +141,7 @@ static struct clk mstp_clks[MSTP_NR] = {
140 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ 141 [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */
141 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ 142 [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */
142 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ 143 [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */
144 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
143 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ 145 [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
144 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ 146 [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
145 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ 147 [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
@@ -188,6 +190,8 @@ static struct clk_lookup lookups[] = {
188 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ 190 CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
189 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ 191 CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
190 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), 192 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
193 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
194 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
191}; 195};
192 196
193#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 197#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \