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-rw-r--r--arch/arm/boot/dts/vexpress-v2m-rs1.dtsi135
-rw-r--r--arch/arm/boot/dts/vexpress-v2m.dtsi135
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts110
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts175
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca5s.dts73
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca9.dts125
6 files changed, 749 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index d8a827bd2bf3..9a7b6922f83b 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -24,6 +24,7 @@
24 24
25 motherboard { 25 motherboard {
26 compatible = "simple-bus"; 26 compatible = "simple-bus";
27 arm,vexpress,site = <0>;
27 arm,v2m-memory-map = "rs1"; 28 arm,v2m-memory-map = "rs1";
28 #address-cells = <2>; /* SMB chipselect number and offset */ 29 #address-cells = <2>; /* SMB chipselect number and offset */
29 #size-cells = <1>; 30 #size-cells = <1>;
@@ -72,14 +73,20 @@
72 #size-cells = <1>; 73 #size-cells = <1>;
73 ranges = <0 3 0 0x200000>; 74 ranges = <0 3 0 0x200000>;
74 75
75 sysreg@010000 { 76 v2m_sysreg: sysreg@010000 {
76 compatible = "arm,vexpress-sysreg"; 77 compatible = "arm,vexpress-sysreg";
77 reg = <0x010000 0x1000>; 78 reg = <0x010000 0x1000>;
79 gpio-controller;
80 #gpio-cells = <2>;
78 }; 81 };
79 82
80 sysctl@020000 { 83 v2m_sysctl: sysctl@020000 {
81 compatible = "arm,sp810", "arm,primecell"; 84 compatible = "arm,sp810", "arm,primecell";
82 reg = <0x020000 0x1000>; 85 reg = <0x020000 0x1000>;
86 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
87 clock-names = "refclk", "timclk", "apb_pclk";
88 #clock-cells = <1>;
89 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
83 }; 90 };
84 91
85 /* PCI-E I2C bus */ 92 /* PCI-E I2C bus */
@@ -100,66 +107,92 @@
100 compatible = "arm,pl041", "arm,primecell"; 107 compatible = "arm,pl041", "arm,primecell";
101 reg = <0x040000 0x1000>; 108 reg = <0x040000 0x1000>;
102 interrupts = <11>; 109 interrupts = <11>;
110 clocks = <&smbclk>;
111 clock-names = "apb_pclk";
103 }; 112 };
104 113
105 mmci@050000 { 114 mmci@050000 {
106 compatible = "arm,pl180", "arm,primecell"; 115 compatible = "arm,pl180", "arm,primecell";
107 reg = <0x050000 0x1000>; 116 reg = <0x050000 0x1000>;
108 interrupts = <9 10>; 117 interrupts = <9 10>;
118 cd-gpios = <&v2m_sysreg 0 0>;
119 wp-gpios = <&v2m_sysreg 1 0>;
120 max-frequency = <12000000>;
121 vmmc-supply = <&v2m_fixed_3v3>;
122 clocks = <&v2m_clk24mhz>, <&smbclk>;
123 clock-names = "mclk", "apb_pclk";
109 }; 124 };
110 125
111 kmi@060000 { 126 kmi@060000 {
112 compatible = "arm,pl050", "arm,primecell"; 127 compatible = "arm,pl050", "arm,primecell";
113 reg = <0x060000 0x1000>; 128 reg = <0x060000 0x1000>;
114 interrupts = <12>; 129 interrupts = <12>;
130 clocks = <&v2m_clk24mhz>, <&smbclk>;
131 clock-names = "KMIREFCLK", "apb_pclk";
115 }; 132 };
116 133
117 kmi@070000 { 134 kmi@070000 {
118 compatible = "arm,pl050", "arm,primecell"; 135 compatible = "arm,pl050", "arm,primecell";
119 reg = <0x070000 0x1000>; 136 reg = <0x070000 0x1000>;
120 interrupts = <13>; 137 interrupts = <13>;
138 clocks = <&v2m_clk24mhz>, <&smbclk>;
139 clock-names = "KMIREFCLK", "apb_pclk";
121 }; 140 };
122 141
123 v2m_serial0: uart@090000 { 142 v2m_serial0: uart@090000 {
124 compatible = "arm,pl011", "arm,primecell"; 143 compatible = "arm,pl011", "arm,primecell";
125 reg = <0x090000 0x1000>; 144 reg = <0x090000 0x1000>;
126 interrupts = <5>; 145 interrupts = <5>;
146 clocks = <&v2m_oscclk2>, <&smbclk>;
147 clock-names = "uartclk", "apb_pclk";
127 }; 148 };
128 149
129 v2m_serial1: uart@0a0000 { 150 v2m_serial1: uart@0a0000 {
130 compatible = "arm,pl011", "arm,primecell"; 151 compatible = "arm,pl011", "arm,primecell";
131 reg = <0x0a0000 0x1000>; 152 reg = <0x0a0000 0x1000>;
132 interrupts = <6>; 153 interrupts = <6>;
154 clocks = <&v2m_oscclk2>, <&smbclk>;
155 clock-names = "uartclk", "apb_pclk";
133 }; 156 };
134 157
135 v2m_serial2: uart@0b0000 { 158 v2m_serial2: uart@0b0000 {
136 compatible = "arm,pl011", "arm,primecell"; 159 compatible = "arm,pl011", "arm,primecell";
137 reg = <0x0b0000 0x1000>; 160 reg = <0x0b0000 0x1000>;
138 interrupts = <7>; 161 interrupts = <7>;
162 clocks = <&v2m_oscclk2>, <&smbclk>;
163 clock-names = "uartclk", "apb_pclk";
139 }; 164 };
140 165
141 v2m_serial3: uart@0c0000 { 166 v2m_serial3: uart@0c0000 {
142 compatible = "arm,pl011", "arm,primecell"; 167 compatible = "arm,pl011", "arm,primecell";
143 reg = <0x0c0000 0x1000>; 168 reg = <0x0c0000 0x1000>;
144 interrupts = <8>; 169 interrupts = <8>;
170 clocks = <&v2m_oscclk2>, <&smbclk>;
171 clock-names = "uartclk", "apb_pclk";
145 }; 172 };
146 173
147 wdt@0f0000 { 174 wdt@0f0000 {
148 compatible = "arm,sp805", "arm,primecell"; 175 compatible = "arm,sp805", "arm,primecell";
149 reg = <0x0f0000 0x1000>; 176 reg = <0x0f0000 0x1000>;
150 interrupts = <0>; 177 interrupts = <0>;
178 clocks = <&v2m_refclk32khz>, <&smbclk>;
179 clock-names = "wdogclk", "apb_pclk";
151 }; 180 };
152 181
153 v2m_timer01: timer@110000 { 182 v2m_timer01: timer@110000 {
154 compatible = "arm,sp804", "arm,primecell"; 183 compatible = "arm,sp804", "arm,primecell";
155 reg = <0x110000 0x1000>; 184 reg = <0x110000 0x1000>;
156 interrupts = <2>; 185 interrupts = <2>;
186 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
187 clock-names = "timclken1", "timclken2", "apb_pclk";
157 }; 188 };
158 189
159 v2m_timer23: timer@120000 { 190 v2m_timer23: timer@120000 {
160 compatible = "arm,sp804", "arm,primecell"; 191 compatible = "arm,sp804", "arm,primecell";
161 reg = <0x120000 0x1000>; 192 reg = <0x120000 0x1000>;
162 interrupts = <3>; 193 interrupts = <3>;
194 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
195 clock-names = "timclken1", "timclken2", "apb_pclk";
163 }; 196 };
164 197
165 /* DVI I2C bus */ 198 /* DVI I2C bus */
@@ -185,6 +218,8 @@
185 compatible = "arm,pl031", "arm,primecell"; 218 compatible = "arm,pl031", "arm,primecell";
186 reg = <0x170000 0x1000>; 219 reg = <0x170000 0x1000>;
187 interrupts = <4>; 220 interrupts = <4>;
221 clocks = <&smbclk>;
222 clock-names = "apb_pclk";
188 }; 223 };
189 224
190 compact-flash@1a0000 { 225 compact-flash@1a0000 {
@@ -198,6 +233,8 @@
198 compatible = "arm,pl111", "arm,primecell"; 233 compatible = "arm,pl111", "arm,primecell";
199 reg = <0x1f0000 0x1000>; 234 reg = <0x1f0000 0x1000>;
200 interrupts = <14>; 235 interrupts = <14>;
236 clocks = <&v2m_oscclk1>, <&smbclk>;
237 clock-names = "clcdclk", "apb_pclk";
201 }; 238 };
202 }; 239 };
203 240
@@ -208,5 +245,99 @@
208 regulator-max-microvolt = <3300000>; 245 regulator-max-microvolt = <3300000>;
209 regulator-always-on; 246 regulator-always-on;
210 }; 247 };
248
249 v2m_clk24mhz: clk24mhz {
250 compatible = "fixed-clock";
251 #clock-cells = <0>;
252 clock-frequency = <24000000>;
253 clock-output-names = "v2m:clk24mhz";
254 };
255
256 v2m_refclk1mhz: refclk1mhz {
257 compatible = "fixed-clock";
258 #clock-cells = <0>;
259 clock-frequency = <1000000>;
260 clock-output-names = "v2m:refclk1mhz";
261 };
262
263 v2m_refclk32khz: refclk32khz {
264 compatible = "fixed-clock";
265 #clock-cells = <0>;
266 clock-frequency = <32768>;
267 clock-output-names = "v2m:refclk32khz";
268 };
269
270 mcc {
271 compatible = "arm,vexpress,config-bus";
272 arm,vexpress,config-bridge = <&v2m_sysreg>;
273
274 osc@0 {
275 /* MCC static memory clock */
276 compatible = "arm,vexpress-osc";
277 arm,vexpress-sysreg,func = <1 0>;
278 freq-range = <25000000 60000000>;
279 #clock-cells = <0>;
280 clock-output-names = "v2m:oscclk0";
281 };
282
283 v2m_oscclk1: osc@1 {
284 /* CLCD clock */
285 compatible = "arm,vexpress-osc";
286 arm,vexpress-sysreg,func = <1 1>;
287 freq-range = <23750000 63500000>;
288 #clock-cells = <0>;
289 clock-output-names = "v2m:oscclk1";
290 };
291
292 v2m_oscclk2: osc@2 {
293 /* IO FPGA peripheral clock */
294 compatible = "arm,vexpress-osc";
295 arm,vexpress-sysreg,func = <1 2>;
296 freq-range = <24000000 24000000>;
297 #clock-cells = <0>;
298 clock-output-names = "v2m:oscclk2";
299 };
300
301 volt@0 {
302 /* Logic level voltage */
303 compatible = "arm,vexpress-volt";
304 arm,vexpress-sysreg,func = <2 0>;
305 regulator-name = "VIO";
306 regulator-always-on;
307 label = "VIO";
308 };
309
310 temp@0 {
311 /* MCC internal operating temperature */
312 compatible = "arm,vexpress-temp";
313 arm,vexpress-sysreg,func = <4 0>;
314 label = "MCC";
315 };
316
317 reset@0 {
318 compatible = "arm,vexpress-reset";
319 arm,vexpress-sysreg,func = <5 0>;
320 };
321
322 muxfpga@0 {
323 compatible = "arm,vexpress-muxfpga";
324 arm,vexpress-sysreg,func = <7 0>;
325 };
326
327 shutdown@0 {
328 compatible = "arm,vexpress-shutdown";
329 arm,vexpress-sysreg,func = <8 0>;
330 };
331
332 reboot@0 {
333 compatible = "arm,vexpress-reboot";
334 arm,vexpress-sysreg,func = <9 0>;
335 };
336
337 dvimode@0 {
338 compatible = "arm,vexpress-dvimode";
339 arm,vexpress-sysreg,func = <11 0>;
340 };
341 };
211 }; 342 };
212}; 343};
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index dba53fd026bb..4d321a832dbd 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -24,6 +24,7 @@
24 24
25 motherboard { 25 motherboard {
26 compatible = "simple-bus"; 26 compatible = "simple-bus";
27 arm,vexpress,site = <0>;
27 #address-cells = <2>; /* SMB chipselect number and offset */ 28 #address-cells = <2>; /* SMB chipselect number and offset */
28 #size-cells = <1>; 29 #size-cells = <1>;
29 #interrupt-cells = <1>; 30 #interrupt-cells = <1>;
@@ -71,14 +72,20 @@
71 #size-cells = <1>; 72 #size-cells = <1>;
72 ranges = <0 7 0 0x20000>; 73 ranges = <0 7 0 0x20000>;
73 74
74 sysreg@00000 { 75 v2m_sysreg: sysreg@00000 {
75 compatible = "arm,vexpress-sysreg"; 76 compatible = "arm,vexpress-sysreg";
76 reg = <0x00000 0x1000>; 77 reg = <0x00000 0x1000>;
78 gpio-controller;
79 #gpio-cells = <2>;
77 }; 80 };
78 81
79 sysctl@01000 { 82 v2m_sysctl: sysctl@01000 {
80 compatible = "arm,sp810", "arm,primecell"; 83 compatible = "arm,sp810", "arm,primecell";
81 reg = <0x01000 0x1000>; 84 reg = <0x01000 0x1000>;
85 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
86 clock-names = "refclk", "timclk", "apb_pclk";
87 #clock-cells = <1>;
88 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
82 }; 89 };
83 90
84 /* PCI-E I2C bus */ 91 /* PCI-E I2C bus */
@@ -99,66 +106,92 @@
99 compatible = "arm,pl041", "arm,primecell"; 106 compatible = "arm,pl041", "arm,primecell";
100 reg = <0x04000 0x1000>; 107 reg = <0x04000 0x1000>;
101 interrupts = <11>; 108 interrupts = <11>;
109 clocks = <&smbclk>;
110 clock-names = "apb_pclk";
102 }; 111 };
103 112
104 mmci@05000 { 113 mmci@05000 {
105 compatible = "arm,pl180", "arm,primecell"; 114 compatible = "arm,pl180", "arm,primecell";
106 reg = <0x05000 0x1000>; 115 reg = <0x05000 0x1000>;
107 interrupts = <9 10>; 116 interrupts = <9 10>;
117 cd-gpios = <&v2m_sysreg 0 0>;
118 wp-gpios = <&v2m_sysreg 1 0>;
119 max-frequency = <12000000>;
120 vmmc-supply = <&v2m_fixed_3v3>;
121 clocks = <&v2m_clk24mhz>, <&smbclk>;
122 clock-names = "mclk", "apb_pclk";
108 }; 123 };
109 124
110 kmi@06000 { 125 kmi@06000 {
111 compatible = "arm,pl050", "arm,primecell"; 126 compatible = "arm,pl050", "arm,primecell";
112 reg = <0x06000 0x1000>; 127 reg = <0x06000 0x1000>;
113 interrupts = <12>; 128 interrupts = <12>;
129 clocks = <&v2m_clk24mhz>, <&smbclk>;
130 clock-names = "KMIREFCLK", "apb_pclk";
114 }; 131 };
115 132
116 kmi@07000 { 133 kmi@07000 {
117 compatible = "arm,pl050", "arm,primecell"; 134 compatible = "arm,pl050", "arm,primecell";
118 reg = <0x07000 0x1000>; 135 reg = <0x07000 0x1000>;
119 interrupts = <13>; 136 interrupts = <13>;
137 clocks = <&v2m_clk24mhz>, <&smbclk>;
138 clock-names = "KMIREFCLK", "apb_pclk";
120 }; 139 };
121 140
122 v2m_serial0: uart@09000 { 141 v2m_serial0: uart@09000 {
123 compatible = "arm,pl011", "arm,primecell"; 142 compatible = "arm,pl011", "arm,primecell";
124 reg = <0x09000 0x1000>; 143 reg = <0x09000 0x1000>;
125 interrupts = <5>; 144 interrupts = <5>;
145 clocks = <&v2m_oscclk2>, <&smbclk>;
146 clock-names = "uartclk", "apb_pclk";
126 }; 147 };
127 148
128 v2m_serial1: uart@0a000 { 149 v2m_serial1: uart@0a000 {
129 compatible = "arm,pl011", "arm,primecell"; 150 compatible = "arm,pl011", "arm,primecell";
130 reg = <0x0a000 0x1000>; 151 reg = <0x0a000 0x1000>;
131 interrupts = <6>; 152 interrupts = <6>;
153 clocks = <&v2m_oscclk2>, <&smbclk>;
154 clock-names = "uartclk", "apb_pclk";
132 }; 155 };
133 156
134 v2m_serial2: uart@0b000 { 157 v2m_serial2: uart@0b000 {
135 compatible = "arm,pl011", "arm,primecell"; 158 compatible = "arm,pl011", "arm,primecell";
136 reg = <0x0b000 0x1000>; 159 reg = <0x0b000 0x1000>;
137 interrupts = <7>; 160 interrupts = <7>;
161 clocks = <&v2m_oscclk2>, <&smbclk>;
162 clock-names = "uartclk", "apb_pclk";
138 }; 163 };
139 164
140 v2m_serial3: uart@0c000 { 165 v2m_serial3: uart@0c000 {
141 compatible = "arm,pl011", "arm,primecell"; 166 compatible = "arm,pl011", "arm,primecell";
142 reg = <0x0c000 0x1000>; 167 reg = <0x0c000 0x1000>;
143 interrupts = <8>; 168 interrupts = <8>;
169 clocks = <&v2m_oscclk2>, <&smbclk>;
170 clock-names = "uartclk", "apb_pclk";
144 }; 171 };
145 172
146 wdt@0f000 { 173 wdt@0f000 {
147 compatible = "arm,sp805", "arm,primecell"; 174 compatible = "arm,sp805", "arm,primecell";
148 reg = <0x0f000 0x1000>; 175 reg = <0x0f000 0x1000>;
149 interrupts = <0>; 176 interrupts = <0>;
177 clocks = <&v2m_refclk32khz>, <&smbclk>;
178 clock-names = "wdogclk", "apb_pclk";
150 }; 179 };
151 180
152 v2m_timer01: timer@11000 { 181 v2m_timer01: timer@11000 {
153 compatible = "arm,sp804", "arm,primecell"; 182 compatible = "arm,sp804", "arm,primecell";
154 reg = <0x11000 0x1000>; 183 reg = <0x11000 0x1000>;
155 interrupts = <2>; 184 interrupts = <2>;
185 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
186 clock-names = "timclken1", "timclken2", "apb_pclk";
156 }; 187 };
157 188
158 v2m_timer23: timer@12000 { 189 v2m_timer23: timer@12000 {
159 compatible = "arm,sp804", "arm,primecell"; 190 compatible = "arm,sp804", "arm,primecell";
160 reg = <0x12000 0x1000>; 191 reg = <0x12000 0x1000>;
161 interrupts = <3>; 192 interrupts = <3>;
193 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
194 clock-names = "timclken1", "timclken2", "apb_pclk";
162 }; 195 };
163 196
164 /* DVI I2C bus */ 197 /* DVI I2C bus */
@@ -184,6 +217,8 @@
184 compatible = "arm,pl031", "arm,primecell"; 217 compatible = "arm,pl031", "arm,primecell";
185 reg = <0x17000 0x1000>; 218 reg = <0x17000 0x1000>;
186 interrupts = <4>; 219 interrupts = <4>;
220 clocks = <&smbclk>;
221 clock-names = "apb_pclk";
187 }; 222 };
188 223
189 compact-flash@1a000 { 224 compact-flash@1a000 {
@@ -197,6 +232,8 @@
197 compatible = "arm,pl111", "arm,primecell"; 232 compatible = "arm,pl111", "arm,primecell";
198 reg = <0x1f000 0x1000>; 233 reg = <0x1f000 0x1000>;
199 interrupts = <14>; 234 interrupts = <14>;
235 clocks = <&v2m_oscclk1>, <&smbclk>;
236 clock-names = "clcdclk", "apb_pclk";
200 }; 237 };
201 }; 238 };
202 239
@@ -207,5 +244,99 @@
207 regulator-max-microvolt = <3300000>; 244 regulator-max-microvolt = <3300000>;
208 regulator-always-on; 245 regulator-always-on;
209 }; 246 };
247
248 v2m_clk24mhz: clk24mhz {
249 compatible = "fixed-clock";
250 #clock-cells = <0>;
251 clock-frequency = <24000000>;
252 clock-output-names = "v2m:clk24mhz";
253 };
254
255 v2m_refclk1mhz: refclk1mhz {
256 compatible = "fixed-clock";
257 #clock-cells = <0>;
258 clock-frequency = <1000000>;
259 clock-output-names = "v2m:refclk1mhz";
260 };
261
262 v2m_refclk32khz: refclk32khz {
263 compatible = "fixed-clock";
264 #clock-cells = <0>;
265 clock-frequency = <32768>;
266 clock-output-names = "v2m:refclk32khz";
267 };
268
269 mcc {
270 compatible = "arm,vexpress,config-bus";
271 arm,vexpress,config-bridge = <&v2m_sysreg>;
272
273 osc@0 {
274 /* MCC static memory clock */
275 compatible = "arm,vexpress-osc";
276 arm,vexpress-sysreg,func = <1 0>;
277 freq-range = <25000000 60000000>;
278 #clock-cells = <0>;
279 clock-output-names = "v2m:oscclk0";
280 };
281
282 v2m_oscclk1: osc@1 {
283 /* CLCD clock */
284 compatible = "arm,vexpress-osc";
285 arm,vexpress-sysreg,func = <1 1>;
286 freq-range = <23750000 63500000>;
287 #clock-cells = <0>;
288 clock-output-names = "v2m:oscclk1";
289 };
290
291 v2m_oscclk2: osc@2 {
292 /* IO FPGA peripheral clock */
293 compatible = "arm,vexpress-osc";
294 arm,vexpress-sysreg,func = <1 2>;
295 freq-range = <24000000 24000000>;
296 #clock-cells = <0>;
297 clock-output-names = "v2m:oscclk2";
298 };
299
300 volt@0 {
301 /* Logic level voltage */
302 compatible = "arm,vexpress-volt";
303 arm,vexpress-sysreg,func = <2 0>;
304 regulator-name = "VIO";
305 regulator-always-on;
306 label = "VIO";
307 };
308
309 temp@0 {
310 /* MCC internal operating temperature */
311 compatible = "arm,vexpress-temp";
312 arm,vexpress-sysreg,func = <4 0>;
313 label = "MCC";
314 };
315
316 reset@0 {
317 compatible = "arm,vexpress-reset";
318 arm,vexpress-sysreg,func = <5 0>;
319 };
320
321 muxfpga@0 {
322 compatible = "arm,vexpress-muxfpga";
323 arm,vexpress-sysreg,func = <7 0>;
324 };
325
326 shutdown@0 {
327 compatible = "arm,vexpress-shutdown";
328 arm,vexpress-sysreg,func = <8 0>;
329 };
330
331 reboot@0 {
332 compatible = "arm,vexpress-reboot";
333 arm,vexpress-sysreg,func = <9 0>;
334 };
335
336 dvimode@0 {
337 compatible = "arm,vexpress-dvimode";
338 arm,vexpress-sysreg,func = <11 0>;
339 };
340 };
210 }; 341 };
211}; 342};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index d12b34ca0568..4bbed10de45b 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA15"; 13 model = "V2P-CA15";
14 arm,hbi = <0x237>; 14 arm,hbi = <0x237>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <2>; 18 #address-cells = <2>;
@@ -54,17 +55,24 @@
54 compatible = "arm,hdlcd"; 55 compatible = "arm,hdlcd";
55 reg = <0 0x2b000000 0 0x1000>; 56 reg = <0 0x2b000000 0 0x1000>;
56 interrupts = <0 85 4>; 57 interrupts = <0 85 4>;
58 clocks = <&oscclk5>;
59 clock-names = "pxlclk";
57 }; 60 };
58 61
59 memory-controller@2b0a0000 { 62 memory-controller@2b0a0000 {
60 compatible = "arm,pl341", "arm,primecell"; 63 compatible = "arm,pl341", "arm,primecell";
61 reg = <0 0x2b0a0000 0 0x1000>; 64 reg = <0 0x2b0a0000 0 0x1000>;
65 clocks = <&oscclk7>;
66 clock-names = "apb_pclk";
62 }; 67 };
63 68
64 wdt@2b060000 { 69 wdt@2b060000 {
65 compatible = "arm,sp805", "arm,primecell"; 70 compatible = "arm,sp805", "arm,primecell";
71 status = "disabled";
66 reg = <0 0x2b060000 0 0x1000>; 72 reg = <0 0x2b060000 0 0x1000>;
67 interrupts = <98>; 73 interrupts = <98>;
74 clocks = <&oscclk7>;
75 clock-names = "apb_pclk";
68 }; 76 };
69 77
70 gic: interrupt-controller@2c001000 { 78 gic: interrupt-controller@2c001000 {
@@ -84,6 +92,8 @@
84 reg = <0 0x7ffd0000 0 0x1000>; 92 reg = <0 0x7ffd0000 0 0x1000>;
85 interrupts = <0 86 4>, 93 interrupts = <0 86 4>,
86 <0 87 4>; 94 <0 87 4>;
95 clocks = <&oscclk7>;
96 clock-names = "apb_pclk";
87 }; 97 };
88 98
89 dma@7ffb0000 { 99 dma@7ffb0000 {
@@ -94,6 +104,8 @@
94 <0 89 4>, 104 <0 89 4>,
95 <0 90 4>, 105 <0 90 4>,
96 <0 91 4>; 106 <0 91 4>;
107 clocks = <&oscclk7>;
108 clock-names = "apb_pclk";
97 }; 109 };
98 110
99 timer { 111 timer {
@@ -110,6 +122,104 @@
110 <0 69 4>; 122 <0 69 4>;
111 }; 123 };
112 124
125 dcc {
126 compatible = "arm,vexpress,config-bus";
127 arm,vexpress,config-bridge = <&v2m_sysreg>;
128
129 osc@0 {
130 /* CPU PLL reference clock */
131 compatible = "arm,vexpress-osc";
132 arm,vexpress-sysreg,func = <1 0>;
133 freq-range = <50000000 60000000>;
134 #clock-cells = <0>;
135 clock-output-names = "oscclk0";
136 };
137
138 osc@4 {
139 /* Multiplexed AXI master clock */
140 compatible = "arm,vexpress-osc";
141 arm,vexpress-sysreg,func = <1 4>;
142 freq-range = <20000000 40000000>;
143 #clock-cells = <0>;
144 clock-output-names = "oscclk4";
145 };
146
147 oscclk5: osc@5 {
148 /* HDLCD PLL reference clock */
149 compatible = "arm,vexpress-osc";
150 arm,vexpress-sysreg,func = <1 5>;
151 freq-range = <23750000 165000000>;
152 #clock-cells = <0>;
153 clock-output-names = "oscclk5";
154 };
155
156 smbclk: osc@6 {
157 /* SMB clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 6>;
160 freq-range = <20000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk6";
163 };
164
165 oscclk7: osc@7 {
166 /* SYS PLL reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 7>;
169 freq-range = <20000000 60000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk7";
172 };
173
174 osc@8 {
175 /* DDR2 PLL reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 8>;
178 freq-range = <40000000 40000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk8";
181 };
182
183 volt@0 {
184 /* CPU core voltage */
185 compatible = "arm,vexpress-volt";
186 arm,vexpress-sysreg,func = <2 0>;
187 regulator-name = "Cores";
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <1050000>;
190 regulator-always-on;
191 label = "Cores";
192 };
193
194 amp@0 {
195 /* Total current for the two cores */
196 compatible = "arm,vexpress-amp";
197 arm,vexpress-sysreg,func = <3 0>;
198 label = "Cores";
199 };
200
201 temp@0 {
202 /* DCC internal temperature */
203 compatible = "arm,vexpress-temp";
204 arm,vexpress-sysreg,func = <4 0>;
205 label = "DCC";
206 };
207
208 power@0 {
209 /* Total power */
210 compatible = "arm,vexpress-power";
211 arm,vexpress-sysreg,func = <12 0>;
212 label = "Cores";
213 };
214
215 energy@0 {
216 /* Total energy */
217 compatible = "arm,vexpress-energy";
218 arm,vexpress-sysreg,func = <13 0>;
219 label = "Cores";
220 };
221 };
222
113 motherboard { 223 motherboard {
114 ranges = <0 0 0 0x08000000 0x04000000>, 224 ranges = <0 0 0 0x08000000 0x04000000>,
115 <1 0 0 0x14000000 0x04000000>, 225 <1 0 0 0x14000000 0x04000000>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 4890a81c5467..3f4e1d00f4be 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA15_CA7"; 13 model = "V2P-CA15_CA7";
14 arm,hbi = <0x249>; 14 arm,hbi = <0x249>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <2>; 18 #address-cells = <2>;
@@ -74,17 +75,23 @@
74 compatible = "arm,sp805", "arm,primecell"; 75 compatible = "arm,sp805", "arm,primecell";
75 reg = <0 0x2a490000 0 0x1000>; 76 reg = <0 0x2a490000 0 0x1000>;
76 interrupts = <98>; 77 interrupts = <98>;
78 clocks = <&oscclk6a>, <&oscclk6a>;
79 clock-names = "wdogclk", "apb_pclk";
77 }; 80 };
78 81
79 hdlcd@2b000000 { 82 hdlcd@2b000000 {
80 compatible = "arm,hdlcd"; 83 compatible = "arm,hdlcd";
81 reg = <0 0x2b000000 0 0x1000>; 84 reg = <0 0x2b000000 0 0x1000>;
82 interrupts = <0 85 4>; 85 interrupts = <0 85 4>;
86 clocks = <&oscclk5>;
87 clock-names = "pxlclk";
83 }; 88 };
84 89
85 memory-controller@2b0a0000 { 90 memory-controller@2b0a0000 {
86 compatible = "arm,pl341", "arm,primecell"; 91 compatible = "arm,pl341", "arm,primecell";
87 reg = <0 0x2b0a0000 0 0x1000>; 92 reg = <0 0x2b0a0000 0 0x1000>;
93 clocks = <&oscclk6a>;
94 clock-names = "apb_pclk";
88 }; 95 };
89 96
90 gic: interrupt-controller@2c001000 { 97 gic: interrupt-controller@2c001000 {
@@ -104,6 +111,8 @@
104 reg = <0 0x7ffd0000 0 0x1000>; 111 reg = <0 0x7ffd0000 0 0x1000>;
105 interrupts = <0 86 4>, 112 interrupts = <0 86 4>,
106 <0 87 4>; 113 <0 87 4>;
114 clocks = <&oscclk6a>;
115 clock-names = "apb_pclk";
107 }; 116 };
108 117
109 dma@7ff00000 { 118 dma@7ff00000 {
@@ -114,6 +123,8 @@
114 <0 89 4>, 123 <0 89 4>,
115 <0 90 4>, 124 <0 90 4>,
116 <0 91 4>; 125 <0 91 4>;
126 clocks = <&oscclk6a>;
127 clock-names = "apb_pclk";
117 }; 128 };
118 129
119 timer { 130 timer {
@@ -130,6 +141,170 @@
130 <0 69 4>; 141 <0 69 4>;
131 }; 142 };
132 143
144 oscclk6a: oscclk6a {
145 /* Reference 24MHz clock */
146 compatible = "fixed-clock";
147 #clock-cells = <0>;
148 clock-frequency = <24000000>;
149 clock-output-names = "oscclk6a";
150 };
151
152 dcc {
153 compatible = "arm,vexpress,config-bus";
154 arm,vexpress,config-bridge = <&v2m_sysreg>;
155
156 osc@0 {
157 /* A15 PLL 0 reference clock */
158 compatible = "arm,vexpress-osc";
159 arm,vexpress-sysreg,func = <1 0>;
160 freq-range = <17000000 50000000>;
161 #clock-cells = <0>;
162 clock-output-names = "oscclk0";
163 };
164
165 osc@1 {
166 /* A15 PLL 1 reference clock */
167 compatible = "arm,vexpress-osc";
168 arm,vexpress-sysreg,func = <1 1>;
169 freq-range = <17000000 50000000>;
170 #clock-cells = <0>;
171 clock-output-names = "oscclk1";
172 };
173
174 osc@2 {
175 /* A7 PLL 0 reference clock */
176 compatible = "arm,vexpress-osc";
177 arm,vexpress-sysreg,func = <1 2>;
178 freq-range = <17000000 50000000>;
179 #clock-cells = <0>;
180 clock-output-names = "oscclk2";
181 };
182
183 osc@3 {
184 /* A7 PLL 1 reference clock */
185 compatible = "arm,vexpress-osc";
186 arm,vexpress-sysreg,func = <1 3>;
187 freq-range = <17000000 50000000>;
188 #clock-cells = <0>;
189 clock-output-names = "oscclk3";
190 };
191
192 osc@4 {
193 /* External AXI master clock */
194 compatible = "arm,vexpress-osc";
195 arm,vexpress-sysreg,func = <1 4>;
196 freq-range = <20000000 40000000>;
197 #clock-cells = <0>;
198 clock-output-names = "oscclk4";
199 };
200
201 oscclk5: osc@5 {
202 /* HDLCD PLL reference clock */
203 compatible = "arm,vexpress-osc";
204 arm,vexpress-sysreg,func = <1 5>;
205 freq-range = <23750000 165000000>;
206 #clock-cells = <0>;
207 clock-output-names = "oscclk5";
208 };
209
210 smbclk: osc@6 {
211 /* Static memory controller clock */
212 compatible = "arm,vexpress-osc";
213 arm,vexpress-sysreg,func = <1 6>;
214 freq-range = <20000000 40000000>;
215 #clock-cells = <0>;
216 clock-output-names = "oscclk6";
217 };
218
219 osc@7 {
220 /* SYS PLL reference clock */
221 compatible = "arm,vexpress-osc";
222 arm,vexpress-sysreg,func = <1 7>;
223 freq-range = <17000000 50000000>;
224 #clock-cells = <0>;
225 clock-output-names = "oscclk7";
226 };
227
228 osc@8 {
229 /* DDR2 PLL reference clock */
230 compatible = "arm,vexpress-osc";
231 arm,vexpress-sysreg,func = <1 8>;
232 freq-range = <20000000 50000000>;
233 #clock-cells = <0>;
234 clock-output-names = "oscclk8";
235 };
236
237 volt@0 {
238 /* A15 CPU core voltage */
239 compatible = "arm,vexpress-volt";
240 arm,vexpress-sysreg,func = <2 0>;
241 regulator-name = "A15 Vcore";
242 regulator-min-microvolt = <800000>;
243 regulator-max-microvolt = <1050000>;
244 regulator-always-on;
245 label = "A15 Vcore";
246 };
247
248 volt@1 {
249 /* A7 CPU core voltage */
250 compatible = "arm,vexpress-volt";
251 arm,vexpress-sysreg,func = <2 1>;
252 regulator-name = "A7 Vcore";
253 regulator-min-microvolt = <800000>;
254 regulator-max-microvolt = <1050000>;
255 regulator-always-on;
256 label = "A7 Vcore";
257 };
258
259 amp@0 {
260 /* Total current for the two A15 cores */
261 compatible = "arm,vexpress-amp";
262 arm,vexpress-sysreg,func = <3 0>;
263 label = "A15 Icore";
264 };
265
266 amp@1 {
267 /* Total current for the three A7 cores */
268 compatible = "arm,vexpress-amp";
269 arm,vexpress-sysreg,func = <3 1>;
270 label = "A7 Icore";
271 };
272
273 temp@0 {
274 /* DCC internal temperature */
275 compatible = "arm,vexpress-temp";
276 arm,vexpress-sysreg,func = <4 0>;
277 label = "DCC";
278 };
279
280 power@0 {
281 /* Total power for the two A15 cores */
282 compatible = "arm,vexpress-power";
283 arm,vexpress-sysreg,func = <12 0>;
284 label = "A15 Pcore";
285 };
286 power@1 {
287 /* Total power for the three A7 cores */
288 compatible = "arm,vexpress-power";
289 arm,vexpress-sysreg,func = <12 1>;
290 label = "A7 Pcore";
291 };
292
293 energy@0 {
294 /* Total energy for the two A15 cores */
295 compatible = "arm,vexpress-energy";
296 arm,vexpress-sysreg,func = <13 0>;
297 label = "A15 Jcore";
298 };
299
300 energy@2 {
301 /* Total energy for the three A7 cores */
302 compatible = "arm,vexpress-energy";
303 arm,vexpress-sysreg,func = <13 2>;
304 label = "A7 Jcore";
305 };
306 };
307
133 motherboard { 308 motherboard {
134 ranges = <0 0 0 0x08000000 0x04000000>, 309 ranges = <0 0 0 0x08000000 0x04000000>,
135 <1 0 0 0x14000000 0x04000000>, 310 <1 0 0 0x14000000 0x04000000>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index 18917a0f8604..f3c1f2a44072 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA5s"; 13 model = "V2P-CA5s";
14 arm,hbi = <0x225>; 14 arm,hbi = <0x225>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <1>; 18 #address-cells = <1>;
@@ -56,11 +57,15 @@
56 compatible = "arm,hdlcd"; 57 compatible = "arm,hdlcd";
57 reg = <0x2a110000 0x1000>; 58 reg = <0x2a110000 0x1000>;
58 interrupts = <0 85 4>; 59 interrupts = <0 85 4>;
60 clocks = <&oscclk3>;
61 clock-names = "pxlclk";
59 }; 62 };
60 63
61 memory-controller@2a150000 { 64 memory-controller@2a150000 {
62 compatible = "arm,pl341", "arm,primecell"; 65 compatible = "arm,pl341", "arm,primecell";
63 reg = <0x2a150000 0x1000>; 66 reg = <0x2a150000 0x1000>;
67 clocks = <&oscclk1>;
68 clock-names = "apb_pclk";
64 }; 69 };
65 70
66 memory-controller@2a190000 { 71 memory-controller@2a190000 {
@@ -68,6 +73,8 @@
68 reg = <0x2a190000 0x1000>; 73 reg = <0x2a190000 0x1000>;
69 interrupts = <0 86 4>, 74 interrupts = <0 86 4>,
70 <0 87 4>; 75 <0 87 4>;
76 clocks = <&oscclk1>;
77 clock-names = "apb_pclk";
71 }; 78 };
72 79
73 scu@2c000000 { 80 scu@2c000000 {
@@ -109,6 +116,72 @@
109 <0 69 4>; 116 <0 69 4>;
110 }; 117 };
111 118
119 dcc {
120 compatible = "arm,vexpress,config-bus";
121 arm,vexpress,config-bridge = <&v2m_sysreg>;
122
123 osc@0 {
124 /* CPU and internal AXI reference clock */
125 compatible = "arm,vexpress-osc";
126 arm,vexpress-sysreg,func = <1 0>;
127 freq-range = <50000000 100000000>;
128 #clock-cells = <0>;
129 clock-output-names = "oscclk0";
130 };
131
132 oscclk1: osc@1 {
133 /* Multiplexed AXI master clock */
134 compatible = "arm,vexpress-osc";
135 arm,vexpress-sysreg,func = <1 1>;
136 freq-range = <5000000 50000000>;
137 #clock-cells = <0>;
138 clock-output-names = "oscclk1";
139 };
140
141 osc@2 {
142 /* DDR2 */
143 compatible = "arm,vexpress-osc";
144 arm,vexpress-sysreg,func = <1 2>;
145 freq-range = <80000000 120000000>;
146 #clock-cells = <0>;
147 clock-output-names = "oscclk2";
148 };
149
150 oscclk3: osc@3 {
151 /* HDLCD */
152 compatible = "arm,vexpress-osc";
153 arm,vexpress-sysreg,func = <1 3>;
154 freq-range = <23750000 165000000>;
155 #clock-cells = <0>;
156 clock-output-names = "oscclk3";
157 };
158
159 osc@4 {
160 /* Test chip gate configuration */
161 compatible = "arm,vexpress-osc";
162 arm,vexpress-sysreg,func = <1 4>;
163 freq-range = <80000000 80000000>;
164 #clock-cells = <0>;
165 clock-output-names = "oscclk4";
166 };
167
168 smbclk: osc@5 {
169 /* SMB clock */
170 compatible = "arm,vexpress-osc";
171 arm,vexpress-sysreg,func = <1 5>;
172 freq-range = <25000000 60000000>;
173 #clock-cells = <0>;
174 clock-output-names = "oscclk5";
175 };
176
177 temp@0 {
178 /* DCC internal operating temperature */
179 compatible = "arm,vexpress-temp";
180 arm,vexpress-sysreg,func = <4 0>;
181 label = "DCC";
182 };
183 };
184
112 motherboard { 185 motherboard {
113 ranges = <0 0 0x08000000 0x04000000>, 186 ranges = <0 0 0x08000000 0x04000000>,
114 <1 0 0x14000000 0x04000000>, 187 <1 0 0x14000000 0x04000000>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
index 3f0c736d31d6..005259db541d 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts
@@ -12,6 +12,7 @@
12/ { 12/ {
13 model = "V2P-CA9"; 13 model = "V2P-CA9";
14 arm,hbi = <0x191>; 14 arm,hbi = <0x191>;
15 arm,vexpress,site = <0xf>;
15 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress"; 16 compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
16 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
17 #address-cells = <1>; 18 #address-cells = <1>;
@@ -70,11 +71,15 @@
70 compatible = "arm,pl111", "arm,primecell"; 71 compatible = "arm,pl111", "arm,primecell";
71 reg = <0x10020000 0x1000>; 72 reg = <0x10020000 0x1000>;
72 interrupts = <0 44 4>; 73 interrupts = <0 44 4>;
74 clocks = <&oscclk1>, <&oscclk2>;
75 clock-names = "clcdclk", "apb_pclk";
73 }; 76 };
74 77
75 memory-controller@100e0000 { 78 memory-controller@100e0000 {
76 compatible = "arm,pl341", "arm,primecell"; 79 compatible = "arm,pl341", "arm,primecell";
77 reg = <0x100e0000 0x1000>; 80 reg = <0x100e0000 0x1000>;
81 clocks = <&oscclk2>;
82 clock-names = "apb_pclk";
78 }; 83 };
79 84
80 memory-controller@100e1000 { 85 memory-controller@100e1000 {
@@ -82,6 +87,8 @@
82 reg = <0x100e1000 0x1000>; 87 reg = <0x100e1000 0x1000>;
83 interrupts = <0 45 4>, 88 interrupts = <0 45 4>,
84 <0 46 4>; 89 <0 46 4>;
90 clocks = <&oscclk2>;
91 clock-names = "apb_pclk";
85 }; 92 };
86 93
87 timer@100e4000 { 94 timer@100e4000 {
@@ -89,12 +96,16 @@
89 reg = <0x100e4000 0x1000>; 96 reg = <0x100e4000 0x1000>;
90 interrupts = <0 48 4>, 97 interrupts = <0 48 4>,
91 <0 49 4>; 98 <0 49 4>;
99 clocks = <&oscclk2>, <&oscclk2>;
100 clock-names = "timclk", "apb_pclk";
92 }; 101 };
93 102
94 watchdog@100e5000 { 103 watchdog@100e5000 {
95 compatible = "arm,sp805", "arm,primecell"; 104 compatible = "arm,sp805", "arm,primecell";
96 reg = <0x100e5000 0x1000>; 105 reg = <0x100e5000 0x1000>;
97 interrupts = <0 51 4>; 106 interrupts = <0 51 4>;
107 clocks = <&oscclk2>, <&oscclk2>;
108 clock-names = "wdogclk", "apb_pclk";
98 }; 109 };
99 110
100 scu@1e000000 { 111 scu@1e000000 {
@@ -140,6 +151,120 @@
140 <0 63 4>; 151 <0 63 4>;
141 }; 152 };
142 153
154 dcc {
155 compatible = "arm,vexpress,config-bus";
156 arm,vexpress,config-bridge = <&v2m_sysreg>;
157
158 osc@0 {
159 /* ACLK clock to the AXI master port on the test chip */
160 compatible = "arm,vexpress-osc";
161 arm,vexpress-sysreg,func = <1 0>;
162 freq-range = <30000000 50000000>;
163 #clock-cells = <0>;
164 clock-output-names = "extsaxiclk";
165 };
166
167 oscclk1: osc@1 {
168 /* Reference clock for the CLCD */
169 compatible = "arm,vexpress-osc";
170 arm,vexpress-sysreg,func = <1 1>;
171 freq-range = <10000000 80000000>;
172 #clock-cells = <0>;
173 clock-output-names = "clcdclk";
174 };
175
176 smbclk: oscclk2: osc@2 {
177 /* Reference clock for the test chip internal PLLs */
178 compatible = "arm,vexpress-osc";
179 arm,vexpress-sysreg,func = <1 2>;
180 freq-range = <33000000 100000000>;
181 #clock-cells = <0>;
182 clock-output-names = "tcrefclk";
183 };
184
185 volt@0 {
186 /* Test Chip internal logic voltage */
187 compatible = "arm,vexpress-volt";
188 arm,vexpress-sysreg,func = <2 0>;
189 regulator-name = "VD10";
190 regulator-always-on;
191 label = "VD10";
192 };
193
194 volt@1 {
195 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
196 compatible = "arm,vexpress-volt";
197 arm,vexpress-sysreg,func = <2 1>;
198 regulator-name = "VD10_S2";
199 regulator-always-on;
200 label = "VD10_S2";
201 };
202
203 volt@2 {
204 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
205 compatible = "arm,vexpress-volt";
206 arm,vexpress-sysreg,func = <2 2>;
207 regulator-name = "VD10_S3";
208 regulator-always-on;
209 label = "VD10_S3";
210 };
211
212 volt@3 {
213 /* DDR2 SDRAM and Test Chip DDR2 I/O supply */
214 compatible = "arm,vexpress-volt";
215 arm,vexpress-sysreg,func = <2 3>;
216 regulator-name = "VCC1V8";
217 regulator-always-on;
218 label = "VCC1V8";
219 };
220
221 volt@4 {
222 /* DDR2 SDRAM VTT termination voltage */
223 compatible = "arm,vexpress-volt";
224 arm,vexpress-sysreg,func = <2 4>;
225 regulator-name = "DDR2VTT";
226 regulator-always-on;
227 label = "DDR2VTT";
228 };
229
230 volt@5 {
231 /* Local board supply for miscellaneous logic external to the Test Chip */
232 arm,vexpress-sysreg,func = <2 5>;
233 compatible = "arm,vexpress-volt";
234 regulator-name = "VCC3V3";
235 regulator-always-on;
236 label = "VCC3V3";
237 };
238
239 amp@0 {
240 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
241 compatible = "arm,vexpress-amp";
242 arm,vexpress-sysreg,func = <3 0>;
243 label = "VD10_S2";
244 };
245
246 amp@1 {
247 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
248 compatible = "arm,vexpress-amp";
249 arm,vexpress-sysreg,func = <3 1>;
250 label = "VD10_S3";
251 };
252
253 power@0 {
254 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
255 compatible = "arm,vexpress-power";
256 arm,vexpress-sysreg,func = <12 0>;
257 label = "PVD10_S2";
258 };
259
260 power@1 {
261 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
262 compatible = "arm,vexpress-power";
263 arm,vexpress-sysreg,func = <12 1>;
264 label = "PVD10_S3";
265 };
266 };
267
143 motherboard { 268 motherboard {
144 ranges = <0 0 0x40000000 0x04000000>, 269 ranges = <0 0 0x40000000 0x04000000>,
145 <1 0 0x44000000 0x04000000>, 270 <1 0 0x44000000 0x04000000>,
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 18:45:41 -0500