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-rw-r--r--drivers/mmc/host/sdhci-acpi.c1
-rw-r--r--drivers/mmc/host/sdhci.h203
-rw-r--r--include/linux/mmc/sdhci.h220
3 files changed, 202 insertions, 222 deletions
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index a45ed39d062c..22d929fa3371 100644
--- a/drivers/mmc/host/sdhci-acpi.c
+++ b/drivers/mmc/host/sdhci-acpi.c
@@ -40,7 +40,6 @@
40#include <linux/mmc/host.h> 40#include <linux/mmc/host.h>
41#include <linux/mmc/pm.h> 41#include <linux/mmc/pm.h>
42#include <linux/mmc/slot-gpio.h> 42#include <linux/mmc/slot-gpio.h>
43#include <linux/mmc/sdhci.h>
44 43
45#include "sdhci.h" 44#include "sdhci.h"
46 45
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 0315e1844330..e639b7f435e5 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -18,7 +18,7 @@
18#include <linux/types.h> 18#include <linux/types.h>
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include <linux/mmc/sdhci.h> 21#include <linux/mmc/host.h>
22 22
23/* 23/*
24 * Controller registers 24 * Controller registers
@@ -309,6 +309,207 @@ struct sdhci_adma2_64_desc {
309 */ 309 */
310#define SDHCI_MAX_SEGS 128 310#define SDHCI_MAX_SEGS 128
311 311
312struct sdhci_host_next {
313 unsigned int sg_count;
314 s32 cookie;
315};
316
317struct sdhci_host {
318 /* Data set by hardware interface driver */
319 const char *hw_name; /* Hardware bus name */
320
321 unsigned int quirks; /* Deviations from spec. */
322
323/* Controller doesn't honor resets unless we touch the clock register */
324#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
325/* Controller has bad caps bits, but really supports DMA */
326#define SDHCI_QUIRK_FORCE_DMA (1<<1)
327/* Controller doesn't like to be reset when there is no card inserted. */
328#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
329/* Controller doesn't like clearing the power reg before a change */
330#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
331/* Controller has flaky internal state so reset it on each ios change */
332#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
333/* Controller has an unusable DMA engine */
334#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
335/* Controller has an unusable ADMA engine */
336#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
337/* Controller can only DMA from 32-bit aligned addresses */
338#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
339/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
340#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
341/* Controller can only ADMA chunks that are a multiple of 32 bits */
342#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
343/* Controller needs to be reset after each request to stay stable */
344#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
345/* Controller needs voltage and power writes to happen separately */
346#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
347/* Controller provides an incorrect timeout value for transfers */
348#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
349/* Controller has an issue with buffer bits for small transfers */
350#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
351/* Controller does not provide transfer-complete interrupt when not busy */
352#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
353/* Controller has unreliable card detection */
354#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
355/* Controller reports inverted write-protect state */
356#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
357/* Controller does not like fast PIO transfers */
358#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
359/* Controller has to be forced to use block size of 2048 bytes */
360#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
361/* Controller cannot do multi-block transfers */
362#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
363/* Controller can only handle 1-bit data transfers */
364#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
365/* Controller needs 10ms delay between applying power and clock */
366#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
367/* Controller uses SDCLK instead of TMCLK for data timeouts */
368#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
369/* Controller reports wrong base clock capability */
370#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
371/* Controller cannot support End Attribute in NOP ADMA descriptor */
372#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
373/* Controller is missing device caps. Use caps provided by host */
374#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
375/* Controller uses Auto CMD12 command to stop the transfer */
376#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
377/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
378#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
379/* Controller treats ADMA descriptors with length 0000h incorrectly */
380#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
381/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
382#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
383
384 unsigned int quirks2; /* More deviations from spec. */
385
386#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
387#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
388/* The system physically doesn't support 1.8v, even if the host does */
389#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
390#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
391#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
392/* Controller has a non-standard host control register */
393#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
394/* Controller does not support HS200 */
395#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
396/* Controller does not support DDR50 */
397#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
398/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
399#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
400/* Controller does not support 64-bit DMA */
401#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
402/* need clear transfer mode register before send cmd */
403#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
404/* Capability register bit-63 indicates HS400 support */
405#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
406/* forced tuned clock */
407#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
408/* disable the block count for single block transactions */
409#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
410/* Controller broken with using ACMD23 */
411#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
412
413 int irq; /* Device IRQ */
414 void __iomem *ioaddr; /* Mapped address */
415
416 const struct sdhci_ops *ops; /* Low level hw interface */
417
418 /* Internal data */
419 struct mmc_host *mmc; /* MMC structure */
420 u64 dma_mask; /* custom DMA mask */
421
422#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
423 struct led_classdev led; /* LED control */
424 char led_name[32];
425#endif
426
427 spinlock_t lock; /* Mutex */
428
429 int flags; /* Host attributes */
430#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
431#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
432#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
433#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
434#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
435#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
436#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
437#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
438#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
439#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
440#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
441#define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
442#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
443#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
444
445 unsigned int version; /* SDHCI spec. version */
446
447 unsigned int max_clk; /* Max possible freq (MHz) */
448 unsigned int timeout_clk; /* Timeout freq (KHz) */
449 unsigned int clk_mul; /* Clock Muliplier value */
450
451 unsigned int clock; /* Current clock (MHz) */
452 u8 pwr; /* Current voltage */
453
454 bool runtime_suspended; /* Host is runtime suspended */
455 bool bus_on; /* Bus power prevents runtime suspend */
456 bool preset_enabled; /* Preset is enabled */
457
458 struct mmc_request *mrq; /* Current request */
459 struct mmc_command *cmd; /* Current command */
460 struct mmc_data *data; /* Current data request */
461 unsigned int data_early:1; /* Data finished before cmd */
462 unsigned int busy_handle:1; /* Handling the order of Busy-end */
463
464 struct sg_mapping_iter sg_miter; /* SG state for PIO */
465 unsigned int blocks; /* remaining PIO blocks */
466
467 int sg_count; /* Mapped sg entries */
468
469 void *adma_table; /* ADMA descriptor table */
470 void *align_buffer; /* Bounce buffer */
471
472 size_t adma_table_sz; /* ADMA descriptor table size */
473 size_t align_buffer_sz; /* Bounce buffer size */
474
475 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
476 dma_addr_t align_addr; /* Mapped bounce buffer */
477
478 unsigned int desc_sz; /* ADMA descriptor size */
479 unsigned int align_sz; /* ADMA alignment */
480 unsigned int align_mask; /* ADMA alignment mask */
481
482 struct tasklet_struct finish_tasklet; /* Tasklet structures */
483
484 struct timer_list timer; /* Timer for timeouts */
485
486 u32 caps; /* Alternative CAPABILITY_0 */
487 u32 caps1; /* Alternative CAPABILITY_1 */
488
489 unsigned int ocr_avail_sdio; /* OCR bit masks */
490 unsigned int ocr_avail_sd;
491 unsigned int ocr_avail_mmc;
492 u32 ocr_mask; /* available voltages */
493
494 unsigned timing; /* Current timing */
495
496 u32 thread_isr;
497
498 /* cached registers */
499 u32 ier;
500
501 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
502 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
503
504 unsigned int tuning_count; /* Timer count for re-tuning */
505 unsigned int tuning_mode; /* Re-tuning mode supported by host */
506#define SDHCI_TUNING_MODE_1 0
507 struct timer_list tuning_timer; /* Timer for tuning */
508
509 struct sdhci_host_next next_data;
510 unsigned long private[0] ____cacheline_aligned;
511};
512
312struct sdhci_ops { 513struct sdhci_ops {
313#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS 514#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
314 u32 (*read_l)(struct sdhci_host *host, int reg); 515 u32 (*read_l)(struct sdhci_host *host, int reg);
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
deleted file mode 100644
index 1bafb1e7716e..000000000000
--- a/include/linux/mmc/sdhci.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * linux/include/linux/mmc/sdhci.h - Secure Digital Host Controller Interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 */
11#ifndef LINUX_MMC_SDHCI_H
12#define LINUX_MMC_SDHCI_H
13
14#include <linux/scatterlist.h>
15#include <linux/compiler.h>
16#include <linux/types.h>
17#include <linux/io.h>
18#include <linux/mmc/host.h>
19
20struct sdhci_host_next {
21 unsigned int sg_count;
22 s32 cookie;
23};
24
25struct sdhci_host {
26 /* Data set by hardware interface driver */
27 const char *hw_name; /* Hardware bus name */
28
29 unsigned int quirks; /* Deviations from spec. */
30
31/* Controller doesn't honor resets unless we touch the clock register */
32#define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
33/* Controller has bad caps bits, but really supports DMA */
34#define SDHCI_QUIRK_FORCE_DMA (1<<1)
35/* Controller doesn't like to be reset when there is no card inserted. */
36#define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
37/* Controller doesn't like clearing the power reg before a change */
38#define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
39/* Controller has flaky internal state so reset it on each ios change */
40#define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
41/* Controller has an unusable DMA engine */
42#define SDHCI_QUIRK_BROKEN_DMA (1<<5)
43/* Controller has an unusable ADMA engine */
44#define SDHCI_QUIRK_BROKEN_ADMA (1<<6)
45/* Controller can only DMA from 32-bit aligned addresses */
46#define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<7)
47/* Controller can only DMA chunk sizes that are a multiple of 32 bits */
48#define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<8)
49/* Controller can only ADMA chunks that are a multiple of 32 bits */
50#define SDHCI_QUIRK_32BIT_ADMA_SIZE (1<<9)
51/* Controller needs to be reset after each request to stay stable */
52#define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<10)
53/* Controller needs voltage and power writes to happen separately */
54#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1<<11)
55/* Controller provides an incorrect timeout value for transfers */
56#define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1<<12)
57/* Controller has an issue with buffer bits for small transfers */
58#define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13)
59/* Controller does not provide transfer-complete interrupt when not busy */
60#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<14)
61/* Controller has unreliable card detection */
62#define SDHCI_QUIRK_BROKEN_CARD_DETECTION (1<<15)
63/* Controller reports inverted write-protect state */
64#define SDHCI_QUIRK_INVERTED_WRITE_PROTECT (1<<16)
65/* Controller does not like fast PIO transfers */
66#define SDHCI_QUIRK_PIO_NEEDS_DELAY (1<<18)
67/* Controller has to be forced to use block size of 2048 bytes */
68#define SDHCI_QUIRK_FORCE_BLK_SZ_2048 (1<<20)
69/* Controller cannot do multi-block transfers */
70#define SDHCI_QUIRK_NO_MULTIBLOCK (1<<21)
71/* Controller can only handle 1-bit data transfers */
72#define SDHCI_QUIRK_FORCE_1_BIT_DATA (1<<22)
73/* Controller needs 10ms delay between applying power and clock */
74#define SDHCI_QUIRK_DELAY_AFTER_POWER (1<<23)
75/* Controller uses SDCLK instead of TMCLK for data timeouts */
76#define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1<<24)
77/* Controller reports wrong base clock capability */
78#define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN (1<<25)
79/* Controller cannot support End Attribute in NOP ADMA descriptor */
80#define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC (1<<26)
81/* Controller is missing device caps. Use caps provided by host */
82#define SDHCI_QUIRK_MISSING_CAPS (1<<27)
83/* Controller uses Auto CMD12 command to stop the transfer */
84#define SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 (1<<28)
85/* Controller doesn't have HISPD bit field in HI-SPEED SD card */
86#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
87/* Controller treats ADMA descriptors with length 0000h incorrectly */
88#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
89/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
90#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
91
92 unsigned int quirks2; /* More deviations from spec. */
93
94#define SDHCI_QUIRK2_HOST_OFF_CARD_ON (1<<0)
95#define SDHCI_QUIRK2_HOST_NO_CMD23 (1<<1)
96/* The system physically doesn't support 1.8v, even if the host does */
97#define SDHCI_QUIRK2_NO_1_8_V (1<<2)
98#define SDHCI_QUIRK2_PRESET_VALUE_BROKEN (1<<3)
99#define SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON (1<<4)
100/* Controller has a non-standard host control register */
101#define SDHCI_QUIRK2_BROKEN_HOST_CONTROL (1<<5)
102/* Controller does not support HS200 */
103#define SDHCI_QUIRK2_BROKEN_HS200 (1<<6)
104/* Controller does not support DDR50 */
105#define SDHCI_QUIRK2_BROKEN_DDR50 (1<<7)
106/* Stop command (CMD12) can set Transfer Complete when not using MMC_RSP_BUSY */
107#define SDHCI_QUIRK2_STOP_WITH_TC (1<<8)
108/* Controller does not support 64-bit DMA */
109#define SDHCI_QUIRK2_BROKEN_64_BIT_DMA (1<<9)
110/* need clear transfer mode register before send cmd */
111#define SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD (1<<10)
112/* Capability register bit-63 indicates HS400 support */
113#define SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 (1<<11)
114/* forced tuned clock */
115#define SDHCI_QUIRK2_TUNING_WORK_AROUND (1<<12)
116/* disable the block count for single block transactions */
117#define SDHCI_QUIRK2_SUPPORT_SINGLE (1<<13)
118/* Controller broken with using ACMD23 */
119#define SDHCI_QUIRK2_ACMD23_BROKEN (1<<14)
120
121 int irq; /* Device IRQ */
122 void __iomem *ioaddr; /* Mapped address */
123
124 const struct sdhci_ops *ops; /* Low level hw interface */
125
126 /* Internal data */
127 struct mmc_host *mmc; /* MMC structure */
128 u64 dma_mask; /* custom DMA mask */
129
130#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
131 struct led_classdev led; /* LED control */
132 char led_name[32];
133#endif
134
135 spinlock_t lock; /* Mutex */
136
137 int flags; /* Host attributes */
138#define SDHCI_USE_SDMA (1<<0) /* Host is SDMA capable */
139#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
140#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
141#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
142#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
143#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
144#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
145#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
146#define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */
147#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
148#define SDHCI_SDR104_NEEDS_TUNING (1<<10) /* SDR104/HS200 needs tuning */
149#define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
150#define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
151#define SDHCI_HS400_TUNING (1<<13) /* Tuning for HS400 */
152
153 unsigned int version; /* SDHCI spec. version */
154
155 unsigned int max_clk; /* Max possible freq (MHz) */
156 unsigned int timeout_clk; /* Timeout freq (KHz) */
157 unsigned int clk_mul; /* Clock Muliplier value */
158
159 unsigned int clock; /* Current clock (MHz) */
160 u8 pwr; /* Current voltage */
161
162 bool runtime_suspended; /* Host is runtime suspended */
163 bool bus_on; /* Bus power prevents runtime suspend */
164 bool preset_enabled; /* Preset is enabled */
165
166 struct mmc_request *mrq; /* Current request */
167 struct mmc_command *cmd; /* Current command */
168 struct mmc_data *data; /* Current data request */
169 unsigned int data_early:1; /* Data finished before cmd */
170 unsigned int busy_handle:1; /* Handling the order of Busy-end */
171
172 struct sg_mapping_iter sg_miter; /* SG state for PIO */
173 unsigned int blocks; /* remaining PIO blocks */
174
175 int sg_count; /* Mapped sg entries */
176
177 void *adma_table; /* ADMA descriptor table */
178 void *align_buffer; /* Bounce buffer */
179
180 size_t adma_table_sz; /* ADMA descriptor table size */
181 size_t align_buffer_sz; /* Bounce buffer size */
182
183 dma_addr_t adma_addr; /* Mapped ADMA descr. table */
184 dma_addr_t align_addr; /* Mapped bounce buffer */
185
186 unsigned int desc_sz; /* ADMA descriptor size */
187 unsigned int align_sz; /* ADMA alignment */
188 unsigned int align_mask; /* ADMA alignment mask */
189
190 struct tasklet_struct finish_tasklet; /* Tasklet structures */
191
192 struct timer_list timer; /* Timer for timeouts */
193
194 u32 caps; /* Alternative CAPABILITY_0 */
195 u32 caps1; /* Alternative CAPABILITY_1 */
196
197 unsigned int ocr_avail_sdio; /* OCR bit masks */
198 unsigned int ocr_avail_sd;
199 unsigned int ocr_avail_mmc;
200 u32 ocr_mask; /* available voltages */
201
202 unsigned timing; /* Current timing */
203
204 u32 thread_isr;
205
206 /* cached registers */
207 u32 ier;
208
209 wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
210 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
211
212 unsigned int tuning_count; /* Timer count for re-tuning */
213 unsigned int tuning_mode; /* Re-tuning mode supported by host */
214#define SDHCI_TUNING_MODE_1 0
215 struct timer_list tuning_timer; /* Timer for tuning */
216
217 struct sdhci_host_next next_data;
218 unsigned long private[0] ____cacheline_aligned;
219};
220#endif /* LINUX_MMC_SDHCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-13 21:43:38 -0400