1 files changed, 4 insertions, 4 deletions

diff --git a/drivers/staging/dgnc/dgnc_cls.c b/drivers/staging/dgnc/dgnc_cls.c
index 4b65306b22ac..5a76a8e2f6cf 100644
--- a/drivers/staging/dgnc/dgnc_cls.c
+++ b/drivers/staging/dgnc/dgnc_cls.c
@@ -1040,11 +1040,11 @@ static void cls_flush_uart_read(struct channel_t *ch)
          * For complete POSIX compatibility, we should be purging the
          * read FIFO in the UART here.
          *
-         * However, doing the statement below also incorrectly flushes
-         * write data as well as just basically trashing the FIFO.
+         * However, clearing the read FIFO (UART_FCR_CLEAR_RCVR) also
+         * incorrectly flushes write data as well as just basically trashing the
+         * FIFO.
          *
-         * I believe this is a BUG in this UART.
-         * So for now, we will leave the code #ifdef'ed out...
+         * Presumably, this is a bug in this UART.
          */
 
         udelay(10);