diff options
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.c | 6 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 20 |
3 files changed, 42 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 1a7559b59997..c7d689e4247c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c | |||
@@ -66,7 +66,11 @@ MODULE_PARM_DESC(semaphores, | |||
66 | int i915_enable_rc6 __read_mostly = -1; | 66 | int i915_enable_rc6 __read_mostly = -1; |
67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
68 | MODULE_PARM_DESC(i915_enable_rc6, | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
69 | "Enable power-saving render C-state 6 (default: -1 (use per-chip default)"); | 69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | ||
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | ||
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | ||
73 | "default: -1 (use per-chip default)"); | ||
70 | 74 | ||
71 | int i915_enable_fbc __read_mostly = -1; | 75 | int i915_enable_fbc __read_mostly = -1; |
72 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c0f19f572004..2c192270cb0d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1053,6 +1053,27 @@ struct drm_i915_file_private { | |||
1053 | 1053 | ||
1054 | #include "i915_trace.h" | 1054 | #include "i915_trace.h" |
1055 | 1055 | ||
1056 | /** | ||
1057 | * RC6 is a special power stage which allows the GPU to enter an very | ||
1058 | * low-voltage mode when idle, using down to 0V while at this stage. This | ||
1059 | * stage is entered automatically when the GPU is idle when RC6 support is | ||
1060 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | ||
1061 | * | ||
1062 | * There are different RC6 modes available in Intel GPU, which differentiate | ||
1063 | * among each other with the latency required to enter and leave RC6 and | ||
1064 | * voltage consumed by the GPU in different states. | ||
1065 | * | ||
1066 | * The combination of the following flags define which states GPU is allowed | ||
1067 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | ||
1068 | * RC6pp is deepest RC6. Their support by hardware varies according to the | ||
1069 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | ||
1070 | * which brings the most power savings; deeper states save more power, but | ||
1071 | * require higher latency to switch to and wake up. | ||
1072 | */ | ||
1073 | #define INTEL_RC6_ENABLE (1<<0) | ||
1074 | #define INTEL_RC6p_ENABLE (1<<1) | ||
1075 | #define INTEL_RC6pp_ENABLE (1<<2) | ||
1076 | |||
1056 | extern struct drm_ioctl_desc i915_ioctls[]; | 1077 | extern struct drm_ioctl_desc i915_ioctls[]; |
1057 | extern int i915_max_ioctl; | 1078 | extern int i915_max_ioctl; |
1058 | extern unsigned int i915_fbpercrtc __always_unused; | 1079 | extern unsigned int i915_fbpercrtc __always_unused; |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 078477306975..a0a4e3bcbcf6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -8221,7 +8221,7 @@ void intel_init_emon(struct drm_device *dev) | |||
8221 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); | 8221 | dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); |
8222 | } | 8222 | } |
8223 | 8223 | ||
8224 | static bool intel_enable_rc6(struct drm_device *dev) | 8224 | static int intel_enable_rc6(struct drm_device *dev) |
8225 | { | 8225 | { |
8226 | /* | 8226 | /* |
8227 | * Respect the kernel parameter if it is set | 8227 | * Respect the kernel parameter if it is set |
@@ -8253,6 +8253,7 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
8253 | u32 pcu_mbox, rc6_mask = 0; | 8253 | u32 pcu_mbox, rc6_mask = 0; |
8254 | u32 gtfifodbg; | 8254 | u32 gtfifodbg; |
8255 | int cur_freq, min_freq, max_freq; | 8255 | int cur_freq, min_freq, max_freq; |
8256 | int rc6_mode; | ||
8256 | int i; | 8257 | int i; |
8257 | 8258 | ||
8258 | /* Here begins a magic sequence of register writes to enable | 8259 | /* Here begins a magic sequence of register writes to enable |
@@ -8290,9 +8291,20 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) | |||
8290 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); | 8291 | I915_WRITE(GEN6_RC6p_THRESHOLD, 100000); |
8291 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ | 8292 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
8292 | 8293 | ||
8293 | if (intel_enable_rc6(dev_priv->dev)) | 8294 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
8294 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE | | 8295 | if (rc6_mode & INTEL_RC6_ENABLE) |
8295 | ((IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0); | 8296 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
8297 | |||
8298 | if (rc6_mode & INTEL_RC6p_ENABLE) | ||
8299 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | ||
8300 | |||
8301 | if (rc6_mode & INTEL_RC6pp_ENABLE) | ||
8302 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | ||
8303 | |||
8304 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", | ||
8305 | (rc6_mode & INTEL_RC6_ENABLE) ? "on" : "off", | ||
8306 | (rc6_mode & INTEL_RC6p_ENABLE) ? "on" : "off", | ||
8307 | (rc6_mode & INTEL_RC6pp_ENABLE) ? "on" : "off"); | ||
8296 | 8308 | ||
8297 | I915_WRITE(GEN6_RC_CONTROL, | 8309 | I915_WRITE(GEN6_RC_CONTROL, |
8298 | rc6_mask | | 8310 | rc6_mask | |