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-rw-r--r--Documentation/networking/gianfar.txt30
-rw-r--r--drivers/net/ethernet/freescale/Makefile3
-rw-r--r--drivers/net/ethernet/freescale/gianfar.c500
-rw-r--r--drivers/net/ethernet/freescale/gianfar.h44
-rw-r--r--drivers/net/ethernet/freescale/gianfar_ethtool.c64
-rw-r--r--drivers/net/ethernet/freescale/gianfar_sysfs.c340
6 files changed, 278 insertions, 703 deletions
diff --git a/Documentation/networking/gianfar.txt b/Documentation/networking/gianfar.txt
index ad474ea07d07..ba1daea7f2e4 100644
--- a/Documentation/networking/gianfar.txt
+++ b/Documentation/networking/gianfar.txt
@@ -1,38 +1,8 @@
1The Gianfar Ethernet Driver 1The Gianfar Ethernet Driver
2Sysfs File description
3 2
4Author: Andy Fleming <afleming@freescale.com> 3Author: Andy Fleming <afleming@freescale.com>
5Updated: 2005-07-28 4Updated: 2005-07-28
6 5
7SYSFS
8
9Several of the features of the gianfar driver are controlled
10through sysfs files. These are:
11
12bd_stash:
13To stash RX Buffer Descriptors in the L2, echo 'on' or '1' to
14bd_stash, echo 'off' or '0' to disable
15
16rx_stash_len:
17To stash the first n bytes of the packet in L2, echo the number
18of bytes to buf_stash_len. echo 0 to disable.
19
20WARNING: You could really screw these up if you set them too low or high!
21fifo_threshold:
22To change the number of bytes the controller needs in the
23fifo before it starts transmission, echo the number of bytes to
24fifo_thresh. Range should be 0-511.
25
26fifo_starve:
27When the FIFO has less than this many bytes during a transmit, it
28enters starve mode, and increases the priority of TX memory
29transactions. To change, echo the number of bytes to
30fifo_starve. Range should be 0-511.
31
32fifo_starve_off:
33Once in starve mode, the FIFO remains there until it has this
34many bytes. To change, echo the number of bytes to
35fifo_starve_off. Range should be 0-511.
36 6
37CHECKSUM OFFLOADING 7CHECKSUM OFFLOADING
38 8
diff --git a/drivers/net/ethernet/freescale/Makefile b/drivers/net/ethernet/freescale/Makefile
index 549ce13b92ac..71debd1c18c9 100644
--- a/drivers/net/ethernet/freescale/Makefile
+++ b/drivers/net/ethernet/freescale/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_FSL_XGMAC_MDIO) += xgmac_mdio.o
14obj-$(CONFIG_GIANFAR) += gianfar_driver.o 14obj-$(CONFIG_GIANFAR) += gianfar_driver.o
15obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o 15obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
16gianfar_driver-objs := gianfar.o \ 16gianfar_driver-objs := gianfar.o \
17 gianfar_ethtool.o \ 17 gianfar_ethtool.o
18 gianfar_sysfs.o
19obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o 18obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
20ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o 19ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
diff --git a/drivers/net/ethernet/freescale/gianfar.c b/drivers/net/ethernet/freescale/gianfar.c
index ad5a5aadc7e1..a2977a8df645 100644
--- a/drivers/net/ethernet/freescale/gianfar.c
+++ b/drivers/net/ethernet/freescale/gianfar.c
@@ -9,7 +9,7 @@
9 * Maintainer: Kumar Gala 9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 * 11 *
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * Copyright 2007 MontaVista Software, Inc. 13 * Copyright 2007 MontaVista Software, Inc.
14 * 14 *
15 * This program is free software; you can redistribute it and/or modify it 15 * This program is free software; you can redistribute it and/or modify it
@@ -138,9 +138,7 @@ int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
138static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue); 138static void gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
139static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb, 139static void gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
140 int amount_pull, struct napi_struct *napi); 140 int amount_pull, struct napi_struct *napi);
141void gfar_halt(struct net_device *dev); 141static void gfar_halt_nodisable(struct gfar_private *priv);
142static void gfar_halt_nodisable(struct net_device *dev);
143void gfar_start(struct net_device *dev);
144static void gfar_clear_exact_match(struct net_device *dev); 142static void gfar_clear_exact_match(struct net_device *dev);
145static void gfar_set_mac_for_addr(struct net_device *dev, int num, 143static void gfar_set_mac_for_addr(struct net_device *dev, int num,
146 const u8 *addr); 144 const u8 *addr);
@@ -338,7 +336,6 @@ static void gfar_init_mac(struct net_device *ndev)
338 struct gfar __iomem *regs = priv->gfargrp[0].regs; 336 struct gfar __iomem *regs = priv->gfargrp[0].regs;
339 u32 rctrl = 0; 337 u32 rctrl = 0;
340 u32 tctrl = 0; 338 u32 tctrl = 0;
341 u32 attrs = 0;
342 339
343 /* write the tx/rx base registers */ 340 /* write the tx/rx base registers */
344 gfar_init_tx_rx_base(priv); 341 gfar_init_tx_rx_base(priv);
@@ -376,13 +373,6 @@ static void gfar_init_mac(struct net_device *ndev)
376 rctrl |= RCTRL_PADDING(priv->padding); 373 rctrl |= RCTRL_PADDING(priv->padding);
377 } 374 }
378 375
379 /* Insert receive time stamps into padding alignment bytes */
380 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
381 rctrl &= ~RCTRL_PAL_MASK;
382 rctrl |= RCTRL_PADDING(8);
383 priv->padding = 8;
384 }
385
386 /* Enable HW time stamping if requested from user space */ 376 /* Enable HW time stamping if requested from user space */
387 if (priv->hwts_rx_en) { 377 if (priv->hwts_rx_en) {
388 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE; 378 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
@@ -409,29 +399,6 @@ static void gfar_init_mac(struct net_device *ndev)
409 } 399 }
410 400
411 gfar_write(&regs->tctrl, tctrl); 401 gfar_write(&regs->tctrl, tctrl);
412
413 /* Set the extraction length and index */
414 attrs = ATTRELI_EL(priv->rx_stash_size) |
415 ATTRELI_EI(priv->rx_stash_index);
416
417 gfar_write(&regs->attreli, attrs);
418
419 /* Start with defaults, and add stashing or locking
420 * depending on the approprate variables
421 */
422 attrs = ATTR_INIT_SETTINGS;
423
424 if (priv->bd_stash_en)
425 attrs |= ATTR_BDSTASH;
426
427 if (priv->rx_stash_size != 0)
428 attrs |= ATTR_BUFSTASH;
429
430 gfar_write(&regs->attr, attrs);
431
432 gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
433 gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
434 gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
435} 402}
436 403
437static struct net_device_stats *gfar_get_stats(struct net_device *dev) 404static struct net_device_stats *gfar_get_stats(struct net_device *dev)
@@ -479,6 +446,29 @@ static const struct net_device_ops gfar_netdev_ops = {
479#endif 446#endif
480}; 447};
481 448
449static void gfar_ints_disable(struct gfar_private *priv)
450{
451 int i;
452 for (i = 0; i < priv->num_grps; i++) {
453 struct gfar __iomem *regs = priv->gfargrp[i].regs;
454 /* Clear IEVENT */
455 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
456
457 /* Initialize IMASK */
458 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
459 }
460}
461
462static void gfar_ints_enable(struct gfar_private *priv)
463{
464 int i;
465 for (i = 0; i < priv->num_grps; i++) {
466 struct gfar __iomem *regs = priv->gfargrp[i].regs;
467 /* Unmask the interrupts we look for */
468 gfar_write(&regs->imask, IMASK_DEFAULT);
469 }
470}
471
482void lock_rx_qs(struct gfar_private *priv) 472void lock_rx_qs(struct gfar_private *priv)
483{ 473{
484 int i; 474 int i;
@@ -511,7 +501,43 @@ void unlock_tx_qs(struct gfar_private *priv)
511 spin_unlock(&priv->tx_queue[i]->txlock); 501 spin_unlock(&priv->tx_queue[i]->txlock);
512} 502}
513 503
514static void free_tx_pointers(struct gfar_private *priv) 504static int gfar_alloc_tx_queues(struct gfar_private *priv)
505{
506 int i;
507
508 for (i = 0; i < priv->num_tx_queues; i++) {
509 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
510 GFP_KERNEL);
511 if (!priv->tx_queue[i])
512 return -ENOMEM;
513
514 priv->tx_queue[i]->tx_skbuff = NULL;
515 priv->tx_queue[i]->qindex = i;
516 priv->tx_queue[i]->dev = priv->ndev;
517 spin_lock_init(&(priv->tx_queue[i]->txlock));
518 }
519 return 0;
520}
521
522static int gfar_alloc_rx_queues(struct gfar_private *priv)
523{
524 int i;
525
526 for (i = 0; i < priv->num_rx_queues; i++) {
527 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
528 GFP_KERNEL);
529 if (!priv->rx_queue[i])
530 return -ENOMEM;
531
532 priv->rx_queue[i]->rx_skbuff = NULL;
533 priv->rx_queue[i]->qindex = i;
534 priv->rx_queue[i]->dev = priv->ndev;
535 spin_lock_init(&(priv->rx_queue[i]->rxlock));
536 }
537 return 0;
538}
539
540static void gfar_free_tx_queues(struct gfar_private *priv)
515{ 541{
516 int i; 542 int i;
517 543
@@ -519,7 +545,7 @@ static void free_tx_pointers(struct gfar_private *priv)
519 kfree(priv->tx_queue[i]); 545 kfree(priv->tx_queue[i]);
520} 546}
521 547
522static void free_rx_pointers(struct gfar_private *priv) 548static void gfar_free_rx_queues(struct gfar_private *priv)
523{ 549{
524 int i; 550 int i;
525 551
@@ -608,6 +634,30 @@ static int gfar_parse_group(struct device_node *np,
608 grp->rx_bit_map = 0xFF; 634 grp->rx_bit_map = 0xFF;
609 grp->tx_bit_map = 0xFF; 635 grp->tx_bit_map = 0xFF;
610 } 636 }
637
638 /* bit_map's MSB is q0 (from q0 to q7) but, for_each_set_bit parses
639 * right to left, so we need to revert the 8 bits to get the q index
640 */
641 grp->rx_bit_map = bitrev8(grp->rx_bit_map);
642 grp->tx_bit_map = bitrev8(grp->tx_bit_map);
643
644 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
645 * also assign queues to groups
646 */
647 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
648 grp->num_rx_queues++;
649 grp->rstat |= (RSTAT_CLEAR_RHALT >> i);
650 priv->rqueue |= ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
651 priv->rx_queue[i]->grp = grp;
652 }
653
654 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
655 grp->num_tx_queues++;
656 grp->tstat |= (TSTAT_CLEAR_THALT >> i);
657 priv->tqueue |= (TQUEUE_EN0 >> i);
658 priv->tx_queue[i]->grp = grp;
659 }
660
611 priv->num_grps++; 661 priv->num_grps++;
612 662
613 return 0; 663 return 0;
@@ -664,7 +714,14 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
664 priv->num_tx_queues = num_tx_qs; 714 priv->num_tx_queues = num_tx_qs;
665 netif_set_real_num_rx_queues(dev, num_rx_qs); 715 netif_set_real_num_rx_queues(dev, num_rx_qs);
666 priv->num_rx_queues = num_rx_qs; 716 priv->num_rx_queues = num_rx_qs;
667 priv->num_grps = 0x0; 717
718 err = gfar_alloc_tx_queues(priv);
719 if (err)
720 goto tx_alloc_failed;
721
722 err = gfar_alloc_rx_queues(priv);
723 if (err)
724 goto rx_alloc_failed;
668 725
669 /* Init Rx queue filer rule set linked list */ 726 /* Init Rx queue filer rule set linked list */
670 INIT_LIST_HEAD(&priv->rx_list.list); 727 INIT_LIST_HEAD(&priv->rx_list.list);
@@ -691,38 +748,6 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
691 goto err_grp_init; 748 goto err_grp_init;
692 } 749 }
693 750
694 for (i = 0; i < priv->num_tx_queues; i++)
695 priv->tx_queue[i] = NULL;
696 for (i = 0; i < priv->num_rx_queues; i++)
697 priv->rx_queue[i] = NULL;
698
699 for (i = 0; i < priv->num_tx_queues; i++) {
700 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
701 GFP_KERNEL);
702 if (!priv->tx_queue[i]) {
703 err = -ENOMEM;
704 goto tx_alloc_failed;
705 }
706 priv->tx_queue[i]->tx_skbuff = NULL;
707 priv->tx_queue[i]->qindex = i;
708 priv->tx_queue[i]->dev = dev;
709 spin_lock_init(&(priv->tx_queue[i]->txlock));
710 }
711
712 for (i = 0; i < priv->num_rx_queues; i++) {
713 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
714 GFP_KERNEL);
715 if (!priv->rx_queue[i]) {
716 err = -ENOMEM;
717 goto rx_alloc_failed;
718 }
719 priv->rx_queue[i]->rx_skbuff = NULL;
720 priv->rx_queue[i]->qindex = i;
721 priv->rx_queue[i]->dev = dev;
722 spin_lock_init(&(priv->rx_queue[i]->rxlock));
723 }
724
725
726 stash = of_get_property(np, "bd-stash", NULL); 751 stash = of_get_property(np, "bd-stash", NULL);
727 752
728 if (stash) { 753 if (stash) {
@@ -749,17 +774,16 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
749 memcpy(dev->dev_addr, mac_addr, ETH_ALEN); 774 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
750 775
751 if (model && !strcasecmp(model, "TSEC")) 776 if (model && !strcasecmp(model, "TSEC"))
752 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 777 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
753 FSL_GIANFAR_DEV_HAS_COALESCE | 778 FSL_GIANFAR_DEV_HAS_COALESCE |
754 FSL_GIANFAR_DEV_HAS_RMON | 779 FSL_GIANFAR_DEV_HAS_RMON |
755 FSL_GIANFAR_DEV_HAS_MULTI_INTR; 780 FSL_GIANFAR_DEV_HAS_MULTI_INTR;
756 781
757 if (model && !strcasecmp(model, "eTSEC")) 782 if (model && !strcasecmp(model, "eTSEC"))
758 priv->device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT | 783 priv->device_flags |= FSL_GIANFAR_DEV_HAS_GIGABIT |
759 FSL_GIANFAR_DEV_HAS_COALESCE | 784 FSL_GIANFAR_DEV_HAS_COALESCE |
760 FSL_GIANFAR_DEV_HAS_RMON | 785 FSL_GIANFAR_DEV_HAS_RMON |
761 FSL_GIANFAR_DEV_HAS_MULTI_INTR | 786 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
762 FSL_GIANFAR_DEV_HAS_PADDING |
763 FSL_GIANFAR_DEV_HAS_CSUM | 787 FSL_GIANFAR_DEV_HAS_CSUM |
764 FSL_GIANFAR_DEV_HAS_VLAN | 788 FSL_GIANFAR_DEV_HAS_VLAN |
765 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET | 789 FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
@@ -784,12 +808,12 @@ static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
784 808
785 return 0; 809 return 0;
786 810
787rx_alloc_failed:
788 free_rx_pointers(priv);
789tx_alloc_failed:
790 free_tx_pointers(priv);
791err_grp_init: 811err_grp_init:
792 unmap_group_regs(priv); 812 unmap_group_regs(priv);
813rx_alloc_failed:
814 gfar_free_rx_queues(priv);
815tx_alloc_failed:
816 gfar_free_tx_queues(priv);
793 free_gfar_dev(priv); 817 free_gfar_dev(priv);
794 return err; 818 return err;
795} 819}
@@ -875,19 +899,6 @@ static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
875 return phy_mii_ioctl(priv->phydev, rq, cmd); 899 return phy_mii_ioctl(priv->phydev, rq, cmd);
876} 900}
877 901
878static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
879{
880 unsigned int new_bit_map = 0x0;
881 int mask = 0x1 << (max_qs - 1), i;
882
883 for (i = 0; i < max_qs; i++) {
884 if (bit_map & mask)
885 new_bit_map = new_bit_map + (1 << i);
886 mask = mask >> 0x1;
887 }
888 return new_bit_map;
889}
890
891static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar, 902static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
892 u32 class) 903 u32 class)
893{ 904{
@@ -1005,43 +1016,10 @@ static void gfar_detect_errata(struct gfar_private *priv)
1005 priv->errata); 1016 priv->errata);
1006} 1017}
1007 1018
1008/* Set up the ethernet device structure, private data, 1019static void gfar_hw_init(struct gfar_private *priv)
1009 * and anything else we need before we start
1010 */
1011static int gfar_probe(struct platform_device *ofdev)
1012{ 1020{
1013 u32 tempval; 1021 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1014 struct net_device *dev = NULL; 1022 u32 tempval, attrs;
1015 struct gfar_private *priv = NULL;
1016 struct gfar __iomem *regs = NULL;
1017 int err = 0, i, grp_idx = 0;
1018 u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
1019 u32 isrg = 0;
1020 u32 __iomem *baddr;
1021
1022 err = gfar_of_init(ofdev, &dev);
1023
1024 if (err)
1025 return err;
1026
1027 priv = netdev_priv(dev);
1028 priv->ndev = dev;
1029 priv->ofdev = ofdev;
1030 priv->dev = &ofdev->dev;
1031 SET_NETDEV_DEV(dev, &ofdev->dev);
1032
1033 spin_lock_init(&priv->bflock);
1034 INIT_WORK(&priv->reset_task, gfar_reset_task);
1035
1036 platform_set_drvdata(ofdev, priv);
1037 regs = priv->gfargrp[0].regs;
1038
1039 gfar_detect_errata(priv);
1040
1041 /* Stop the DMA engine now, in case it was running before
1042 * (The firmware could have used it, and left it running).
1043 */
1044 gfar_halt(dev);
1045 1023
1046 /* Reset MAC layer */ 1024 /* Reset MAC layer */
1047 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET); 1025 gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
@@ -1049,15 +1027,10 @@ static int gfar_probe(struct platform_device *ofdev)
1049 /* We need to delay at least 3 TX clocks */ 1027 /* We need to delay at least 3 TX clocks */
1050 udelay(2); 1028 udelay(2);
1051 1029
1052 tempval = 0;
1053 if (!priv->pause_aneg_en && priv->tx_pause_en)
1054 tempval |= MACCFG1_TX_FLOW;
1055 if (!priv->pause_aneg_en && priv->rx_pause_en)
1056 tempval |= MACCFG1_RX_FLOW;
1057 /* the soft reset bit is not self-resetting, so we need to 1030 /* the soft reset bit is not self-resetting, so we need to
1058 * clear it before resuming normal operation 1031 * clear it before resuming normal operation
1059 */ 1032 */
1060 gfar_write(&regs->maccfg1, tempval); 1033 gfar_write(&regs->maccfg1, 0);
1061 1034
1062 /* Initialize MACCFG2. */ 1035 /* Initialize MACCFG2. */
1063 tempval = MACCFG2_INIT_SETTINGS; 1036 tempval = MACCFG2_INIT_SETTINGS;
@@ -1068,36 +1041,38 @@ static int gfar_probe(struct platform_device *ofdev)
1068 /* Initialize ECNTRL */ 1041 /* Initialize ECNTRL */
1069 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS); 1042 gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1070 1043
1071 /* Set the dev->base_addr to the gfar reg region */ 1044 /* Set the extraction length and index */
1072 dev->base_addr = (unsigned long) regs; 1045 attrs = ATTRELI_EL(priv->rx_stash_size) |
1046 ATTRELI_EI(priv->rx_stash_index);
1073 1047
1074 /* Fill in the dev structure */ 1048 gfar_write(&regs->attreli, attrs);
1075 dev->watchdog_timeo = TX_TIMEOUT;
1076 dev->mtu = 1500;
1077 dev->netdev_ops = &gfar_netdev_ops;
1078 dev->ethtool_ops = &gfar_ethtool_ops;
1079 1049
1080 /* Register for napi ...We are registering NAPI for each grp */ 1050 /* Start with defaults, and add stashing
1081 if (priv->mode == SQ_SG_MODE) 1051 * depending on driver parameters
1082 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq, 1052 */
1083 GFAR_DEV_WEIGHT); 1053 attrs = ATTR_INIT_SETTINGS;
1084 else
1085 for (i = 0; i < priv->num_grps; i++)
1086 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1087 GFAR_DEV_WEIGHT);
1088 1054
1089 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) { 1055 if (priv->bd_stash_en)
1090 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | 1056 attrs |= ATTR_BDSTASH;
1091 NETIF_F_RXCSUM;
1092 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1093 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1094 }
1095 1057
1096 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) { 1058 if (priv->rx_stash_size != 0)
1097 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 1059 attrs |= ATTR_BUFSTASH;
1098 NETIF_F_HW_VLAN_CTAG_RX; 1060
1099 dev->features |= NETIF_F_HW_VLAN_CTAG_RX; 1061 gfar_write(&regs->attr, attrs);
1100 } 1062
1063 /* FIFO configs */
1064 gfar_write(&regs->fifo_tx_thr, DEFAULT_FIFO_TX_THR);
1065 gfar_write(&regs->fifo_tx_starve, DEFAULT_FIFO_TX_STARVE);
1066 gfar_write(&regs->fifo_tx_starve_shutoff, DEFAULT_FIFO_TX_STARVE_OFF);
1067
1068 /* Program the interrupt steering regs, only for MG devices */
1069 if (priv->num_grps > 1)
1070 gfar_write_isrg(priv);
1071}
1072
1073static void __init gfar_init_addr_hash_table(struct gfar_private *priv)
1074{
1075 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1101 1076
1102 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) { 1077 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1103 priv->extended_hash = 1; 1078 priv->extended_hash = 1;
@@ -1133,68 +1108,82 @@ static int gfar_probe(struct platform_device *ofdev)
1133 priv->hash_regs[6] = &regs->gaddr6; 1108 priv->hash_regs[6] = &regs->gaddr6;
1134 priv->hash_regs[7] = &regs->gaddr7; 1109 priv->hash_regs[7] = &regs->gaddr7;
1135 } 1110 }
1111}
1136 1112
1137 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING) 1113/* Set up the ethernet device structure, private data,
1138 priv->padding = DEFAULT_PADDING; 1114 * and anything else we need before we start
1139 else 1115 */
1140 priv->padding = 0; 1116static int gfar_probe(struct platform_device *ofdev)
1117{
1118 struct net_device *dev = NULL;
1119 struct gfar_private *priv = NULL;
1120 int err = 0, i;
1141 1121
1142 if (dev->features & NETIF_F_IP_CSUM || 1122 err = gfar_of_init(ofdev, &dev);
1143 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1144 dev->needed_headroom = GMAC_FCB_LEN;
1145 1123
1146 /* Program the isrg regs only if number of grps > 1 */ 1124 if (err)
1147 if (priv->num_grps > 1) { 1125 return err;
1148 baddr = &regs->isrg0;
1149 for (i = 0; i < priv->num_grps; i++) {
1150 isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1151 isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1152 gfar_write(baddr, isrg);
1153 baddr++;
1154 isrg = 0x0;
1155 }
1156 }
1157 1126
1158 /* Need to reverse the bit maps as bit_map's MSB is q0 1127 priv = netdev_priv(dev);
1159 * but, for_each_set_bit parses from right to left, which 1128 priv->ndev = dev;
1160 * basically reverses the queue numbers 1129 priv->ofdev = ofdev;
1130 priv->dev = &ofdev->dev;
1131 SET_NETDEV_DEV(dev, &ofdev->dev);
1132
1133 spin_lock_init(&priv->bflock);
1134 INIT_WORK(&priv->reset_task, gfar_reset_task);
1135
1136 platform_set_drvdata(ofdev, priv);
1137
1138 gfar_detect_errata(priv);
1139
1140 /* Stop the DMA engine now, in case it was running before
1141 * (The firmware could have used it, and left it running).
1161 */ 1142 */
1162 for (i = 0; i< priv->num_grps; i++) { 1143 gfar_halt(priv);
1163 priv->gfargrp[i].tx_bit_map = 1144
1164 reverse_bitmap(priv->gfargrp[i].tx_bit_map, MAX_TX_QS); 1145 gfar_hw_init(priv);
1165 priv->gfargrp[i].rx_bit_map = 1146
1166 reverse_bitmap(priv->gfargrp[i].rx_bit_map, MAX_RX_QS); 1147 /* Set the dev->base_addr to the gfar reg region */
1148 dev->base_addr = (unsigned long) priv->gfargrp[0].regs;
1149
1150 /* Fill in the dev structure */
1151 dev->watchdog_timeo = TX_TIMEOUT;
1152 dev->mtu = 1500;
1153 dev->netdev_ops = &gfar_netdev_ops;
1154 dev->ethtool_ops = &gfar_ethtool_ops;
1155
1156 /* Register for napi ...We are registering NAPI for each grp */
1157 if (priv->mode == SQ_SG_MODE)
1158 netif_napi_add(dev, &priv->gfargrp[0].napi, gfar_poll_sq,
1159 GFAR_DEV_WEIGHT);
1160 else
1161 for (i = 0; i < priv->num_grps; i++)
1162 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll,
1163 GFAR_DEV_WEIGHT);
1164
1165 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1166 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1167 NETIF_F_RXCSUM;
1168 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1169 NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1167 } 1170 }
1168 1171
1169 /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values, 1172 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1170 * also assign queues to groups 1173 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX |
1171 */ 1174 NETIF_F_HW_VLAN_CTAG_RX;
1172 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) { 1175 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
1173 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1174
1175 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1176 priv->num_rx_queues) {
1177 priv->gfargrp[grp_idx].num_rx_queues++;
1178 priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1179 rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1180 rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1181 }
1182 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1183
1184 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1185 priv->num_tx_queues) {
1186 priv->gfargrp[grp_idx].num_tx_queues++;
1187 priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1188 tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1189 tqueue = tqueue | (TQUEUE_EN0 >> i);
1190 }
1191 priv->gfargrp[grp_idx].rstat = rstat;
1192 priv->gfargrp[grp_idx].tstat = tstat;
1193 rstat = tstat =0;
1194 } 1176 }
1195 1177
1196 gfar_write(&regs->rqueue, rqueue); 1178 gfar_init_addr_hash_table(priv);
1197 gfar_write(&regs->tqueue, tqueue); 1179
1180 /* Insert receive time stamps into padding alignment bytes */
1181 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1182 priv->padding = 8;
1183
1184 if (dev->features & NETIF_F_IP_CSUM ||
1185 priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1186 dev->needed_headroom = GMAC_FCB_LEN;
1198 1187
1199 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE; 1188 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1200 1189
@@ -1251,9 +1240,6 @@ static int gfar_probe(struct platform_device *ofdev)
1251 /* Initialize the filer table */ 1240 /* Initialize the filer table */
1252 gfar_init_filer_table(priv); 1241 gfar_init_filer_table(priv);
1253 1242
1254 /* Create all the sysfs files */
1255 gfar_init_sysfs(dev);
1256
1257 /* Print out the device info */ 1243 /* Print out the device info */
1258 netdev_info(dev, "mac: %pM\n", dev->dev_addr); 1244 netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1259 1245
@@ -1272,8 +1258,8 @@ static int gfar_probe(struct platform_device *ofdev)
1272 1258
1273register_fail: 1259register_fail:
1274 unmap_group_regs(priv); 1260 unmap_group_regs(priv);
1275 free_tx_pointers(priv); 1261 gfar_free_rx_queues(priv);
1276 free_rx_pointers(priv); 1262 gfar_free_tx_queues(priv);
1277 if (priv->phy_node) 1263 if (priv->phy_node)
1278 of_node_put(priv->phy_node); 1264 of_node_put(priv->phy_node);
1279 if (priv->tbi_node) 1265 if (priv->tbi_node)
@@ -1293,6 +1279,8 @@ static int gfar_remove(struct platform_device *ofdev)
1293 1279
1294 unregister_netdev(priv->ndev); 1280 unregister_netdev(priv->ndev);
1295 unmap_group_regs(priv); 1281 unmap_group_regs(priv);
1282 gfar_free_rx_queues(priv);
1283 gfar_free_tx_queues(priv);
1296 free_gfar_dev(priv); 1284 free_gfar_dev(priv);
1297 1285
1298 return 0; 1286 return 0;
@@ -1320,7 +1308,7 @@ static int gfar_suspend(struct device *dev)
1320 lock_tx_qs(priv); 1308 lock_tx_qs(priv);
1321 lock_rx_qs(priv); 1309 lock_rx_qs(priv);
1322 1310
1323 gfar_halt_nodisable(ndev); 1311 gfar_halt_nodisable(priv);
1324 1312
1325 /* Disable Tx, and Rx if wake-on-LAN is disabled. */ 1313 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1326 tempval = gfar_read(&regs->maccfg1); 1314 tempval = gfar_read(&regs->maccfg1);
@@ -1384,7 +1372,7 @@ static int gfar_resume(struct device *dev)
1384 tempval &= ~MACCFG2_MPEN; 1372 tempval &= ~MACCFG2_MPEN;
1385 gfar_write(&regs->maccfg2, tempval); 1373 gfar_write(&regs->maccfg2, tempval);
1386 1374
1387 gfar_start(ndev); 1375 gfar_start(priv);
1388 1376
1389 unlock_rx_qs(priv); 1377 unlock_rx_qs(priv);
1390 unlock_tx_qs(priv); 1378 unlock_tx_qs(priv);
@@ -1416,7 +1404,7 @@ static int gfar_restore(struct device *dev)
1416 init_registers(ndev); 1404 init_registers(ndev);
1417 gfar_set_mac_address(ndev); 1405 gfar_set_mac_address(ndev);
1418 gfar_init_mac(ndev); 1406 gfar_init_mac(ndev);
1419 gfar_start(ndev); 1407 gfar_start(priv);
1420 1408
1421 priv->oldlink = 0; 1409 priv->oldlink = 0;
1422 priv->oldspeed = 0; 1410 priv->oldspeed = 0;
@@ -1577,19 +1565,10 @@ static void gfar_configure_serdes(struct net_device *dev)
1577static void init_registers(struct net_device *dev) 1565static void init_registers(struct net_device *dev)
1578{ 1566{
1579 struct gfar_private *priv = netdev_priv(dev); 1567 struct gfar_private *priv = netdev_priv(dev);
1580 struct gfar __iomem *regs = NULL; 1568 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1581 int i;
1582
1583 for (i = 0; i < priv->num_grps; i++) {
1584 regs = priv->gfargrp[i].regs;
1585 /* Clear IEVENT */
1586 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1587 1569
1588 /* Initialize IMASK */ 1570 gfar_ints_disable(priv);
1589 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1590 }
1591 1571
1592 regs = priv->gfargrp[0].regs;
1593 /* Init hash registers to zero */ 1572 /* Init hash registers to zero */
1594 gfar_write(&regs->igaddr0, 0); 1573 gfar_write(&regs->igaddr0, 0);
1595 gfar_write(&regs->igaddr1, 0); 1574 gfar_write(&regs->igaddr1, 0);
@@ -1648,23 +1627,13 @@ static int __gfar_is_rx_idle(struct gfar_private *priv)
1648} 1627}
1649 1628
1650/* Halt the receive and transmit queues */ 1629/* Halt the receive and transmit queues */
1651static void gfar_halt_nodisable(struct net_device *dev) 1630static void gfar_halt_nodisable(struct gfar_private *priv)
1652{ 1631{
1653 struct gfar_private *priv = netdev_priv(dev); 1632 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1654 struct gfar __iomem *regs = NULL;
1655 u32 tempval; 1633 u32 tempval;
1656 int i;
1657 1634
1658 for (i = 0; i < priv->num_grps; i++) { 1635 gfar_ints_disable(priv);
1659 regs = priv->gfargrp[i].regs;
1660 /* Mask all interrupts */
1661 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1662
1663 /* Clear all interrupts */
1664 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1665 }
1666 1636
1667 regs = priv->gfargrp[0].regs;
1668 /* Stop the DMA, and wait for it to stop */ 1637 /* Stop the DMA, and wait for it to stop */
1669 tempval = gfar_read(&regs->dmactrl); 1638 tempval = gfar_read(&regs->dmactrl);
1670 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) != 1639 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS)) !=
@@ -1685,15 +1654,20 @@ static void gfar_halt_nodisable(struct net_device *dev)
1685} 1654}
1686 1655
1687/* Halt the receive and transmit queues */ 1656/* Halt the receive and transmit queues */
1688void gfar_halt(struct net_device *dev) 1657void gfar_halt(struct gfar_private *priv)
1689{ 1658{
1690 struct gfar_private *priv = netdev_priv(dev);
1691 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1659 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1692 u32 tempval; 1660 u32 tempval;
1693 1661
1694 gfar_halt_nodisable(dev); 1662 /* Dissable the Rx/Tx hw queues */
1663 gfar_write(&regs->rqueue, 0);
1664 gfar_write(&regs->tqueue, 0);
1665
1666 mdelay(10);
1695 1667
1696 /* Disable Rx and Tx */ 1668 gfar_halt_nodisable(priv);
1669
1670 /* Disable Rx/Tx DMA */
1697 tempval = gfar_read(&regs->maccfg1); 1671 tempval = gfar_read(&regs->maccfg1);
1698 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN); 1672 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1699 gfar_write(&regs->maccfg1, tempval); 1673 gfar_write(&regs->maccfg1, tempval);
@@ -1720,7 +1694,7 @@ void stop_gfar(struct net_device *dev)
1720 lock_tx_qs(priv); 1694 lock_tx_qs(priv);
1721 lock_rx_qs(priv); 1695 lock_rx_qs(priv);
1722 1696
1723 gfar_halt(dev); 1697 gfar_halt(priv);
1724 1698
1725 unlock_rx_qs(priv); 1699 unlock_rx_qs(priv);
1726 unlock_tx_qs(priv); 1700 unlock_tx_qs(priv);
@@ -1825,17 +1799,15 @@ static void free_skb_resources(struct gfar_private *priv)
1825 priv->tx_queue[0]->tx_bd_dma_base); 1799 priv->tx_queue[0]->tx_bd_dma_base);
1826} 1800}
1827 1801
1828void gfar_start(struct net_device *dev) 1802void gfar_start(struct gfar_private *priv)
1829{ 1803{
1830 struct gfar_private *priv = netdev_priv(dev);
1831 struct gfar __iomem *regs = priv->gfargrp[0].regs; 1804 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1832 u32 tempval; 1805 u32 tempval;
1833 int i = 0; 1806 int i = 0;
1834 1807
1835 /* Enable Rx and Tx in MACCFG1 */ 1808 /* Enable Rx/Tx hw queues */
1836 tempval = gfar_read(&regs->maccfg1); 1809 gfar_write(&regs->rqueue, priv->rqueue);
1837 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN); 1810 gfar_write(&regs->tqueue, priv->tqueue);
1838 gfar_write(&regs->maccfg1, tempval);
1839 1811
1840 /* Initialize DMACTRL to have WWR and WOP */ 1812 /* Initialize DMACTRL to have WWR and WOP */
1841 tempval = gfar_read(&regs->dmactrl); 1813 tempval = gfar_read(&regs->dmactrl);
@@ -1852,11 +1824,16 @@ void gfar_start(struct net_device *dev)
1852 /* Clear THLT/RHLT, so that the DMA starts polling now */ 1824 /* Clear THLT/RHLT, so that the DMA starts polling now */
1853 gfar_write(&regs->tstat, priv->gfargrp[i].tstat); 1825 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1854 gfar_write(&regs->rstat, priv->gfargrp[i].rstat); 1826 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1855 /* Unmask the interrupts we look for */
1856 gfar_write(&regs->imask, IMASK_DEFAULT);
1857 } 1827 }
1858 1828
1859 dev->trans_start = jiffies; /* prevent tx timeout */ 1829 /* Enable Rx/Tx DMA */
1830 tempval = gfar_read(&regs->maccfg1);
1831 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1832 gfar_write(&regs->maccfg1, tempval);
1833
1834 gfar_ints_enable(priv);
1835
1836 priv->ndev->trans_start = jiffies; /* prevent tx timeout */
1860} 1837}
1861 1838
1862static void gfar_configure_coalescing(struct gfar_private *priv, 1839static void gfar_configure_coalescing(struct gfar_private *priv,
@@ -1960,15 +1937,10 @@ err_irq_fail:
1960int startup_gfar(struct net_device *ndev) 1937int startup_gfar(struct net_device *ndev)
1961{ 1938{
1962 struct gfar_private *priv = netdev_priv(ndev); 1939 struct gfar_private *priv = netdev_priv(ndev);
1963 struct gfar __iomem *regs = NULL;
1964 int err, i, j; 1940 int err, i, j;
1965 1941
1966 for (i = 0; i < priv->num_grps; i++) { 1942 gfar_ints_disable(priv);
1967 regs= priv->gfargrp[i].regs;
1968 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1969 }
1970 1943
1971 regs= priv->gfargrp[0].regs;
1972 err = gfar_alloc_skb_resources(ndev); 1944 err = gfar_alloc_skb_resources(ndev);
1973 if (err) 1945 if (err)
1974 return err; 1946 return err;
@@ -1985,7 +1957,7 @@ int startup_gfar(struct net_device *ndev)
1985 } 1957 }
1986 1958
1987 /* Start the controller */ 1959 /* Start the controller */
1988 gfar_start(ndev); 1960 gfar_start(priv);
1989 1961
1990 phy_start(priv->phydev); 1962 phy_start(priv->phydev);
1991 1963
diff --git a/drivers/net/ethernet/freescale/gianfar.h b/drivers/net/ethernet/freescale/gianfar.h
index 52bb2b0195cc..2a59398f8cf0 100644
--- a/drivers/net/ethernet/freescale/gianfar.h
+++ b/drivers/net/ethernet/freescale/gianfar.h
@@ -9,7 +9,7 @@
9 * Maintainer: Kumar Gala 9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com> 10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
11 * 11 *
12 * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc. 12 * Copyright 2002-2009, 2011-2013 Freescale Semiconductor, Inc.
13 * 13 *
14 * This program is free software; you can redistribute it and/or modify it 14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the 15 * under the terms of the GNU General Public License as published by the
@@ -880,7 +880,6 @@ struct gfar {
880#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010 880#define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
881#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020 881#define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
882#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040 882#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
883#define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
884#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100 883#define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
885#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200 884#define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
886#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400 885#define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
@@ -892,8 +891,8 @@ struct gfar {
892#define DEFAULT_MAPPING 0xFF 891#define DEFAULT_MAPPING 0xFF
893#endif 892#endif
894 893
895#define ISRG_SHIFT_TX 0x10 894#define ISRG_RR0 0x80000000
896#define ISRG_SHIFT_RX 0x18 895#define ISRG_TR0 0x00800000
897 896
898/* The same driver can operate in two modes */ 897/* The same driver can operate in two modes */
899/* SQ_SG_MODE: Single Queue Single Group Mode 898/* SQ_SG_MODE: Single Queue Single Group Mode
@@ -1113,6 +1112,9 @@ struct gfar_private {
1113 unsigned int total_tx_ring_size; 1112 unsigned int total_tx_ring_size;
1114 unsigned int total_rx_ring_size; 1113 unsigned int total_rx_ring_size;
1115 1114
1115 u32 rqueue;
1116 u32 tqueue;
1117
1116 /* RX per device parameters */ 1118 /* RX per device parameters */
1117 unsigned int rx_stash_size; 1119 unsigned int rx_stash_size;
1118 unsigned int rx_stash_index; 1120 unsigned int rx_stash_index;
@@ -1127,11 +1129,6 @@ struct gfar_private {
1127 u32 __iomem *hash_regs[16]; 1129 u32 __iomem *hash_regs[16];
1128 int hash_width; 1130 int hash_width;
1129 1131
1130 /* global parameters */
1131 unsigned int fifo_threshold;
1132 unsigned int fifo_starve;
1133 unsigned int fifo_starve_off;
1134
1135 /*Filer table*/ 1132 /*Filer table*/
1136 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1]; 1133 unsigned int ftp_rqfpr[MAX_FILER_IDX + 1];
1137 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1]; 1134 unsigned int ftp_rqfcr[MAX_FILER_IDX + 1];
@@ -1176,6 +1173,31 @@ static inline void gfar_read_filer(struct gfar_private *priv,
1176 *fpr = gfar_read(&regs->rqfpr); 1173 *fpr = gfar_read(&regs->rqfpr);
1177} 1174}
1178 1175
1176static inline void gfar_write_isrg(struct gfar_private *priv)
1177{
1178 struct gfar __iomem *regs = priv->gfargrp[0].regs;
1179 u32 __iomem *baddr = &regs->isrg0;
1180 u32 isrg = 0;
1181 int grp_idx, i;
1182
1183 for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1184 struct gfar_priv_grp *grp = &priv->gfargrp[grp_idx];
1185
1186 for_each_set_bit(i, &grp->rx_bit_map, priv->num_rx_queues) {
1187 isrg |= (ISRG_RR0 >> i);
1188 }
1189
1190 for_each_set_bit(i, &grp->tx_bit_map, priv->num_tx_queues) {
1191 isrg |= (ISRG_TR0 >> i);
1192 }
1193
1194 gfar_write(baddr, isrg);
1195
1196 baddr++;
1197 isrg = 0;
1198 }
1199}
1200
1179void lock_rx_qs(struct gfar_private *priv); 1201void lock_rx_qs(struct gfar_private *priv);
1180void lock_tx_qs(struct gfar_private *priv); 1202void lock_tx_qs(struct gfar_private *priv);
1181void unlock_rx_qs(struct gfar_private *priv); 1203void unlock_rx_qs(struct gfar_private *priv);
@@ -1183,11 +1205,11 @@ void unlock_tx_qs(struct gfar_private *priv);
1183irqreturn_t gfar_receive(int irq, void *dev_id); 1205irqreturn_t gfar_receive(int irq, void *dev_id);
1184int startup_gfar(struct net_device *dev); 1206int startup_gfar(struct net_device *dev);
1185void stop_gfar(struct net_device *dev); 1207void stop_gfar(struct net_device *dev);
1186void gfar_halt(struct net_device *dev); 1208void gfar_halt(struct gfar_private *priv);
1209void gfar_start(struct gfar_private *priv);
1187void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable, 1210void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev, int enable,
1188 u32 regnum, u32 read); 1211 u32 regnum, u32 read);
1189void gfar_configure_coalescing_all(struct gfar_private *priv); 1212void gfar_configure_coalescing_all(struct gfar_private *priv);
1190void gfar_init_sysfs(struct net_device *dev);
1191int gfar_set_features(struct net_device *dev, netdev_features_t features); 1213int gfar_set_features(struct net_device *dev, netdev_features_t features);
1192void gfar_check_rx_parser_mode(struct gfar_private *priv); 1214void gfar_check_rx_parser_mode(struct gfar_private *priv);
1193void gfar_vlan_mode(struct net_device *dev, netdev_features_t features); 1215void gfar_vlan_mode(struct net_device *dev, netdev_features_t features);
diff --git a/drivers/net/ethernet/freescale/gianfar_ethtool.c b/drivers/net/ethernet/freescale/gianfar_ethtool.c
index 63d234419cc1..19557ec31f33 100644
--- a/drivers/net/ethernet/freescale/gianfar_ethtool.c
+++ b/drivers/net/ethernet/freescale/gianfar_ethtool.c
@@ -44,10 +44,6 @@
44 44
45#include "gianfar.h" 45#include "gianfar.h"
46 46
47extern void gfar_start(struct net_device *dev);
48extern int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue,
49 int rx_work_limit);
50
51#define GFAR_MAX_COAL_USECS 0xffff 47#define GFAR_MAX_COAL_USECS 0xffff
52#define GFAR_MAX_COAL_FRAMES 0xff 48#define GFAR_MAX_COAL_FRAMES 0xff
53static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy, 49static void gfar_fill_stats(struct net_device *dev, struct ethtool_stats *dummy,
@@ -467,15 +463,13 @@ static void gfar_gringparam(struct net_device *dev,
467} 463}
468 464
469/* Change the current ring parameters, stopping the controller if 465/* Change the current ring parameters, stopping the controller if
470 * necessary so that we don't mess things up while we're in 466 * necessary so that we don't mess things up while we're in motion.
471 * motion. We wait for the ring to be clean before reallocating
472 * the rings.
473 */ 467 */
474static int gfar_sringparam(struct net_device *dev, 468static int gfar_sringparam(struct net_device *dev,
475 struct ethtool_ringparam *rvals) 469 struct ethtool_ringparam *rvals)
476{ 470{
477 struct gfar_private *priv = netdev_priv(dev); 471 struct gfar_private *priv = netdev_priv(dev);
478 int err = 0, i = 0; 472 int err = 0, i;
479 473
480 if (rvals->rx_pending > GFAR_RX_MAX_RING_SIZE) 474 if (rvals->rx_pending > GFAR_RX_MAX_RING_SIZE)
481 return -EINVAL; 475 return -EINVAL;
@@ -493,38 +487,15 @@ static int gfar_sringparam(struct net_device *dev,
493 return -EINVAL; 487 return -EINVAL;
494 } 488 }
495 489
496 490 if (dev->flags & IFF_UP)
497 if (dev->flags & IFF_UP) {
498 unsigned long flags;
499
500 /* Halt TX and RX, and process the frames which
501 * have already been received
502 */
503 local_irq_save(flags);
504 lock_tx_qs(priv);
505 lock_rx_qs(priv);
506
507 gfar_halt(dev);
508
509 unlock_rx_qs(priv);
510 unlock_tx_qs(priv);
511 local_irq_restore(flags);
512
513 for (i = 0; i < priv->num_rx_queues; i++)
514 gfar_clean_rx_ring(priv->rx_queue[i],
515 priv->rx_queue[i]->rx_ring_size);
516
517 /* Now we take down the rings to rebuild them */
518 stop_gfar(dev); 491 stop_gfar(dev);
519 }
520 492
521 /* Change the size */ 493 /* Change the sizes */
522 for (i = 0; i < priv->num_rx_queues; i++) { 494 for (i = 0; i < priv->num_rx_queues; i++)
523 priv->rx_queue[i]->rx_ring_size = rvals->rx_pending; 495 priv->rx_queue[i]->rx_ring_size = rvals->rx_pending;
496
497 for (i = 0; i < priv->num_tx_queues; i++)
524 priv->tx_queue[i]->tx_ring_size = rvals->tx_pending; 498 priv->tx_queue[i]->tx_ring_size = rvals->tx_pending;
525 priv->tx_queue[i]->num_txbdfree =
526 priv->tx_queue[i]->tx_ring_size;
527 }
528 499
529 /* Rebuild the rings with the new size */ 500 /* Rebuild the rings with the new size */
530 if (dev->flags & IFF_UP) { 501 if (dev->flags & IFF_UP) {
@@ -608,10 +579,8 @@ static int gfar_spauseparam(struct net_device *dev,
608 579
609int gfar_set_features(struct net_device *dev, netdev_features_t features) 580int gfar_set_features(struct net_device *dev, netdev_features_t features)
610{ 581{
611 struct gfar_private *priv = netdev_priv(dev);
612 unsigned long flags;
613 int err = 0, i = 0;
614 netdev_features_t changed = dev->features ^ features; 582 netdev_features_t changed = dev->features ^ features;
583 int err = 0;
615 584
616 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX)) 585 if (changed & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
617 gfar_vlan_mode(dev, features); 586 gfar_vlan_mode(dev, features);
@@ -620,23 +589,6 @@ int gfar_set_features(struct net_device *dev, netdev_features_t features)
620 return 0; 589 return 0;
621 590
622 if (dev->flags & IFF_UP) { 591 if (dev->flags & IFF_UP) {
623 /* Halt TX and RX, and process the frames which
624 * have already been received
625 */
626 local_irq_save(flags);
627 lock_tx_qs(priv);
628 lock_rx_qs(priv);
629
630 gfar_halt(dev);
631
632 unlock_tx_qs(priv);
633 unlock_rx_qs(priv);
634 local_irq_restore(flags);
635
636 for (i = 0; i < priv->num_rx_queues; i++)
637 gfar_clean_rx_ring(priv->rx_queue[i],
638 priv->rx_queue[i]->rx_ring_size);
639
640 /* Now we take down the rings to rebuild them */ 592 /* Now we take down the rings to rebuild them */
641 stop_gfar(dev); 593 stop_gfar(dev);
642 594
diff --git a/drivers/net/ethernet/freescale/gianfar_sysfs.c b/drivers/net/ethernet/freescale/gianfar_sysfs.c
deleted file mode 100644
index e02dd1378751..000000000000
--- a/drivers/net/ethernet/freescale/gianfar_sysfs.c
+++ /dev/null
@@ -1,340 +0,0 @@
1/*
2 * drivers/net/ethernet/freescale/gianfar_sysfs.c
3 *
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
8 *
9 * Author: Andy Fleming
10 * Maintainer: Kumar Gala (galak@kernel.crashing.org)
11 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 *
13 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 *
20 * Sysfs file creation and management
21 */
22
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/errno.h>
26#include <linux/unistd.h>
27#include <linux/delay.h>
28#include <linux/etherdevice.h>
29#include <linux/spinlock.h>
30#include <linux/mm.h>
31#include <linux/device.h>
32
33#include <asm/uaccess.h>
34#include <linux/module.h>
35
36#include "gianfar.h"
37
38static ssize_t gfar_show_bd_stash(struct device *dev,
39 struct device_attribute *attr, char *buf)
40{
41 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
42
43 return sprintf(buf, "%s\n", priv->bd_stash_en ? "on" : "off");
44}
45
46static ssize_t gfar_set_bd_stash(struct device *dev,
47 struct device_attribute *attr,
48 const char *buf, size_t count)
49{
50 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
51 struct gfar __iomem *regs = priv->gfargrp[0].regs;
52 int new_setting = 0;
53 u32 temp;
54 unsigned long flags;
55
56 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_BD_STASHING))
57 return count;
58
59
60 /* Find out the new setting */
61 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1))
62 new_setting = 1;
63 else if (!strncmp("off", buf, count - 1) ||
64 !strncmp("0", buf, count - 1))
65 new_setting = 0;
66 else
67 return count;
68
69
70 local_irq_save(flags);
71 lock_rx_qs(priv);
72
73 /* Set the new stashing value */
74 priv->bd_stash_en = new_setting;
75
76 temp = gfar_read(&regs->attr);
77
78 if (new_setting)
79 temp |= ATTR_BDSTASH;
80 else
81 temp &= ~(ATTR_BDSTASH);
82
83 gfar_write(&regs->attr, temp);
84
85 unlock_rx_qs(priv);
86 local_irq_restore(flags);
87
88 return count;
89}
90
91static DEVICE_ATTR(bd_stash, 0644, gfar_show_bd_stash, gfar_set_bd_stash);
92
93static ssize_t gfar_show_rx_stash_size(struct device *dev,
94 struct device_attribute *attr, char *buf)
95{
96 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
97
98 return sprintf(buf, "%d\n", priv->rx_stash_size);
99}
100
101static ssize_t gfar_set_rx_stash_size(struct device *dev,
102 struct device_attribute *attr,
103 const char *buf, size_t count)
104{
105 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
106 struct gfar __iomem *regs = priv->gfargrp[0].regs;
107 unsigned int length = simple_strtoul(buf, NULL, 0);
108 u32 temp;
109 unsigned long flags;
110
111 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_BUF_STASHING))
112 return count;
113
114 local_irq_save(flags);
115 lock_rx_qs(priv);
116
117 if (length > priv->rx_buffer_size)
118 goto out;
119
120 if (length == priv->rx_stash_size)
121 goto out;
122
123 priv->rx_stash_size = length;
124
125 temp = gfar_read(&regs->attreli);
126 temp &= ~ATTRELI_EL_MASK;
127 temp |= ATTRELI_EL(length);
128 gfar_write(&regs->attreli, temp);
129
130 /* Turn stashing on/off as appropriate */
131 temp = gfar_read(&regs->attr);
132
133 if (length)
134 temp |= ATTR_BUFSTASH;
135 else
136 temp &= ~(ATTR_BUFSTASH);
137
138 gfar_write(&regs->attr, temp);
139
140out:
141 unlock_rx_qs(priv);
142 local_irq_restore(flags);
143
144 return count;
145}
146
147static DEVICE_ATTR(rx_stash_size, 0644, gfar_show_rx_stash_size,
148 gfar_set_rx_stash_size);
149
150/* Stashing will only be enabled when rx_stash_size != 0 */
151static ssize_t gfar_show_rx_stash_index(struct device *dev,
152 struct device_attribute *attr,
153 char *buf)
154{
155 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
156
157 return sprintf(buf, "%d\n", priv->rx_stash_index);
158}
159
160static ssize_t gfar_set_rx_stash_index(struct device *dev,
161 struct device_attribute *attr,
162 const char *buf, size_t count)
163{
164 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
165 struct gfar __iomem *regs = priv->gfargrp[0].regs;
166 unsigned short index = simple_strtoul(buf, NULL, 0);
167 u32 temp;
168 unsigned long flags;
169
170 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_BUF_STASHING))
171 return count;
172
173 local_irq_save(flags);
174 lock_rx_qs(priv);
175
176 if (index > priv->rx_stash_size)
177 goto out;
178
179 if (index == priv->rx_stash_index)
180 goto out;
181
182 priv->rx_stash_index = index;
183
184 temp = gfar_read(&regs->attreli);
185 temp &= ~ATTRELI_EI_MASK;
186 temp |= ATTRELI_EI(index);
187 gfar_write(&regs->attreli, temp);
188
189out:
190 unlock_rx_qs(priv);
191 local_irq_restore(flags);
192
193 return count;
194}
195
196static DEVICE_ATTR(rx_stash_index, 0644, gfar_show_rx_stash_index,
197 gfar_set_rx_stash_index);
198
199static ssize_t gfar_show_fifo_threshold(struct device *dev,
200 struct device_attribute *attr,
201 char *buf)
202{
203 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
204
205 return sprintf(buf, "%d\n", priv->fifo_threshold);
206}
207
208static ssize_t gfar_set_fifo_threshold(struct device *dev,
209 struct device_attribute *attr,
210 const char *buf, size_t count)
211{
212 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
213 struct gfar __iomem *regs = priv->gfargrp[0].regs;
214 unsigned int length = simple_strtoul(buf, NULL, 0);
215 u32 temp;
216 unsigned long flags;
217
218 if (length > GFAR_MAX_FIFO_THRESHOLD)
219 return count;
220
221 local_irq_save(flags);
222 lock_tx_qs(priv);
223
224 priv->fifo_threshold = length;
225
226 temp = gfar_read(&regs->fifo_tx_thr);
227 temp &= ~FIFO_TX_THR_MASK;
228 temp |= length;
229 gfar_write(&regs->fifo_tx_thr, temp);
230
231 unlock_tx_qs(priv);
232 local_irq_restore(flags);
233
234 return count;
235}
236
237static DEVICE_ATTR(fifo_threshold, 0644, gfar_show_fifo_threshold,
238 gfar_set_fifo_threshold);
239
240static ssize_t gfar_show_fifo_starve(struct device *dev,
241 struct device_attribute *attr, char *buf)
242{
243 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
244
245 return sprintf(buf, "%d\n", priv->fifo_starve);
246}
247
248static ssize_t gfar_set_fifo_starve(struct device *dev,
249 struct device_attribute *attr,
250 const char *buf, size_t count)
251{
252 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
253 struct gfar __iomem *regs = priv->gfargrp[0].regs;
254 unsigned int num = simple_strtoul(buf, NULL, 0);
255 u32 temp;
256 unsigned long flags;
257
258 if (num > GFAR_MAX_FIFO_STARVE)
259 return count;
260
261 local_irq_save(flags);
262 lock_tx_qs(priv);
263
264 priv->fifo_starve = num;
265
266 temp = gfar_read(&regs->fifo_tx_starve);
267 temp &= ~FIFO_TX_STARVE_MASK;
268 temp |= num;
269 gfar_write(&regs->fifo_tx_starve, temp);
270
271 unlock_tx_qs(priv);
272 local_irq_restore(flags);
273
274 return count;
275}
276
277static DEVICE_ATTR(fifo_starve, 0644, gfar_show_fifo_starve,
278 gfar_set_fifo_starve);
279
280static ssize_t gfar_show_fifo_starve_off(struct device *dev,
281 struct device_attribute *attr,
282 char *buf)
283{
284 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
285
286 return sprintf(buf, "%d\n", priv->fifo_starve_off);
287}
288
289static ssize_t gfar_set_fifo_starve_off(struct device *dev,
290 struct device_attribute *attr,
291 const char *buf, size_t count)
292{
293 struct gfar_private *priv = netdev_priv(to_net_dev(dev));
294 struct gfar __iomem *regs = priv->gfargrp[0].regs;
295 unsigned int num = simple_strtoul(buf, NULL, 0);
296 u32 temp;
297 unsigned long flags;
298
299 if (num > GFAR_MAX_FIFO_STARVE_OFF)
300 return count;
301
302 local_irq_save(flags);
303 lock_tx_qs(priv);
304
305 priv->fifo_starve_off = num;
306
307 temp = gfar_read(&regs->fifo_tx_starve_shutoff);
308 temp &= ~FIFO_TX_STARVE_OFF_MASK;
309 temp |= num;
310 gfar_write(&regs->fifo_tx_starve_shutoff, temp);
311
312 unlock_tx_qs(priv);
313 local_irq_restore(flags);
314
315 return count;
316}
317
318static DEVICE_ATTR(fifo_starve_off, 0644, gfar_show_fifo_starve_off,
319 gfar_set_fifo_starve_off);
320
321void gfar_init_sysfs(struct net_device *dev)
322{
323 struct gfar_private *priv = netdev_priv(dev);
324 int rc;
325
326 /* Initialize the default values */
327 priv->fifo_threshold = DEFAULT_FIFO_TX_THR;
328 priv->fifo_starve = DEFAULT_FIFO_TX_STARVE;
329 priv->fifo_starve_off = DEFAULT_FIFO_TX_STARVE_OFF;
330
331 /* Create our sysfs files */
332 rc = device_create_file(&dev->dev, &dev_attr_bd_stash);
333 rc |= device_create_file(&dev->dev, &dev_attr_rx_stash_size);
334 rc |= device_create_file(&dev->dev, &dev_attr_rx_stash_index);
335 rc |= device_create_file(&dev->dev, &dev_attr_fifo_threshold);
336 rc |= device_create_file(&dev->dev, &dev_attr_fifo_starve);
337 rc |= device_create_file(&dev->dev, &dev_attr_fifo_starve_off);
338 if (rc)
339 dev_err(&dev->dev, "Error creating gianfar sysfs files\n");
340}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-25 18:38:09 -0400