aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.c484
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_uncore.h86
-rw-r--r--include/linux/pci_ids.h11
3 files changed, 581 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index e20c65a0e108..d34f68bf990b 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
@@ -21,6 +21,482 @@ DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
21DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23"); 21DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
22DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28"); 22DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
23DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31"); 23DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
24DEFINE_UNCORE_FORMAT_ATTR(thresh8, thresh, "config:24-31");
25DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
26DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
27DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
28DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
29
30/* Sandy Bridge-EP uncore support */
31static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
32{
33 struct pci_dev *pdev = box->pci_dev;
34 int box_ctl = uncore_pci_box_ctl(box);
35 u32 config;
36
37 pci_read_config_dword(pdev, box_ctl, &config);
38 config |= SNBEP_PMON_BOX_CTL_FRZ;
39 pci_write_config_dword(pdev, box_ctl, config);
40}
41
42static void snbep_uncore_pci_enable_box(struct intel_uncore_box *box)
43{
44 struct pci_dev *pdev = box->pci_dev;
45 int box_ctl = uncore_pci_box_ctl(box);
46 u32 config;
47
48 pci_read_config_dword(pdev, box_ctl, &config);
49 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
50 pci_write_config_dword(pdev, box_ctl, config);
51}
52
53static void snbep_uncore_pci_enable_event(struct intel_uncore_box *box,
54 struct perf_event *event)
55{
56 struct pci_dev *pdev = box->pci_dev;
57 struct hw_perf_event *hwc = &event->hw;
58
59 pci_write_config_dword(pdev, hwc->config_base, hwc->config |
60 SNBEP_PMON_CTL_EN);
61}
62
63static void snbep_uncore_pci_disable_event(struct intel_uncore_box *box,
64 struct perf_event *event)
65{
66 struct pci_dev *pdev = box->pci_dev;
67 struct hw_perf_event *hwc = &event->hw;
68
69 pci_write_config_dword(pdev, hwc->config_base, hwc->config);
70}
71
72static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box,
73 struct perf_event *event)
74{
75 struct pci_dev *pdev = box->pci_dev;
76 struct hw_perf_event *hwc = &event->hw;
77 u64 count;
78
79 pci_read_config_dword(pdev, hwc->event_base, (u32 *)&count);
80 pci_read_config_dword(pdev, hwc->event_base + 4, (u32 *)&count + 1);
81 return count;
82}
83
84static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
85{
86 struct pci_dev *pdev = box->pci_dev;
87 pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL,
88 SNBEP_PMON_BOX_CTL_INT);
89}
90
91static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
92{
93 u64 config;
94 unsigned msr;
95
96 msr = uncore_msr_box_ctl(box);
97 if (msr) {
98 rdmsrl(msr, config);
99 config |= SNBEP_PMON_BOX_CTL_FRZ;
100 wrmsrl(msr, config);
101 return;
102 }
103}
104
105static void snbep_uncore_msr_enable_box(struct intel_uncore_box *box)
106{
107 u64 config;
108 unsigned msr;
109
110 msr = uncore_msr_box_ctl(box);
111 if (msr) {
112 rdmsrl(msr, config);
113 config &= ~SNBEP_PMON_BOX_CTL_FRZ;
114 wrmsrl(msr, config);
115 return;
116 }
117}
118
119static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box,
120 struct perf_event *event)
121{
122 struct hw_perf_event *hwc = &event->hw;
123
124 wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
125}
126
127static void snbep_uncore_msr_disable_event(struct intel_uncore_box *box,
128 struct perf_event *event)
129{
130 struct hw_perf_event *hwc = &event->hw;
131
132 wrmsrl(hwc->config_base, hwc->config);
133}
134
135static u64 snbep_uncore_msr_read_counter(struct intel_uncore_box *box,
136 struct perf_event *event)
137{
138 struct hw_perf_event *hwc = &event->hw;
139 u64 count;
140
141 rdmsrl(hwc->event_base, count);
142 return count;
143}
144
145static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
146{
147 unsigned msr = uncore_msr_box_ctl(box);
148 if (msr)
149 wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
150}
151
152static struct attribute *snbep_uncore_formats_attr[] = {
153 &format_attr_event.attr,
154 &format_attr_umask.attr,
155 &format_attr_edge.attr,
156 &format_attr_inv.attr,
157 &format_attr_thresh8.attr,
158 NULL,
159};
160
161static struct attribute *snbep_uncore_ubox_formats_attr[] = {
162 &format_attr_event.attr,
163 &format_attr_umask.attr,
164 &format_attr_edge.attr,
165 &format_attr_inv.attr,
166 &format_attr_thresh5.attr,
167 NULL,
168};
169
170static struct attribute *snbep_uncore_pcu_formats_attr[] = {
171 &format_attr_event.attr,
172 &format_attr_occ_sel.attr,
173 &format_attr_edge.attr,
174 &format_attr_inv.attr,
175 &format_attr_thresh5.attr,
176 &format_attr_occ_invert.attr,
177 &format_attr_occ_edge.attr,
178 NULL,
179};
180
181static struct uncore_event_desc snbep_uncore_imc_events[] = {
182 INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "config=0xffff"),
183 /* read */
184 INTEL_UNCORE_EVENT_DESC(CAS_COUNT_RD, "event=0x4,umask=0x3"),
185 /* write */
186 INTEL_UNCORE_EVENT_DESC(CAS_COUNT_WR, "event=0x4,umask=0xc"),
187 { /* end: all zeroes */ },
188};
189
190static struct uncore_event_desc snbep_uncore_qpi_events[] = {
191 INTEL_UNCORE_EVENT_DESC(CLOCKTICKS, "event=0x14"),
192 /* outgoing data+nondata flits */
193 INTEL_UNCORE_EVENT_DESC(TxL_FLITS_ACTIVE, "event=0x0,umask=0x6"),
194 /* DRS data received */
195 INTEL_UNCORE_EVENT_DESC(DRS_DATA, "event=0x2,umask=0x8"),
196 /* NCB data received */
197 INTEL_UNCORE_EVENT_DESC(NCB_DATA, "event=0x3,umask=0x4"),
198 { /* end: all zeroes */ },
199};
200
201static struct attribute_group snbep_uncore_format_group = {
202 .name = "format",
203 .attrs = snbep_uncore_formats_attr,
204};