aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4.h16
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c524
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h12
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c26
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c155
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.h19
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h149
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h81
8 files changed, 982 insertions, 0 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 5ab5c3133acd..7c785b5e7757 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -290,11 +290,21 @@ enum chip_type {
290 T5_LAST_REV = T5_A1, 290 T5_LAST_REV = T5_A1,
291}; 291};
292 292
293struct devlog_params {
294 u32 memtype; /* which memory (EDC0, EDC1, MC) */
295 u32 start; /* start of log in firmware memory */
296 u32 size; /* size of log */
297};
298
293struct adapter_params { 299struct adapter_params {
294 struct sge_params sge; 300 struct sge_params sge;
295 struct tp_params tp; 301 struct tp_params tp;
296 struct vpd_params vpd; 302 struct vpd_params vpd;
297 struct pci_params pci; 303 struct pci_params pci;
304 struct devlog_params devlog;
305 enum pcie_memwin drv_memwin;
306
307 unsigned int cim_la_size;
298 308
299 unsigned int sf_size; /* serial flash size in bytes */ 309 unsigned int sf_size; /* serial flash size in bytes */
300 unsigned int sf_nsec; /* # of flash sectors */ 310 unsigned int sf_nsec; /* # of flash sectors */
@@ -1026,6 +1036,12 @@ int t4_mc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
1026 u64 *parity); 1036 u64 *parity);
1027int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, 1037int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data,
1028 u64 *parity); 1038 u64 *parity);
1039int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1040 unsigned int *valp);
1041int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1042 const unsigned int *valp);
1043int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1044void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1029const char *t4_get_port_type_description(enum fw_port_type port_type); 1045const char *t4_get_port_type_description(enum fw_port_type port_type);
1030void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p); 1046void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1031void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log); 1047void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
index c98a350d857e..e9f348942eb0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.c
@@ -43,6 +43,526 @@
43#include "cxgb4_debugfs.h" 43#include "cxgb4_debugfs.h"
44#include "l2t.h" 44#include "l2t.h"
45 45
46/* generic seq_file support for showing a table of size rows x width. */
47static void *seq_tab_get_idx(struct seq_tab *tb, loff_t pos)
48{
49 pos -= tb->skip_first;
50 return pos >= tb->rows ? NULL : &tb->data[pos * tb->width];
51}
52
53static void *seq_tab_start(struct seq_file *seq, loff_t *pos)
54{
55 struct seq_tab *tb = seq->private;
56
57 if (tb->skip_first && *pos == 0)
58 return SEQ_START_TOKEN;
59
60 return seq_tab_get_idx(tb, *pos);
61}
62
63static void *seq_tab_next(struct seq_file *seq, void *v, loff_t *pos)
64{
65 v = seq_tab_get_idx(seq->private, *pos + 1);
66 if (v)
67 ++*pos;
68 return v;
69}
70
71static void seq_tab_stop(struct seq_file *seq, void *v)
72{
73}
74
75static int seq_tab_show(struct seq_file *seq, void *v)
76{
77 const struct seq_tab *tb = seq->private;
78
79 return tb->show(seq, v, ((char *)v - tb->data) / tb->width);
80}
81
82static const struct seq_operations seq_tab_ops = {
83 .start = seq_tab_start,
84 .next = seq_tab_next,
85 .stop = seq_tab_stop,
86 .show = seq_tab_show
87};
88
89struct seq_tab *seq_open_tab(struct file *f, unsigned int rows,
90 unsigned int width, unsigned int have_header,
91 int (*show)(struct seq_file *seq, void *v, int i))
92{
93 struct seq_tab *p;
94
95 p = __seq_open_private(f, &seq_tab_ops, sizeof(*p) + rows * width);
96 if (p) {
97 p->show = show;
98 p->rows = rows;
99 p->width = width;
100 p->skip_first = have_header != 0;
101 }
102 return p;
103}
104
105static int cim_la_show(struct seq_file *seq, void *v, int idx)
106{
107 if (v == SEQ_START_TOKEN)
108 seq_puts(seq, "Status Data PC LS0Stat LS0Addr "
109 " LS0Data\n");
110 else {
111 const u32 *p = v;
112
113 seq_printf(seq,
114 " %02x %x%07x %x%07x %08x %08x %08x%08x%08x%08x\n",
115 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
116 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
117 p[6], p[7]);
118 }
119 return 0;
120}
121
122static int cim_la_show_3in1(struct seq_file *seq, void *v, int idx)
123{
124 if (v == SEQ_START_TOKEN) {
125 seq_puts(seq, "Status Data PC\n");
126 } else {
127 const u32 *p = v;
128
129 seq_printf(seq, " %02x %08x %08x\n", p[5] & 0xff, p[6],
130 p[7]);
131 seq_printf(seq, " %02x %02x%06x %02x%06x\n",
132 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
133 p[4] & 0xff, p[5] >> 8);
134 seq_printf(seq, " %02x %x%07x %x%07x\n", (p[0] >> 4) & 0xff,
135 p[0] & 0xf, p[1] >> 4, p[1] & 0xf, p[2] >> 4);
136 }
137 return 0;
138}
139
140static int cim_la_open(struct inode *inode, struct file *file)
141{
142 int ret;
143 unsigned int cfg;
144 struct seq_tab *p;
145 struct adapter *adap = inode->i_private;
146
147 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
148 if (ret)
149 return ret;
150
151 p = seq_open_tab(file, adap->params.cim_la_size / 8, 8 * sizeof(u32), 1,
152 cfg & UPDBGLACAPTPCONLY_F ?
153 cim_la_show_3in1 : cim_la_show);
154 if (!p)
155 return -ENOMEM;
156
157 ret = t4_cim_read_la(adap, (u32 *)p->data, NULL);
158 if (ret)
159 seq_release_private(inode, file);
160 return ret;
161}
162
163static const struct file_operations cim_la_fops = {
164 .owner = THIS_MODULE,
165 .open = cim_la_open,
166 .read = seq_read,
167 .llseek = seq_lseek,
168 .release = seq_release_private
169};
170
171static int cim_qcfg_show(struct seq_file *seq, void *v)
172{
173 static const char * const qname[] = {
174 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",
175 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI",
176 "SGE0-RX", "SGE1-RX"
177 };
178
179 int i;
180 struct adapter *adap = seq->private;
181 u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
182 u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
183 u32 stat[(4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5))];
184 u16 thres[CIM_NUM_IBQ];
185 u32 obq_wr_t4[2 * CIM_NUM_OBQ], *wr;
186 u32 obq_wr_t5[2 * CIM_NUM_OBQ_T5];
187 u32 *p = stat;
188 int cim_num_obq = is_t4(adap->params.chip) ?
189 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
190
191 i = t4_cim_read(adap, is_t4(adap->params.chip) ? UP_IBQ_0_RDADDR_A :
192 UP_IBQ_0_SHADOW_RDADDR_A,
193 ARRAY_SIZE(stat), stat);
194 if (!i) {
195 if (is_t4(adap->params.chip)) {
196 i = t4_cim_read(adap, UP_OBQ_0_REALADDR_A,
197 ARRAY_SIZE(obq_wr_t4), obq_wr_t4);
198 wr = obq_wr_t4;
199 } else {
200 i = t4_cim_read(adap, UP_OBQ_0_SHADOW_REALADDR_A,
201 ARRAY_SIZE(obq_wr_t5), obq_wr_t5);
202 wr = obq_wr_t5;
203 }
204 }
205 if (i)
206 return i;
207
208 t4_read_cimq_cfg(adap, base, size, thres);
209
210 seq_printf(seq,
211 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail\n");
212 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
213 seq_printf(seq, "%7s %5x %5u %5u %6x %4x %4u %4u %5u\n",
214 qname[i], base[i], size[i], thres[i],
215 IBQRDADDR_G(p[0]), IBQWRADDR_G(p[1]),
216 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
217 QUEREMFLITS_G(p[2]) * 16);
218 for ( ; i < CIM_NUM_IBQ + cim_num_obq; i++, p += 4, wr += 2)
219 seq_printf(seq, "%7s %5x %5u %12x %4x %4u %4u %5u\n",
220 qname[i], base[i], size[i],
221 QUERDADDR_G(p[0]) & 0x3fff, wr[0] - base[i],
222 QUESOPCNT_G(p[3]), QUEEOPCNT_G(p[3]),
223 QUEREMFLITS_G(p[2]) * 16);
224 return 0;
225}
226
227static int cim_qcfg_open(struct inode *inode, struct file *file)
228{
229 return single_open(file, cim_qcfg_show, inode->i_private);
230}
231
232static const struct file_operations cim_qcfg_fops = {
233 .owner = THIS_MODULE,
234 .open = cim_qcfg_open,
235 .read = seq_read,
236 .llseek = seq_lseek,
237 .release = single_release,
238};
239
240/* Firmware Device Log dump. */
241static const char * const devlog_level_strings[] = {
242 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
243 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
244 [FW_DEVLOG_LEVEL_ERR] = "ERR",
245 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
246 [FW_DEVLOG_LEVEL_INFO] = "INFO",
247 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
248};
249
250static const char * const devlog_facility_strings[] = {
251 [FW_DEVLOG_FACILITY_CORE] = "CORE",
252 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
253 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
254 [FW_DEVLOG_FACILITY_RES] = "RES",
255 [FW_DEVLOG_FACILITY_HW] = "HW",
256 [FW_DEVLOG_FACILITY_FLR] = "FLR",
257 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
258 [FW_DEVLOG_FACILITY_PHY] = "PHY",
259 [FW_DEVLOG_FACILITY_MAC] = "MAC",
260 [FW_DEVLOG_FACILITY_PORT] = "PORT",
261 [FW_DEVLOG_FACILITY_VI] = "VI",
262 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
263 [FW_DEVLOG_FACILITY_ACL] = "ACL",
264 [FW_DEVLOG_FACILITY_TM] = "TM",
265 [FW_DEVLOG_FACILITY_QFC] = "QFC",
266 [FW_DEVLOG_FACILITY_DCB] = "DCB",
267 [FW_DEVLOG_FACILITY_ETH] = "ETH",
268 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
269 [FW_DEVLOG_FACILITY_RI] = "RI",
270 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
271 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
272 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
273 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE"
274};
275
276/* Information gathered by Device Log Open routine for the display routine.
277 */
278struct devlog_info {
279 unsigned int nentries; /* number of entries in log[] */
280 unsigned int first; /* first [temporal] entry in log[] */
281 struct fw_devlog_e log[0]; /* Firmware Device Log */
282};
283
284/* Dump a Firmaware Device Log entry.
285 */
286static int devlog_show(struct seq_file *seq, void *v)
287{
288 if (v == SEQ_START_TOKEN)
289 seq_printf(seq, "%10s %15s %8s %8s %s\n",
290 "Seq#", "Tstamp", "Level", "Facility", "Message");
291 else {
292 struct devlog_info *dinfo = seq->private;
293 int fidx = (uintptr_t)v - 2;
294 unsigned long index;
295 struct fw_devlog_e *e;
296
297 /* Get a pointer to the log entry to display. Skip unused log
298 * entries.
299 */
300 index = dinfo->first + fidx;
301 if (index >= dinfo->nentries)
302 index -= dinfo->nentries;
303 e = &dinfo->log[index];
304 if (e->timestamp == 0)
305 return 0;
306
307 /* Print the message. This depends on the firmware using
308 * exactly the same formating strings as the kernel so we may
309 * eventually have to put a format interpreter in here ...
310 */
311 seq_printf(seq, "%10d %15llu %8s %8s ",
312 e->seqno, e->timestamp,
313 (e->level < ARRAY_SIZE(devlog_level_strings)
314 ? devlog_level_strings[e->level]
315 : "UNKNOWN"),
316 (e->facility < ARRAY_SIZE(devlog_facility_strings)
317 ? devlog_facility_strings[e->facility]
318 : "UNKNOWN"));
319 seq_printf(seq, e->fmt, e->params[0], e->params[1],
320 e->params[2], e->params[3], e->params[4],
321 e->params[5], e->params[6], e->params[7]);
322 }
323 return 0;
324}
325
326/* Sequential File Operations for Device Log.
327 */
328static inline void *devlog_get_idx(struct devlog_info *dinfo, loff_t pos)
329{
330 if (pos > dinfo->nentries)
331 return NULL;
332
333 return (void *)(uintptr_t)(pos + 1);
334}
335
336static void *devlog_start(struct seq_file *seq, loff_t *pos)
337{
338 struct devlog_info *dinfo = seq->private;
339
340 return (*pos
341 ? devlog_get_idx(dinfo, *pos)
342 : SEQ_START_TOKEN);
343}
344
345static void *devlog_next(struct seq_file *seq, void *v, loff_t *pos)
346{
347 struct devlog_info *dinfo = seq->private;
348
349 (*pos)++;
350 return devlog_get_idx(dinfo, *pos);
351}
352
353static void devlog_stop(struct seq_file *seq, void *v)
354{
355}
356
357static const struct seq_operations devlog_seq_ops = {
358 .start = devlog_start,
359 .next = devlog_next,
360 .stop = devlog_stop,
361 .show = devlog_show
362};
363
364/* Set up for reading the firmware's device log. We read the entire log here
365 * and then display it incrementally in devlog_show().
366 */
367static int devlog_open(struct inode *inode, struct file *file)
368{
369 struct adapter *adap = inode->i_private;
370 struct devlog_params *dparams = &adap->params.devlog;
371 struct devlog_info *dinfo;
372 unsigned int index;
373 u32 fseqno;
374 int ret;
375
376 /* If we don't know where the log is we can't do anything.
377 */
378 if (dparams->start == 0)
379 return -ENXIO;
380
381 /* Allocate the space to read in the firmware's device log and set up
382 * for the iterated call to our display function.
383 */
384 dinfo = __seq_open_private(file, &devlog_seq_ops,
385 sizeof(*dinfo) + dparams->size);
386 if (!dinfo)
387 return -ENOMEM;
388
389 /* Record the basic log buffer information and read in the raw log.
390 */
391 dinfo->nentries = (dparams->size / sizeof(struct fw_devlog_e));
392 dinfo->first = 0;
393 spin_lock(&adap->win0_lock);
394 ret = t4_memory_rw(adap, adap->params.drv_memwin, dparams->memtype,
395 dparams->start, dparams->size, (__be32 *)dinfo->log,
396 T4_MEMORY_READ);
397 spin_unlock(&adap->win0_lock);
398 if (ret) {
399 seq_release_private(inode, file);
400 return ret;
401 }
402
403 /* Translate log multi-byte integral elements into host native format
404 * and determine where the first entry in the log is.
405 */
406 for (fseqno = ~((u32)0), index = 0; index < dinfo->nentries; index++) {
407 struct fw_devlog_e *e = &dinfo->log[index];
408 int i;
409 __u32 seqno;
410
411 if (e->timestamp == 0)
412 continue;
413
414 e->timestamp = (__force __be64)be64_to_cpu(e->timestamp);
415 seqno = be32_to_cpu(e->seqno);
416 for (i = 0; i < 8; i++)
417 e->params[i] =
418 (__force __be32)be32_to_cpu(e->params[i]);
419
420 if (seqno < fseqno) {
421 fseqno = seqno;
422 dinfo->first = index;
423 }
424 }
425 return 0;
426}
427
428static const struct file_operations devlog_fops = {
429 .owner = THIS_MODULE,
430 .open = devlog_open,
431 .read = seq_read,
432 .llseek = seq_lseek,
433 .release = seq_release_private
434};
435
436static inline void tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
437{
438 *mask = x | y;
439 y = (__force u64)cpu_to_be64(y);
440 memcpy(addr, (char *)&y + 2, ETH_ALEN);
441}
442
443static int mps_tcam_show(struct seq_file *seq, void *v)
444{
445 if (v == SEQ_START_TOKEN)
446 seq_puts(seq, "Idx Ethernet address Mask Vld Ports PF"
447 " VF Replication "
448 "P0 P1 P2 P3 ML\n");
449 else {
450 u64 mask;
451 u8 addr[ETH_ALEN];
452 struct adapter *adap = seq->private;
453 unsigned int idx = (uintptr_t)v - 2;
454 u64 tcamy = t4_read_reg64(adap, MPS_CLS_TCAM_Y_L(idx));
455 u64 tcamx = t4_read_reg64(adap, MPS_CLS_TCAM_X_L(idx));
456 u32 cls_lo = t4_read_reg(adap, MPS_CLS_SRAM_L(idx));
457 u32 cls_hi = t4_read_reg(adap, MPS_CLS_SRAM_H(idx));
458 u32 rplc[4] = {0, 0, 0, 0};
459
460 if (tcamx & tcamy) {
461 seq_printf(seq, "%3u -\n", idx);
462 goto out;
463 }
464
465 if (cls_lo & REPLICATE_F) {
466 struct fw_ldst_cmd ldst_cmd;
467 int ret;
468
469 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
470 ldst_cmd.op_to_addrspace =
471 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
472 FW_CMD_REQUEST_F |
473 FW_CMD_READ_F |
474 FW_LDST_CMD_ADDRSPACE_V(
475 FW_LDST_ADDRSPC_MPS));
476 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
477 ldst_cmd.u.mps.fid_ctl =
478 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
479 FW_LDST_CMD_CTL_V(idx));
480 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd,
481 sizeof(ldst_cmd), &ldst_cmd);
482 if (ret)
483 dev_warn(adap->pdev_dev, "Can't read MPS "
484 "replication map for idx %d: %d\n",
485 idx, -ret);
486 else {
487 rplc[0] = ntohl(ldst_cmd.u.mps.rplc31_0);
488 rplc[1] = ntohl(ldst_cmd.u.mps.rplc63_32);
489 rplc[2] = ntohl(ldst_cmd.u.mps.rplc95_64);
490 rplc[3] = ntohl(ldst_cmd.u.mps.rplc127_96);
491 }
492 }
493
494 tcamxy2valmask(tcamx, tcamy, addr, &mask);
495 seq_printf(seq, "%3u %02x:%02x:%02x:%02x:%02x:%02x %012llx"
496 "%3c %#x%4u%4d",
497 idx, addr[0], addr[1], addr[2], addr[3], addr[4],
498 addr[5], (unsigned long long)mask,
499 (cls_lo & SRAM_VLD_F) ? 'Y' : 'N', PORTMAP_G(cls_hi),
500 PF_G(cls_lo),
501 (cls_lo & VF_VALID_F) ? VF_G(cls_lo) : -1);
502 if (cls_lo & REPLICATE_F)
503 seq_printf(seq, " %08x %08x %08x %08x",
504 rplc[3], rplc[2], rplc[1], rplc[0]);
505 else
506 seq_printf(seq, "%36c", ' ');
507 seq_printf(seq, "%4u%3u%3u%3u %#x\n",
508 SRAM_PRIO0_G(cls_lo), SRAM_PRIO1_G(cls_lo),
509 SRAM_PRIO2_G(cls_lo), SRAM_PRIO3_G(cls_lo),
510 (cls_lo >> MULTILISTEN0_S) & 0xf);
511 }
512out: return 0;
513}
514
515static inline void *mps_tcam_get_idx(struct seq_file *seq, loff_t pos)
516{
517 struct adapter *adap = seq->private;
518 int max_mac_addr = is_t4(adap->params.chip) ?
519 NUM_MPS_CLS_SRAM_L_INSTANCES :
520 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
521 return ((pos <= max_mac_addr) ? (void *)(uintptr_t)(pos + 1) : NULL);
522}
523
524static void *mps_tcam_start(struct seq_file *seq, loff_t *pos)
525{
526 return *pos ? mps_tcam_get_idx(seq, *pos) : SEQ_START_TOKEN;
527}
528
529static void *mps_tcam_next(struct seq_file *seq, void *v, loff_t *pos)
530{
531 ++*pos;
532 return mps_tcam_get_idx(seq, *pos);
533}
534
535static void mps_tcam_stop(struct seq_file *seq, void *v)
536{
537}
538
539static const struct seq_operations mps_tcam_seq_ops = {
540 .start = mps_tcam_start,
541 .next = mps_tcam_next,
542 .stop = mps_tcam_stop,
543 .show = mps_tcam_show
544};
545
546static int mps_tcam_open(struct inode *inode, struct file *file)
547{
548 int res = seq_open(file, &mps_tcam_seq_ops);
549
550 if (!res) {
551 struct seq_file *seq = file->private_data;
552
553 seq->private = inode->i_private;
554 }
555 return res;
556}
557
558static const struct file_operations mps_tcam_debugfs_fops = {
559 .owner = THIS_MODULE,
560 .open = mps_tcam_open,
561 .read = seq_read,
562 .llseek = seq_lseek,
563 .release = seq_release,
564};
565
46static ssize_t mem_read(struct file *file, char __user *buf, size_t count, 566static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
47 loff_t *ppos) 567 loff_t *ppos)
48{ 568{
@@ -121,7 +641,11 @@ int t4_setup_debugfs(struct adapter *adap)
121 u32 size; 641 u32 size;
122 642
123 static struct t4_debugfs_entry t4_debugfs_files[] = { 643 static struct t4_debugfs_entry t4_debugfs_files[] = {
644 { "cim_la", &cim_la_fops, S_IRUSR, 0 },
645 { "cim_qcfg", &cim_qcfg_fops, S_IRUSR, 0 },
646 { "devlog", &devlog_fops, S_IRUSR, 0 },
124 { "l2t", &t4_l2t_fops, S_IRUSR, 0}, 647 { "l2t", &t4_l2t_fops, S_IRUSR, 0},
648 { "mps_tcam", &mps_tcam_debugfs_fops, S_IRUSR, 0 },
125 }; 649 };
126 650
127 add_debugfs_files(adap, 651 add_debugfs_files(adap,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
index a3d8867efd3d..70fcbc930826 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_debugfs.h
@@ -44,6 +44,18 @@ struct t4_debugfs_entry {
44 unsigned char data; 44 unsigned char data;
45}; 45};
46 46
47struct seq_tab {
48 int (*show)(struct seq_file *seq, void *v, int idx);
49 unsigned int rows; /* # of entries */
50 unsigned char width; /* size in bytes of each entry */
51 unsigned char skip_first; /* whether the first line is a header */
52 char data[0]; /* the table data */
53};
54
55struct seq_tab *seq_open_tab(struct file *f, unsigned int rows,
56 unsigned int width, unsigned int have_header,
57 int (*show)(struct seq_file *seq, void *v, int i));
58
47int t4_setup_debugfs(struct adapter *adap); 59int t4_setup_debugfs(struct adapter *adap);
48void add_debugfs_files(struct adapter *adap, 60void add_debugfs_files(struct adapter *adap,
49 struct t4_debugfs_entry *files, 61 struct t4_debugfs_entry *files,
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 04e675b8218a..6de41cc6687e 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -5541,6 +5541,8 @@ static int adap_init0(struct adapter *adap)
5541 enum dev_state state; 5541 enum dev_state state;
5542 u32 params[7], val[7]; 5542 u32 params[7], val[7];
5543 struct fw_caps_config_cmd caps_cmd; 5543 struct fw_caps_config_cmd caps_cmd;
5544 struct fw_devlog_cmd devlog_cmd;
5545 u32 devlog_meminfo;
5544 int reset = 1; 5546 int reset = 1;
5545 5547
5546 /* Contact FW, advertising Master capability */ 5548 /* Contact FW, advertising Master capability */
@@ -5621,6 +5623,30 @@ static int adap_init0(struct adapter *adap)
5621 if (ret < 0) 5623 if (ret < 0)
5622 goto bye; 5624 goto bye;
5623 5625
5626 /* Read firmware device log parameters. We really need to find a way
5627 * to get these parameters initialized with some default values (which
5628 * are likely to be correct) for the case where we either don't
5629 * attache to the firmware or it's crashed when we probe the adapter.
5630 * That way we'll still be able to perform early firmware startup
5631 * debugging ... If the request to get the Firmware's Device Log
5632 * parameters fails, we'll live so we don't make that a fatal error.
5633 */
5634 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
5635 devlog_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_DEVLOG_CMD) |
5636 FW_CMD_REQUEST_F | FW_CMD_READ_F);
5637 devlog_cmd.retval_len16 = htonl(FW_LEN16(devlog_cmd));
5638 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
5639 &devlog_cmd);
5640 if (ret == 0) {
5641 devlog_meminfo =
5642 ntohl(devlog_cmd.memtype_devlog_memaddr16_devlog);
5643 adap->params.devlog.memtype =
5644 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
5645 adap->params.devlog.start =
5646 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
5647 adap->params.devlog.size = ntohl(devlog_cmd.memsize_devlog);
5648 }
5649
5624 /* 5650 /*
5625 * Find out what ports are available to us. Note that we need to do 5651 * Find out what ports are available to us. Note that we need to do
5626 * this before calling adap_init0_no_config() since it needs nports 5652 * this before calling adap_init0_no_config() since it needs nports
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index 3776279337c8..734d33e3f53b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -4031,6 +4031,7 @@ int t4_prep_adapter(struct adapter *adapter)
4031 return -EINVAL; 4031 return -EINVAL;
4032 } 4032 }
4033 4033
4034 adapter->params.cim_la_size = CIMLA_SIZE;
4034 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd); 4035 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
4035 4036
4036 /* 4037 /*
@@ -4323,3 +4324,157 @@ int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
4323 } 4324 }
4324 return 0; 4325 return 0;
4325} 4326}
4327
4328/**
4329 * t4_read_cimq_cfg - read CIM queue configuration
4330 * @adap: the adapter
4331 * @base: holds the queue base addresses in bytes
4332 * @size: holds the queue sizes in bytes
4333 * @thres: holds the queue full thresholds in bytes
4334 *
4335 * Returns the current configuration of the CIM queues, starting with
4336 * the IBQs, then the OBQs.
4337 */
4338void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
4339{
4340 unsigned int i, v;
4341 int cim_num_obq = is_t4(adap->params.chip) ?
4342 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
4343
4344 for (i = 0; i < CIM_NUM_IBQ; i++) {
4345 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
4346 QUENUMSELECT_V(i));
4347 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
4348 /* value is in 256-byte units */
4349 *base++ = CIMQBASE_G(v) * 256;
4350 *size++ = CIMQSIZE_G(v) * 256;
4351 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
4352 }
4353 for (i = 0; i < cim_num_obq; i++) {
4354 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
4355 QUENUMSELECT_V(i));
4356 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
4357 /* value is in 256-byte units */
4358 *base++ = CIMQBASE_G(v) * 256;
4359 *size++ = CIMQSIZE_G(v) * 256;
4360 }
4361}
4362
4363/**
4364 * t4_cim_read - read a block from CIM internal address space
4365 * @adap: the adapter
4366 * @addr: the start address within the CIM address space
4367 * @n: number of words to read
4368 * @valp: where to store the result
4369 *
4370 * Reads a block of 4-byte words from the CIM intenal address space.
4371 */
4372int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
4373 unsigned int *valp)
4374{
4375 int ret = 0;
4376
4377 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
4378 return -EBUSY;
4379
4380 for ( ; !ret && n--; addr += 4) {
4381 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
4382 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
4383 0, 5, 2);
4384 if (!ret)
4385 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
4386 }
4387 return ret;
4388}
4389
4390/**
4391 * t4_cim_write - write a block into CIM internal address space
4392 * @adap: the adapter
4393 * @addr: the start address within the CIM address space
4394 * @n: number of words to write
4395 * @valp: set of values to write
4396 *
4397 * Writes a block of 4-byte words into the CIM intenal address space.
4398 */
4399int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
4400 const unsigned int *valp)
4401{
4402 int ret = 0;
4403
4404 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
4405 return -EBUSY;
4406
4407 for ( ; !ret && n--; addr += 4) {
4408 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
4409 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
4410 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
4411 0, 5, 2);
4412 }
4413 return ret;
4414}
4415
4416static int t4_cim_write1(struct adapter *adap, unsigned int addr,
4417 unsigned int val)
4418{
4419 return t4_cim_write(adap, addr, 1, &val);
4420}
4421
4422/**
4423 * t4_cim_read_la - read CIM LA capture buffer
4424 * @adap: the adapter
4425 * @la_buf: where to store the LA data
4426 * @wrptr: the HW write pointer within the capture buffer
4427 *
4428 * Reads the contents of the CIM LA buffer with the most recent entry at
4429 * the end of the returned data and with the entry at @wrptr first.
4430 * We try to leave the LA in the running state we find it in.
4431 */
4432int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
4433{
4434 int i, ret;
4435 unsigned int cfg, val, idx;
4436
4437 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
4438 if (ret)
4439 return ret;
4440
4441 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
4442 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
4443 if (ret)
4444 return ret;
4445 }
4446
4447 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
4448 if (ret)
4449 goto restart;
4450
4451 idx = UPDBGLAWRPTR_G(val);
4452 if (wrptr)
4453 *wrptr = idx;
4454
4455 for (i = 0; i < adap->params.cim_la_size; i++) {
4456 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
4457 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
4458 if (ret)
4459 break;
4460 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
4461 if (ret)
4462 break;
4463 if (val & UPDBGLARDEN_F) {
4464 ret = -ETIMEDOUT;
4465 break;
4466 }
4467 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
4468 if (ret)
4469 break;
4470 idx = (idx + 1) & UPDBGLARDPTR_M;
4471 }
4472restart:
4473 if (cfg & UPDBGLAEN_F) {
4474 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
4475 cfg & ~UPDBGLARDEN_F);
4476 if (!ret)
4477 ret = r;
4478 }
4479 return ret;
4480}
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
index c19a90e7f7d1..f6b82da350e2 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.h
@@ -56,6 +56,13 @@ enum {
56}; 56};
57 57
58enum { 58enum {
59 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
60 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
61 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
62 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
63};
64
65enum {
59 SF_PAGE_SIZE = 256, /* serial flash page size */ 66 SF_PAGE_SIZE = 256, /* serial flash page size */
60 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */ 67 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
61}; 68};
@@ -110,6 +117,18 @@ enum {
110 SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */ 117 SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
111}; 118};
112 119
120/* PCI-e memory window access */
121enum pcie_memwin {
122 MEMWIN_NIC = 0,
123 MEMWIN_RSVD1 = 1,
124 MEMWIN_RSVD2 = 2,
125 MEMWIN_RDMA = 3,
126 MEMWIN_RSVD4 = 4,
127 MEMWIN_FOISCSI = 5,
128 MEMWIN_CSIOSTOR = 6,
129 MEMWIN_RSVD7 = 7,
130};
131
113struct sge_qstat { /* data written to SGE queue status entries */ 132struct sge_qstat { /* data written to SGE queue status entries */
114 __be32 qid; 133 __be32 qid;
115 __be16 cidx; 134 __be16 cidx;
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 4077227b5cea..7ce55f9be9d4 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -1708,6 +1708,66 @@
1708 1708
1709#define MPS_RX_PERR_INT_CAUSE_A 0x11074 1709#define MPS_RX_PERR_INT_CAUSE_A 0x11074
1710 1710
1711#define MPS_CLS_TCAM_Y_L_A 0xf000
1712#define MPS_CLS_TCAM_X_L_A 0xf008
1713
1714#define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
1715#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
1716
1717#define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
1718#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
1719
1720#define MPS_CLS_SRAM_L_A 0xe000
1721#define MPS_CLS_SRAM_H_A 0xe004
1722
1723#define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
1724#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
1725
1726#define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
1727#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
1728
1729#define MULTILISTEN0_S 25
1730
1731#define REPLICATE_S 11
1732#define REPLICATE_V(x) ((x) << REPLICATE_S)
1733#define REPLICATE_F REPLICATE_V(1U)
1734
1735#define PF_S 8
1736#define PF_M 0x7U
1737#define PF_G(x) (((x) >> PF_S) & PF_M)
1738
1739#define VF_VALID_S 7
1740#define VF_VALID_V(x) ((x) << VF_VALID_S)
1741#define VF_VALID_F VF_VALID_V(1U)
1742
1743#define VF_S 0
1744#define VF_M 0x7fU
1745#define VF_G(x) (((x) >> VF_S) & VF_M)
1746
1747#define SRAM_PRIO3_S 22
1748#define SRAM_PRIO3_M 0x7U
1749#define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
1750
1751#define SRAM_PRIO2_S 19
1752#define SRAM_PRIO2_M 0x7U
1753#define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
1754
1755#define SRAM_PRIO1_S 16
1756#define SRAM_PRIO1_M 0x7U
1757#define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
1758
1759#define SRAM_PRIO0_S 13
1760#define SRAM_PRIO0_M 0x7U
1761#define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
1762
1763#define SRAM_VLD_S 12
1764#define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
1765#define SRAM_VLD_F SRAM_VLD_V(1U)
1766
1767#define PORTMAP_S 0
1768#define PORTMAP_M 0xfU
1769#define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
1770
1711#define CPL_INTR_CAUSE_A 0x19054 1771#define CPL_INTR_CAUSE_A 0x19054
1712 1772
1713#define CIM_OP_MAP_PERR_S 5 1773#define CIM_OP_MAP_PERR_S 5
@@ -2062,4 +2122,93 @@
2062#define PL_VF_WHOAMI_A 0x0 2122#define PL_VF_WHOAMI_A 0x0
2063#define PL_VF_REVISION_A 0x8 2123#define PL_VF_REVISION_A 0x8
2064 2124
2125/* registers for module CIM */
2126#define CIM_HOST_ACC_CTRL_A 0x7b50
2127#define CIM_HOST_ACC_DATA_A 0x7b54
2128#define UP_UP_DBG_LA_CFG_A 0x140
2129#define UP_UP_DBG_LA_DATA_A 0x144
2130
2131#define HOSTBUSY_S 17
2132#define HOSTBUSY_V(x) ((x) << HOSTBUSY_S)
2133#define HOSTBUSY_F HOSTBUSY_V(1U)
2134
2135#define HOSTWRITE_S 16
2136#define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
2137#define HOSTWRITE_F HOSTWRITE_V(1U)
2138
2139#define UPDBGLARDEN_S 1
2140#define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
2141#define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
2142
2143#define UPDBGLAEN_S 0
2144#define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S)
2145#define UPDBGLAEN_F UPDBGLAEN_V(1U)
2146
2147#define UPDBGLARDPTR_S 2
2148#define UPDBGLARDPTR_M 0xfffU
2149#define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S)
2150
2151#define UPDBGLAWRPTR_S 16
2152#define UPDBGLAWRPTR_M 0xfffU
2153#define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
2154
2155#define UPDBGLACAPTPCONLY_S 30
2156#define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)
2157#define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
2158
2159#define CIM_QUEUE_CONFIG_REF_A 0x7b48
2160#define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
2161
2162#define CIMQSIZE_S 24
2163#define CIMQSIZE_M 0x3fU
2164#define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
2165
2166#define CIMQBASE_S 16
2167#define CIMQBASE_M 0x3fU
2168#define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
2169
2170#define QUEFULLTHRSH_S 0
2171#define QUEFULLTHRSH_M 0x1ffU
2172#define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
2173
2174#define UP_IBQ_0_RDADDR_A 0x10
2175#define UP_IBQ_0_SHADOW_RDADDR_A 0x280
2176#define UP_OBQ_0_REALADDR_A 0x104
2177#define UP_OBQ_0_SHADOW_REALADDR_A 0x394
2178
2179#define IBQRDADDR_S 0
2180#define IBQRDADDR_M 0x1fffU
2181#define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
2182
2183#define IBQWRADDR_S 0
2184#define IBQWRADDR_M 0x1fffU
2185#define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
2186
2187#define QUERDADDR_S 0
2188#define QUERDADDR_M 0x7fffU
2189#define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
2190
2191#define QUEREMFLITS_S 0
2192#define QUEREMFLITS_M 0x7ffU
2193#define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
2194
2195#define QUEEOPCNT_S 16
2196#define QUEEOPCNT_M 0xfffU
2197#define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
2198
2199#define QUESOPCNT_S 0
2200#define QUESOPCNT_M 0xfffU
2201#define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
2202
2203#define OBQSELECT_S 4
2204#define OBQSELECT_V(x) ((x) << OBQSELECT_S)
2205#define OBQSELECT_F OBQSELECT_V(1U)
2206
2207#define IBQSELECT_S 3
2208#define IBQSELECT_V(x) ((x) << IBQSELECT_S)
2209#define IBQSELECT_F IBQSELECT_V(1U)
2210
2211#define QUENUMSELECT_S 0
2212#define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
2213
2065#endif /* __T4_REGS_H */ 2214#endif /* __T4_REGS_H */
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
index 7c0aec85137a..de8283324f1f 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4fw_api.h
@@ -673,6 +673,7 @@ enum fw_cmd_opcodes {
673 FW_RSS_IND_TBL_CMD = 0x20, 673 FW_RSS_IND_TBL_CMD = 0x20,
674 FW_RSS_GLB_CONFIG_CMD = 0x22, 674 FW_RSS_GLB_CONFIG_CMD = 0x22,
675 FW_RSS_VI_CONFIG_CMD = 0x23, 675 FW_RSS_VI_CONFIG_CMD = 0x23,
676 FW_DEVLOG_CMD = 0x25,
676 FW_CLIP_CMD = 0x28, 677 FW_CLIP_CMD = 0x28,
677 FW_LASTC2E_CMD = 0x40, 678 FW_LASTC2E_CMD = 0x40,
678 FW_ERROR_CMD = 0x80, 679 FW_ERROR_CMD = 0x80,
@@ -3038,4 +3039,84 @@ enum fw_hdr_flags {
3038 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 3039 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3039}; 3040};
3040 3041
3042/* length of the formatting string */
3043#define FW_DEVLOG_FMT_LEN 192
3044
3045/* maximum number of the formatting string parameters */
3046#define FW_DEVLOG_FMT_PARAMS_NUM 8
3047
3048/* priority levels */
3049enum fw_devlog_level {
3050 FW_DEVLOG_LEVEL_EMERG = 0x0,
3051 FW_DEVLOG_LEVEL_CRIT = 0x1,
3052 FW_DEVLOG_LEVEL_ERR = 0x2,
3053 FW_DEVLOG_LEVEL_NOTICE = 0x3,
3054 FW_DEVLOG_LEVEL_INFO = 0x4,
3055 FW_DEVLOG_LEVEL_DEBUG = 0x5,
3056 FW_DEVLOG_LEVEL_MAX = 0x5,
3057};
3058
3059/* facilities that may send a log message */
3060enum fw_devlog_facility {
3061 FW_DEVLOG_FACILITY_CORE = 0x00,
3062 FW_DEVLOG_FACILITY_CF = 0x01,
3063 FW_DEVLOG_FACILITY_SCHED = 0x02,
3064 FW_DEVLOG_FACILITY_TIMER = 0x04,
3065 FW_DEVLOG_FACILITY_RES = 0x06,
3066 FW_DEVLOG_FACILITY_HW = 0x08,
3067 FW_DEVLOG_FACILITY_FLR = 0x10,
3068 FW_DEVLOG_FACILITY_DMAQ = 0x12,
3069 FW_DEVLOG_FACILITY_PHY = 0x14,
3070 FW_DEVLOG_FACILITY_MAC = 0x16,
3071 FW_DEVLOG_FACILITY_PORT = 0x18,
3072 FW_DEVLOG_FACILITY_VI = 0x1A,
3073 FW_DEVLOG_FACILITY_FILTER = 0x1C,
3074 FW_DEVLOG_FACILITY_ACL = 0x1E,
3075 FW_DEVLOG_FACILITY_TM = 0x20,
3076 FW_DEVLOG_FACILITY_QFC = 0x22,
3077 FW_DEVLOG_FACILITY_DCB = 0x24,
3078 FW_DEVLOG_FACILITY_ETH = 0x26,
3079 FW_DEVLOG_FACILITY_OFLD = 0x28,
3080 FW_DEVLOG_FACILITY_RI = 0x2A,
3081 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
3082 FW_DEVLOG_FACILITY_FCOE = 0x2E,
3083 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
3084 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
3085 FW_DEVLOG_FACILITY_MAX = 0x32,
3086};
3087
3088/* log message format */
3089struct fw_devlog_e {
3090 __be64 timestamp;
3091 __be32 seqno;
3092 __be16 reserved1;
3093 __u8 level;
3094 __u8 facility;
3095 __u8 fmt[FW_DEVLOG_FMT_LEN];
3096 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
3097 __be32 reserved3[4];
3098};
3099
3100struct fw_devlog_cmd {
3101 __be32 op_to_write;
3102 __be32 retval_len16;
3103 __u8 level;
3104 __u8 r2[7];
3105 __be32 memtype_devlog_memaddr16_devlog;
3106 __be32 memsize_devlog;
3107 __be32 r3[2];
3108};
3109
3110#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
3111#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf
3112#define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \
3113 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3114 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3115
3116#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0
3117#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff
3118#define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \
3119 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3120 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3121
3041#endif /* _T4FW_INTERFACE_H_ */ 3122#endif /* _T4FW_INTERFACE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 16:15:02 -0400