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-rw-r--r--arch/mips/bcm63xx/Kconfig4
-rw-r--r--arch/mips/bcm63xx/clk.c18
-rw-r--r--arch/mips/bcm63xx/cpu.c28
-rw-r--r--arch/mips/bcm63xx/dev-flash.c1
-rw-r--r--arch/mips/bcm63xx/dev-spi.c6
-rw-r--r--arch/mips/bcm63xx/dev-uart.c3
-rw-r--r--arch/mips/bcm63xx/irq.c19
-rw-r--r--arch/mips/bcm63xx/prom.c4
-rw-r--r--arch/mips/bcm63xx/reset.c29
-rw-r--r--arch/mips/bcm63xx/setup.c3
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h110
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h45
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h4
-rw-r--r--arch/mips/pci/pci-bcm63xx.c3
15 files changed, 259 insertions, 19 deletions
diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig
index 5639662fd503..afe52d4ed3b9 100644
--- a/arch/mips/bcm63xx/Kconfig
+++ b/arch/mips/bcm63xx/Kconfig
@@ -1,6 +1,10 @@
1menu "CPU support" 1menu "CPU support"
2 depends on BCM63XX 2 depends on BCM63XX
3 3
4config BCM63XX_CPU_3368
5 bool "support 3368 CPU"
6 select HW_HAS_PCI
7
4config BCM63XX_CPU_6328 8config BCM63XX_CPU_6328
5 bool "support 6328 CPU" 9 bool "support 6328 CPU"
6 select HW_HAS_PCI 10 select HW_HAS_PCI
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index c726a97fc798..fda2690a8ef1 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -84,7 +84,7 @@ static void enetx_set(struct clk *clk, int enable)
84 else 84 else
85 clk_disable_unlocked(&clk_enet_misc); 85 clk_disable_unlocked(&clk_enet_misc);
86 86
87 if (BCMCPU_IS_6358()) { 87 if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
88 u32 mask; 88 u32 mask;
89 89
90 if (clk->id == 0) 90 if (clk->id == 0)
@@ -110,9 +110,8 @@ static struct clk clk_enet1 = {
110 */ 110 */
111static void ephy_set(struct clk *clk, int enable) 111static void ephy_set(struct clk *clk, int enable)
112{ 112{
113 if (!BCMCPU_IS_6358()) 113 if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
114 return; 114 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
115 bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable);
116} 115}
117 116
118 117
@@ -155,9 +154,10 @@ static struct clk clk_enetsw = {
155 */ 154 */
156static void pcm_set(struct clk *clk, int enable) 155static void pcm_set(struct clk *clk, int enable)
157{ 156{
158 if (!BCMCPU_IS_6358()) 157 if (BCMCPU_IS_3368())
159 return; 158 bcm_hwclock_set(CKCTL_3368_PCM_EN, enable);
160 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); 159 if (BCMCPU_IS_6358())
160 bcm_hwclock_set(CKCTL_6358_PCM_EN, enable);
161} 161}
162 162
163static struct clk clk_pcm = { 163static struct clk clk_pcm = {
@@ -211,7 +211,7 @@ static void spi_set(struct clk *clk, int enable)
211 mask = CKCTL_6338_SPI_EN; 211 mask = CKCTL_6338_SPI_EN;
212 else if (BCMCPU_IS_6348()) 212 else if (BCMCPU_IS_6348())
213 mask = CKCTL_6348_SPI_EN; 213 mask = CKCTL_6348_SPI_EN;
214 else if (BCMCPU_IS_6358()) 214 else if (BCMCPU_IS_3368() || BCMCPU_IS_6358())
215 mask = CKCTL_6358_SPI_EN; 215 mask = CKCTL_6358_SPI_EN;
216 else if (BCMCPU_IS_6362()) 216 else if (BCMCPU_IS_6362())
217 mask = CKCTL_6362_SPI_EN; 217 mask = CKCTL_6362_SPI_EN;
@@ -338,7 +338,7 @@ struct clk *clk_get(struct device *dev, const char *id)
338 return &clk_xtm; 338 return &clk_xtm;
339 if (!strcmp(id, "periph")) 339 if (!strcmp(id, "periph"))
340 return &clk_periph; 340 return &clk_periph;
341 if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) 341 if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
342 return &clk_pcm; 342 return &clk_pcm;
343 if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec")) 343 if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
344 return &clk_ipsec; 344 return &clk_ipsec;
diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c
index 79fe32df5e96..7e17374a9ae8 100644
--- a/arch/mips/bcm63xx/cpu.c
+++ b/arch/mips/bcm63xx/cpu.c
@@ -29,6 +29,14 @@ static u8 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq; 29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size; 30static unsigned int bcm63xx_memory_size;
31 31
32static const unsigned long bcm3368_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(3368)
34};
35
36static const int bcm3368_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(3368)
38};
39
32static const unsigned long bcm6328_regs_base[] = { 40static const unsigned long bcm6328_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6328) 41 __GEN_CPU_REGS_TABLE(6328)
34}; 42};
@@ -116,6 +124,9 @@ unsigned int bcm63xx_get_memory_size(void)
116static unsigned int detect_cpu_clock(void) 124static unsigned int detect_cpu_clock(void)
117{ 125{
118 switch (bcm63xx_get_cpu_id()) { 126 switch (bcm63xx_get_cpu_id()) {
127 case BCM3368_CPU_ID:
128 return 300000000;
129
119 case BCM6328_CPU_ID: 130 case BCM6328_CPU_ID:
120 { 131 {
121 unsigned int tmp, mips_pll_fcvo; 132 unsigned int tmp, mips_pll_fcvo;
@@ -266,7 +277,7 @@ static unsigned int detect_memory_size(void)
266 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; 277 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
267 } 278 }
268 279
269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) { 280 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
270 val = bcm_memc_readl(MEMC_CFG_REG); 281 val = bcm_memc_readl(MEMC_CFG_REG);
271 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; 282 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
272 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; 283 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
@@ -302,10 +313,17 @@ void __init bcm63xx_cpu_init(void)
302 chipid_reg = BCM_6345_PERF_BASE; 313 chipid_reg = BCM_6345_PERF_BASE;
303 break; 314 break;
304 case CPU_BMIPS4350: 315 case CPU_BMIPS4350:
305 if ((read_c0_prid() & 0xf0) == 0x10) 316 switch ((read_c0_prid() & 0xff)) {
317 case 0x04:
318 chipid_reg = BCM_3368_PERF_BASE;
319 break;
320 case 0x10:
306 chipid_reg = BCM_6345_PERF_BASE; 321 chipid_reg = BCM_6345_PERF_BASE;
307 else 322 break;
323 default:
308 chipid_reg = BCM_6368_PERF_BASE; 324 chipid_reg = BCM_6368_PERF_BASE;
325 break;
326 }
309 break; 327 break;
310 } 328 }
311 329
@@ -322,6 +340,10 @@ void __init bcm63xx_cpu_init(void)
322 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; 340 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
323 341
324 switch (bcm63xx_cpu_id) { 342 switch (bcm63xx_cpu_id) {
343 case BCM3368_CPU_ID:
344 bcm63xx_regs_base = bcm3368_regs_base;
345 bcm63xx_irqs = bcm3368_irqs;
346 break;
325 case BCM6328_CPU_ID: 347 case BCM6328_CPU_ID:
326 bcm63xx_regs_base = bcm6328_regs_base; 348 bcm63xx_regs_base = bcm6328_regs_base;
327 bcm63xx_irqs = bcm6328_irqs; 349 bcm63xx_irqs = bcm6328_irqs;
diff --git a/arch/mips/bcm63xx/dev-flash.c b/arch/mips/bcm63xx/dev-flash.c
index 588d1ec622e4..172dd8397178 100644
--- a/arch/mips/bcm63xx/dev-flash.c
+++ b/arch/mips/bcm63xx/dev-flash.c
@@ -71,6 +71,7 @@ static int __init bcm63xx_detect_flash_type(void)
71 case BCM6348_CPU_ID: 71 case BCM6348_CPU_ID:
72 /* no way to auto detect so assume parallel */ 72 /* no way to auto detect so assume parallel */
73 return BCM63XX_FLASH_TYPE_PARALLEL; 73 return BCM63XX_FLASH_TYPE_PARALLEL;
74 case BCM3368_CPU_ID:
74 case BCM6358_CPU_ID: 75 case BCM6358_CPU_ID:
75 val = bcm_gpio_readl(GPIO_STRAPBUS_REG); 76 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
76 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL) 77 if (val & STRAPBUS_6358_BOOT_SEL_PARALLEL)
diff --git a/arch/mips/bcm63xx/dev-spi.c b/arch/mips/bcm63xx/dev-spi.c
index 3065bb61820d..d12daed749bc 100644
--- a/arch/mips/bcm63xx/dev-spi.c
+++ b/arch/mips/bcm63xx/dev-spi.c
@@ -37,7 +37,8 @@ static __init void bcm63xx_spi_regs_init(void)
37{ 37{
38 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) 38 if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
39 bcm63xx_regs_spi = bcm6348_regs_spi; 39 bcm63xx_regs_spi = bcm6348_regs_spi;
40 if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) 40 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
41 BCMCPU_IS_6362() || BCMCPU_IS_6368())
41 bcm63xx_regs_spi = bcm6358_regs_spi; 42 bcm63xx_regs_spi = bcm6358_regs_spi;
42} 43}
43#else 44#else
@@ -87,7 +88,8 @@ int __init bcm63xx_spi_register(void)
87 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH; 88 spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
88 } 89 }
89 90
90 if (BCMCPU_IS_6358() || BCMCPU_IS_6362() || BCMCPU_IS_6368()) { 91 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
92 BCMCPU_IS_6368()) {
91 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1; 93 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
92 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE; 94 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
93 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT; 95 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c
index d6e42c608325..3bc7f3bfc9ad 100644
--- a/arch/mips/bcm63xx/dev-uart.c
+++ b/arch/mips/bcm63xx/dev-uart.c
@@ -54,7 +54,8 @@ int __init bcm63xx_uart_register(unsigned int id)
54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices)) 54 if (id >= ARRAY_SIZE(bcm63xx_uart_devices))
55 return -ENODEV; 55 return -ENODEV;
56 56
57 if (id == 1 && (!BCMCPU_IS_6358() && !BCMCPU_IS_6368())) 57 if (id == 1 && (!BCMCPU_IS_3368() && !BCMCPU_IS_6358() &&
58 !BCMCPU_IS_6368()))
58 return -ENODEV; 59 return -ENODEV;
59 60
60 if (id == 0) { 61 if (id == 0) {
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index d744606e19e9..1525f8a3841b 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused; 27static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
28 28
29#ifndef BCMCPU_RUNTIME_DETECT 29#ifndef BCMCPU_RUNTIME_DETECT
30#ifdef CONFIG_BCM63XX_CPU_3368
31#define irq_stat_reg PERF_IRQSTAT_3368_REG
32#define irq_mask_reg PERF_IRQMASK_3368_REG
33#define irq_bits 32
34#define is_ext_irq_cascaded 0
35#define ext_irq_start 0
36#define ext_irq_end 0
37#define ext_irq_count 4
38#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_3368
39#define ext_irq_cfg_reg2 0
40#endif
30#ifdef CONFIG_BCM63XX_CPU_6328 41#ifdef CONFIG_BCM63XX_CPU_6328
31#define irq_stat_reg PERF_IRQSTAT_6328_REG 42#define irq_stat_reg PERF_IRQSTAT_6328_REG
32#define irq_mask_reg PERF_IRQMASK_6328_REG 43#define irq_mask_reg PERF_IRQMASK_6328_REG
@@ -140,6 +151,13 @@ static void bcm63xx_init_irq(void)
140 irq_mask_addr = bcm63xx_regset_address(RSET_PERF); 151 irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
141 152
142 switch (bcm63xx_get_cpu_id()) { 153 switch (bcm63xx_get_cpu_id()) {
154 case BCM3368_CPU_ID:
155 irq_stat_addr += PERF_IRQSTAT_3368_REG;
156 irq_mask_addr += PERF_IRQMASK_3368_REG;
157 irq_bits = 32;
158 ext_irq_count = 4;
159 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
160 break;
143 case BCM6328_CPU_ID: 161 case BCM6328_CPU_ID:
144 irq_stat_addr += PERF_IRQSTAT_6328_REG; 162 irq_stat_addr += PERF_IRQSTAT_6328_REG;
145 irq_mask_addr += PERF_IRQMASK_6328_REG; 163 irq_mask_addr += PERF_IRQMASK_6328_REG;
@@ -479,6 +497,7 @@ static int bcm63xx_external_irq_set_type(struct irq_data *d,
479 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq); 497 reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
480 break; 498 break;
481 499
500 case BCM3368_CPU_ID:
482 case BCM6328_CPU_ID: 501 case BCM6328_CPU_ID:
483 case BCM6338_CPU_ID: 502 case BCM6338_CPU_ID:
484 case BCM6345_CPU_ID: 503 case BCM6345_CPU_ID:
diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c
index fd698087fbfd..f3ff28f4c258 100644
--- a/arch/mips/bcm63xx/prom.c
+++ b/arch/mips/bcm63xx/prom.c
@@ -26,7 +26,9 @@ void __init prom_init(void)
26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); 26 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
27 27
28 /* disable all hardware blocks clock for now */ 28 /* disable all hardware blocks clock for now */
29 if (BCMCPU_IS_6328()) 29 if (BCMCPU_IS_3368())
30 mask = CKCTL_3368_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6328())
30 mask = CKCTL_6328_ALL_SAFE_EN; 32 mask = CKCTL_6328_ALL_SAFE_EN;
31 else if (BCMCPU_IS_6338()) 33 else if (BCMCPU_IS_6338())
32 mask = CKCTL_6338_ALL_SAFE_EN; 34 mask = CKCTL_6338_ALL_SAFE_EN;
diff --git a/arch/mips/bcm63xx/reset.c b/arch/mips/bcm63xx/reset.c
index 317931c6cf58..acbeb1fe7c57 100644
--- a/arch/mips/bcm63xx/reset.c
+++ b/arch/mips/bcm63xx/reset.c
@@ -30,6 +30,19 @@
30 [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \ 30 [BCM63XX_RESET_PCIE] = BCM## __cpu ##_RESET_PCIE, \
31 [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT, 31 [BCM63XX_RESET_PCIE_EXT] = BCM## __cpu ##_RESET_PCIE_EXT,
32 32
33#define BCM3368_RESET_SPI SOFTRESET_3368_SPI_MASK
34#define BCM3368_RESET_ENET SOFTRESET_3368_ENET_MASK
35#define BCM3368_RESET_USBH 0
36#define BCM3368_RESET_USBD SOFTRESET_3368_USBS_MASK
37#define BCM3368_RESET_DSL 0
38#define BCM3368_RESET_SAR 0
39#define BCM3368_RESET_EPHY SOFTRESET_3368_EPHY_MASK
40#define BCM3368_RESET_ENETSW 0
41#define BCM3368_RESET_PCM SOFTRESET_3368_PCM_MASK
42#define BCM3368_RESET_MPI SOFTRESET_3368_MPI_MASK
43#define BCM3368_RESET_PCIE 0
44#define BCM3368_RESET_PCIE_EXT 0
45
33#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK 46#define BCM6328_RESET_SPI SOFTRESET_6328_SPI_MASK
34#define BCM6328_RESET_ENET 0 47#define BCM6328_RESET_ENET 0
35#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK 48#define BCM6328_RESET_USBH SOFTRESET_6328_USBH_MASK
@@ -117,6 +130,10 @@
117/* 130/*
118 * core reset bits 131 * core reset bits
119 */ 132 */
133static const u32 bcm3368_reset_bits[] = {
134 __GEN_RESET_BITS_TABLE(3368)
135};
136
120static const u32 bcm6328_reset_bits[] = { 137static const u32 bcm6328_reset_bits[] = {
121 __GEN_RESET_BITS_TABLE(6328) 138 __GEN_RESET_BITS_TABLE(6328)
122}; 139};
@@ -146,7 +163,10 @@ static int reset_reg;
146 163
147static int __init bcm63xx_reset_bits_init(void) 164static int __init bcm63xx_reset_bits_init(void)
148{ 165{
149 if (BCMCPU_IS_6328()) { 166 if (BCMCPU_IS_3368()) {
167 reset_reg = PERF_SOFTRESET_6358_REG;
168 bcm63xx_reset_bits = bcm3368_reset_bits;
169 } else if (BCMCPU_IS_6328()) {
150 reset_reg = PERF_SOFTRESET_6328_REG; 170 reset_reg = PERF_SOFTRESET_6328_REG;
151 bcm63xx_reset_bits = bcm6328_reset_bits; 171 bcm63xx_reset_bits = bcm6328_reset_bits;
152 } else if (BCMCPU_IS_6338()) { 172 } else if (BCMCPU_IS_6338()) {
@@ -170,6 +190,13 @@ static int __init bcm63xx_reset_bits_init(void)
170} 190}
171#else 191#else
172 192
193#ifdef CONFIG_BCM63XX_CPU_3368
194static const u32 bcm63xx_reset_bits[] = {
195 __GEN_RESET_BITS_TABLE(3368)
196};
197#define reset_reg PERF_SOFTRESET_6358_REG
198#endif
199
173#ifdef CONFIG_BCM63XX_CPU_6328 200#ifdef CONFIG_BCM63XX_CPU_6328
174static const u32 bcm63xx_reset_bits[] = { 201static const u32 bcm63xx_reset_bits[] = {
175 __GEN_RESET_BITS_TABLE(6328) 202 __GEN_RESET_BITS_TABLE(6328)
diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c
index 24a24445db64..6660c7ddf87b 100644
--- a/arch/mips/bcm63xx/setup.c
+++ b/arch/mips/bcm63xx/setup.c
@@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
68 68
69 /* mask and clear all external irq */ 69 /* mask and clear all external irq */
70 switch (bcm63xx_get_cpu_id()) { 70 switch (bcm63xx_get_cpu_id()) {
71 case BCM3368_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_3368;
73 break;
71 case BCM6328_CPU_ID: 74 case BCM6328_CPU_ID:
72 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328; 75 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
73 break; 76 break;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index 336228990808..9d3c08e4a7e4 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,6 +9,7 @@
9 * compile time if only one CPU support is enabled (idea stolen from 9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types) 10 * arm mach-types)
11 */ 11 */
12#define BCM3368_CPU_ID 0x3368
12#define BCM6328_CPU_ID 0x6328 13#define BCM6328_CPU_ID 0x6328
13#define BCM6338_CPU_ID 0x6338 14#define BCM6338_CPU_ID 0x6338
14#define BCM6345_CPU_ID 0x6345 15#define BCM6345_CPU_ID 0x6345
@@ -22,6 +23,19 @@ u16 __bcm63xx_get_cpu_id(void);
22u8 bcm63xx_get_cpu_rev(void); 23u8 bcm63xx_get_cpu_rev(void);
23unsigned int bcm63xx_get_cpu_freq(void); 24unsigned int bcm63xx_get_cpu_freq(void);
24 25
26#ifdef CONFIG_BCM63XX_CPU_3368
27# ifdef bcm63xx_get_cpu_id
28# undef bcm63xx_get_cpu_id
29# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
30# define BCMCPU_RUNTIME_DETECT
31# else
32# define bcm63xx_get_cpu_id() BCM3368_CPU_ID
33# endif
34# define BCMCPU_IS_3368() (bcm63xx_get_cpu_id() == BCM3368_CPU_ID)
35#else
36# define BCMCPU_IS_3368() (0)
37#endif
38
25#ifdef CONFIG_BCM63XX_CPU_6328 39#ifdef CONFIG_BCM63XX_CPU_6328
26# ifdef bcm63xx_get_cpu_id 40# ifdef bcm63xx_get_cpu_id
27# undef bcm63xx_get_cpu_id 41# undef bcm63xx_get_cpu_id
@@ -191,6 +205,53 @@ enum bcm63xx_regs_set {
191#define RSET_RNG_SIZE 20 205#define RSET_RNG_SIZE 20
192 206
193/* 207/*
208 * 3368 register sets base address
209 */
210#define BCM_3368_DSL_LMEM_BASE (0xdeadbeef)
211#define BCM_3368_PERF_BASE (0xfff8c000)
212#define BCM_3368_TIMER_BASE (0xfff8c040)
213#define BCM_3368_WDT_BASE (0xfff8c080)
214#define BCM_3368_UART0_BASE (0xfff8c100)
215#define BCM_3368_UART1_BASE (0xfff8c120)
216#define BCM_3368_GPIO_BASE (0xfff8c080)
217#define BCM_3368_SPI_BASE (0xfff8c800)
218#define BCM_3368_HSSPI_BASE (0xdeadbeef)
219#define BCM_3368_UDC0_BASE (0xdeadbeef)
220#define BCM_3368_USBDMA_BASE (0xdeadbeef)
221#define BCM_3368_OHCI0_BASE (0xdeadbeef)
222#define BCM_3368_OHCI_PRIV_BASE (0xdeadbeef)
223#define BCM_3368_USBH_PRIV_BASE (0xdeadbeef)
224#define BCM_3368_USBD_BASE (0xdeadbeef)
225#define BCM_3368_MPI_BASE (0xfff80000)
226#define BCM_3368_PCMCIA_BASE (0xfff80054)
227#define BCM_3368_PCIE_BASE (0xdeadbeef)
228#define BCM_3368_SDRAM_REGS_BASE (0xdeadbeef)
229#define BCM_3368_DSL_BASE (0xdeadbeef)
230#define BCM_3368_UBUS_BASE (0xdeadbeef)
231#define BCM_3368_ENET0_BASE (0xfff98000)
232#define BCM_3368_ENET1_BASE (0xfff98800)
233#define BCM_3368_ENETDMA_BASE (0xfff99800)
234#define BCM_3368_ENETDMAC_BASE (0xfff99900)
235#define BCM_3368_ENETDMAS_BASE (0xfff99a00)
236#define BCM_3368_ENETSW_BASE (0xdeadbeef)
237#define BCM_3368_EHCI0_BASE (0xdeadbeef)
238#define BCM_3368_SDRAM_BASE (0xdeadbeef)
239#define BCM_3368_MEMC_BASE (0xfff84000)
240#define BCM_3368_DDR_BASE (0xdeadbeef)
241#define BCM_3368_M2M_BASE (0xdeadbeef)
242#define BCM_3368_ATM_BASE (0xdeadbeef)
243#define BCM_3368_XTM_BASE (0xdeadbeef)
244#define BCM_3368_XTMDMA_BASE (0xdeadbeef)
245#define BCM_3368_XTMDMAC_BASE (0xdeadbeef)
246#define BCM_3368_XTMDMAS_BASE (0xdeadbeef)
247#define BCM_3368_PCM_BASE (0xfff9c200)
248#define BCM_3368_PCMDMA_BASE (0xdeadbeef)
249#define BCM_3368_PCMDMAC_BASE (0xdeadbeef)
250#define BCM_3368_PCMDMAS_BASE (0xdeadbeef)
251#define BCM_3368_RNG_BASE (0xdeadbeef)
252#define BCM_3368_MISC_BASE (0xdeadbeef)
253
254/*
194 * 6328 register sets base address 255 * 6328 register sets base address
195 */ 256 */
196#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef) 257#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
@@ -620,6 +681,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
620#ifdef BCMCPU_RUNTIME_DETECT 681#ifdef BCMCPU_RUNTIME_DETECT
621 return bcm63xx_regs_base[set]; 682 return bcm63xx_regs_base[set];
622#else 683#else
684#ifdef CONFIG_BCM63XX_CPU_3368
685 __GEN_RSET(3368)
686#endif
623#ifdef CONFIG_BCM63XX_CPU_6328 687#ifdef CONFIG_BCM63XX_CPU_6328
624 __GEN_RSET(6328) 688 __GEN_RSET(6328)
625#endif 689#endif
@@ -687,6 +751,52 @@ enum bcm63xx_irq {
687}; 751};
688 752
689/* 753/*
754 * 3368 irqs
755 */
756#define BCM_3368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
757#define BCM_3368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
758#define BCM_3368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
759#define BCM_3368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
760#define BCM_3368_DSL_IRQ 0
761#define BCM_3368_UDC0_IRQ 0
762#define BCM_3368_OHCI0_IRQ 0
763#define BCM_3368_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
764#define BCM_3368_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
765#define BCM_3368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
766#define BCM_3368_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
767#define BCM_3368_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
768#define BCM_3368_HSSPI_IRQ 0
769#define BCM_3368_EHCI0_IRQ 0
770#define BCM_3368_USBD_IRQ 0
771#define BCM_3368_USBD_RXDMA0_IRQ 0
772#define BCM_3368_USBD_TXDMA0_IRQ 0
773#define BCM_3368_USBD_RXDMA1_IRQ 0
774#define BCM_3368_USBD_TXDMA1_IRQ 0
775#define BCM_3368_USBD_RXDMA2_IRQ 0
776#define BCM_3368_USBD_TXDMA2_IRQ 0
777#define BCM_3368_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
778#define BCM_3368_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
779#define BCM_3368_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
780#define BCM_3368_PCMCIA_IRQ 0
781#define BCM_3368_ATM_IRQ 0
782#define BCM_3368_ENETSW_RXDMA0_IRQ 0
783#define BCM_3368_ENETSW_RXDMA1_IRQ 0
784#define BCM_3368_ENETSW_RXDMA2_IRQ 0
785#define BCM_3368_ENETSW_RXDMA3_IRQ 0
786#define BCM_3368_ENETSW_TXDMA0_IRQ 0
787#define BCM_3368_ENETSW_TXDMA1_IRQ 0
788#define BCM_3368_ENETSW_TXDMA2_IRQ 0
789#define BCM_3368_ENETSW_TXDMA3_IRQ 0
790#define BCM_3368_XTM_IRQ 0
791#define BCM_3368_XTM_DMA0_IRQ 0
792
793#define BCM_3368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
794#define BCM_3368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
795#define BCM_3368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
796#define BCM_3368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
797
798
799/*
690 * 6328 irqs 800 * 6328 irqs
691 */ 801 */
692#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32) 802#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 35baa1a60a64..565ff36a1119 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -11,6 +11,7 @@ static inline unsigned long bcm63xx_gpio_count(void)
11 switch (bcm63xx_get_cpu_id()) { 11 switch (bcm63xx_get_cpu_id()) {
12 case BCM6328_CPU_ID: 12 case BCM6328_CPU_ID:
13 return 32; 13 return 32;
14 case BCM3368_CPU_ID:
14 case BCM6358_CPU_ID: 15 case BCM6358_CPU_ID:
15 return 40; 16 return 40;
16 case BCM6338_CPU_ID: 17 case BCM6338_CPU_ID:
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 3203fe49b34d..654213746b32 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,6 +15,39 @@
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
17 17
18#define CKCTL_3368_MAC_EN (1 << 3)
19#define CKCTL_3368_TC_EN (1 << 5)
20#define CKCTL_3368_US_TOP_EN (1 << 6)
21#define CKCTL_3368_DS_TOP_EN (1 << 7)
22#define CKCTL_3368_APM_EN (1 << 8)
23#define CKCTL_3368_SPI_EN (1 << 9)
24#define CKCTL_3368_USBS_EN (1 << 10)
25#define CKCTL_3368_BMU_EN (1 << 11)
26#define CKCTL_3368_PCM_EN (1 << 12)
27#define CKCTL_3368_NTP_EN (1 << 13)
28#define CKCTL_3368_ACP_B_EN (1 << 14)
29#define CKCTL_3368_ACP_A_EN (1 << 15)
30#define CKCTL_3368_EMUSB_EN (1 << 17)
31#define CKCTL_3368_ENET0_EN (1 << 18)
32#define CKCTL_3368_ENET1_EN (1 << 19)
33#define CKCTL_3368_USBU_EN (1 << 20)
34#define CKCTL_3368_EPHY_EN (1 << 21)
35
36#define CKCTL_3368_ALL_SAFE_EN (CKCTL_3368_MAC_EN | \
37 CKCTL_3368_TC_EN | \
38 CKCTL_3368_US_TOP_EN | \
39 CKCTL_3368_DS_TOP_EN | \
40 CKCTL_3368_APM_EN | \
41 CKCTL_3368_SPI_EN | \
42 CKCTL_3368_USBS_EN | \
43 CKCTL_3368_BMU_EN | \
44 CKCTL_3368_PCM_EN | \
45 CKCTL_3368_NTP_EN | \
46 CKCTL_3368_ACP_B_EN | \
47 CKCTL_3368_ACP_A_EN | \
48 CKCTL_3368_EMUSB_EN | \
49 CKCTL_3368_USBU_EN)
50
18#define CKCTL_6328_PHYMIPS_EN (1 << 0) 51#define CKCTL_6328_PHYMIPS_EN (1 << 0)
19#define CKCTL_6328_ADSL_QPROC_EN (1 << 1) 52#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20#define CKCTL_6328_ADSL_AFE_EN (1 << 2) 53#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
@@ -181,6 +214,7 @@
181#define SYS_PLL_SOFT_RESET 0x1 214#define SYS_PLL_SOFT_RESET 0x1
182 215
183/* Interrupt Mask register */ 216/* Interrupt Mask register */
217#define PERF_IRQMASK_3368_REG 0xc
184#define PERF_IRQMASK_6328_REG 0x20 218#define PERF_IRQMASK_6328_REG 0x20
185#define PERF_IRQMASK_6338_REG 0xc 219#define PERF_IRQMASK_6338_REG 0xc
186#define PERF_IRQMASK_6345_REG 0xc 220#define PERF_IRQMASK_6345_REG 0xc
@@ -190,6 +224,7 @@
190#define PERF_IRQMASK_6368_REG 0x20 224#define PERF_IRQMASK_6368_REG 0x20
191 225
192/* Interrupt Status register */ 226/* Interrupt Status register */
227#define PERF_IRQSTAT_3368_REG 0x10
193#define PERF_IRQSTAT_6328_REG 0x28 228#define PERF_IRQSTAT_6328_REG 0x28
194#define PERF_IRQSTAT_6338_REG 0x10 229#define PERF_IRQSTAT_6338_REG 0x10
195#define PERF_IRQSTAT_6345_REG 0x10 230#define PERF_IRQSTAT_6345_REG 0x10
@@ -199,6 +234,7 @@
199#define PERF_IRQSTAT_6368_REG 0x28 234#define PERF_IRQSTAT_6368_REG 0x28
200 235
201/* External Interrupt Configuration register */ 236/* External Interrupt Configuration register */
237#define PERF_EXTIRQ_CFG_REG_3368 0x14
202#define PERF_EXTIRQ_CFG_REG_6328 0x18 238#define PERF_EXTIRQ_CFG_REG_6328 0x18
203#define PERF_EXTIRQ_CFG_REG_6338 0x14 239#define PERF_EXTIRQ_CFG_REG_6338 0x14
204#define PERF_EXTIRQ_CFG_REG_6345 0x14 240#define PERF_EXTIRQ_CFG_REG_6345 0x14
@@ -236,6 +272,13 @@
236#define PERF_SOFTRESET_6362_REG 0x10 272#define PERF_SOFTRESET_6362_REG 0x10
237#define PERF_SOFTRESET_6368_REG 0x10 273#define PERF_SOFTRESET_6368_REG 0x10
238 274
275#define SOFTRESET_3368_SPI_MASK (1 << 0)
276#define SOFTRESET_3368_ENET_MASK (1 << 2)
277#define SOFTRESET_3368_MPI_MASK (1 << 3)
278#define SOFTRESET_3368_EPHY_MASK (1 << 6)
279#define SOFTRESET_3368_USBS_MASK (1 << 11)
280#define SOFTRESET_3368_PCM_MASK (1 << 13)
281
239#define SOFTRESET_6328_SPI_MASK (1 << 0) 282#define SOFTRESET_6328_SPI_MASK (1 << 0)
240#define SOFTRESET_6328_EPHY_MASK (1 << 1) 283#define SOFTRESET_6328_EPHY_MASK (1 << 1)
241#define SOFTRESET_6328_SAR_MASK (1 << 2) 284#define SOFTRESET_6328_SAR_MASK (1 << 2)
@@ -1293,7 +1336,7 @@
1293#define SPI_6348_RX_DATA 0x80 1336#define SPI_6348_RX_DATA 0x80
1294#define SPI_6348_RX_DATA_SIZE 0x3f 1337#define SPI_6348_RX_DATA_SIZE 0x3f
1295 1338
1296/* BCM 6358/6262/6368 SPI core */ 1339/* BCM 3368/6358/6262/6368 SPI core */
1297#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */ 1340#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1298#define SPI_6358_MSG_CTL_WIDTH 16 1341#define SPI_6358_MSG_CTL_WIDTH 16
1299#define SPI_6358_MSG_DATA 0x02 1342#define SPI_6358_MSG_DATA 0x02
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
index 94e3011ba7df..ff15e3b14e7a 100644
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
@@ -11,6 +11,10 @@ static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
11static inline int is_bcm63xx_internal_registers(phys_t offset) 11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{ 12{
13 switch (bcm63xx_get_cpu_id()) { 13 switch (bcm63xx_get_cpu_id()) {
14 case BCM3368_CPU_ID:
15 if (offset >= 0xfff80000)
16 return 1;
17 break;
14 case BCM6338_CPU_ID: 18 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID: 19 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID: 20 case BCM6348_CPU_ID:
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index 2eb954239bc5..151d9b5870bb 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -266,7 +266,7 @@ static int __init bcm63xx_register_pci(void)
266 /* setup PCI to local bus access, used by PCI device to target 266 /* setup PCI to local bus access, used by PCI device to target
267 * local RAM while bus mastering */ 267 * local RAM while bus mastering */
268 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); 268 bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
269 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) 269 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6368())
270 val = MPI_SP0_REMAP_ENABLE_MASK; 270 val = MPI_SP0_REMAP_ENABLE_MASK;
271 else 271 else
272 val = 0; 272 val = 0;
@@ -338,6 +338,7 @@ static int __init bcm63xx_pci_init(void)
338 case BCM6328_CPU_ID: 338 case BCM6328_CPU_ID:
339 case BCM6362_CPU_ID: 339 case BCM6362_CPU_ID:
340 return bcm63xx_register_pcie(); 340 return bcm63xx_register_pcie();
341 case BCM3368_CPU_ID:
341 case BCM6348_CPU_ID: 342 case BCM6348_CPU_ID:
342 case BCM6358_CPU_ID: 343 case BCM6358_CPU_ID:
343 case BCM6368_CPU_ID: 344 case BCM6368_CPU_ID:
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 14:20:37 -0400