diff options
-rw-r--r-- | arch/powerpc/platforms/cell/spu_base.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index d152a3fbdb83..269dda4fd0b4 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c | |||
@@ -486,14 +486,13 @@ int spu_irq_class_1_bottom(struct spu *spu) | |||
486 | 486 | ||
487 | ea = spu->dar; | 487 | ea = spu->dar; |
488 | dsisr = spu->dsisr; | 488 | dsisr = spu->dsisr; |
489 | if (dsisr & MFC_DSISR_PTE_NOT_FOUND) { | 489 | if (dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)) { |
490 | access = (_PAGE_PRESENT | _PAGE_USER); | 490 | access = (_PAGE_PRESENT | _PAGE_USER); |
491 | access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL; | 491 | access |= (dsisr & MFC_DSISR_ACCESS_PUT) ? _PAGE_RW : 0UL; |
492 | if (hash_page(ea, access, 0x300) != 0) | 492 | if (hash_page(ea, access, 0x300) != 0) |
493 | error |= CLASS1_ENABLE_STORAGE_FAULT_INTR; | 493 | error |= CLASS1_ENABLE_STORAGE_FAULT_INTR; |
494 | } | 494 | } |
495 | if ((error & CLASS1_ENABLE_STORAGE_FAULT_INTR) || | 495 | if (error & CLASS1_ENABLE_STORAGE_FAULT_INTR) { |
496 | (dsisr & MFC_DSISR_ACCESS_DENIED)) { | ||
497 | if ((ret = spu_handle_mm_fault(spu)) != 0) | 496 | if ((ret = spu_handle_mm_fault(spu)) != 0) |
498 | error |= CLASS1_ENABLE_STORAGE_FAULT_INTR; | 497 | error |= CLASS1_ENABLE_STORAGE_FAULT_INTR; |
499 | else | 498 | else |