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-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/kernel/perf_event.c936
2 files changed, 933 insertions, 5 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9fb91ce106bc..1d10b9064567 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1176,7 +1176,7 @@ config HIGHPTE
1176 1176
1177config HW_PERF_EVENTS 1177config HW_PERF_EVENTS
1178 bool "Enable hardware performance counter support for perf events" 1178 bool "Enable hardware performance counter support for perf events"
1179 depends on PERF_EVENTS && CPU_HAS_PMU && CPU_V6 1179 depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
1180 default y 1180 default y
1181 help 1181 help
1182 Enable hardware performance counter support for perf events. If 1182 Enable hardware performance counter support for perf events. If
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 7b1022b9aa52..c54ceb3d1f97 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -5,6 +5,9 @@
5 * 5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles 6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * 7 *
8 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
9 * 2010 (c) MontaVista Software, LLC.
10 *
8 * This code is based on the sparc64 perf event code, which is in turn based 11 * This code is based on the sparc64 perf event code, which is in turn based
9 * on the x86 code. Callchain code is based on the ARM OProfile backtrace 12 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
10 * code. 13 * code.
@@ -35,8 +38,12 @@ DEFINE_SPINLOCK(pmu_lock);
35 * ARMv6 supports a maximum of 3 events, starting from index 1. If we add 38 * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
36 * another platform that supports more, we need to increase this to be the 39 * another platform that supports more, we need to increase this to be the
37 * largest of all platforms. 40 * largest of all platforms.
41 *
42 * ARMv7 supports up to 32 events:
43 * cycle counter CCNT + 31 events counters CNT0..30.
44 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
38 */ 45 */
39#define ARMPMU_MAX_HWEVENTS 4 46#define ARMPMU_MAX_HWEVENTS 33
40 47
41/* The events for a given CPU. */ 48/* The events for a given CPU. */
42struct cpu_hw_events { 49struct cpu_hw_events {
@@ -61,7 +68,7 @@ struct cpu_hw_events {
61DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 68DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
62 69
63struct arm_pmu { 70struct arm_pmu {
64 const char *name; 71 char *name;
65 irqreturn_t (*handle_irq)(int irq_num, void *dev); 72 irqreturn_t (*handle_irq)(int irq_num, void *dev);
66 void (*enable)(struct hw_perf_event *evt, int idx); 73 void (*enable)(struct hw_perf_event *evt, int idx);
67 void (*disable)(struct hw_perf_event *evt, int idx); 74 void (*disable)(struct hw_perf_event *evt, int idx);
@@ -1174,6 +1181,903 @@ static const struct arm_pmu armv6mpcore_pmu = {
1174 .max_period = (1LLU << 32) - 1, 1181 .max_period = (1LLU << 32) - 1,
1175}; 1182};
1176 1183
1184/*
1185 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
1186 *
1187 * Copied from ARMv6 code, with the low level code inspired
1188 * by the ARMv7 Oprofile code.
1189 *
1190 * Cortex-A8 has up to 4 configurable performance counters and
1191 * a single cycle counter.
1192 * Cortex-A9 has up to 31 configurable performance counters and
1193 * a single cycle counter.
1194 *
1195 * All counters can be enabled/disabled and IRQ masked separately. The cycle
1196 * counter and all 4 performance counters together can be reset separately.
1197 */
1198
1199#define ARMV7_PMU_CORTEX_A8_NAME "ARMv7 Cortex-A8"
1200
1201#define ARMV7_PMU_CORTEX_A9_NAME "ARMv7 Cortex-A9"
1202
1203/* Common ARMv7 event types */
1204enum armv7_perf_types {
1205 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
1206 ARMV7_PERFCTR_IFETCH_MISS = 0x01,
1207 ARMV7_PERFCTR_ITLB_MISS = 0x02,
1208 ARMV7_PERFCTR_DCACHE_REFILL = 0x03,
1209 ARMV7_PERFCTR_DCACHE_ACCESS = 0x04,
1210 ARMV7_PERFCTR_DTLB_REFILL = 0x05,
1211 ARMV7_PERFCTR_DREAD = 0x06,
1212 ARMV7_PERFCTR_DWRITE = 0x07,
1213
1214 ARMV7_PERFCTR_EXC_TAKEN = 0x09,
1215 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
1216 ARMV7_PERFCTR_CID_WRITE = 0x0B,
1217 /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
1218 * It counts:
1219 * - all branch instructions,
1220 * - instructions that explicitly write the PC,
1221 * - exception generating instructions.
1222 */
1223 ARMV7_PERFCTR_PC_WRITE = 0x0C,
1224 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
1225 ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F,
1226 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
1227 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
1228
1229 ARMV7_PERFCTR_PC_BRANCH_MIS_USED = 0x12,
1230
1231 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
1232};
1233
1234/* ARMv7 Cortex-A8 specific event types */
1235enum armv7_a8_perf_types {
1236 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
1237
1238 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
1239
1240 ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40,
1241 ARMV7_PERFCTR_L2_STORE_MERGED = 0x41,
1242 ARMV7_PERFCTR_L2_STORE_BUFF = 0x42,
1243 ARMV7_PERFCTR_L2_ACCESS = 0x43,
1244 ARMV7_PERFCTR_L2_CACH_MISS = 0x44,
1245 ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45,
1246 ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46,
1247 ARMV7_PERFCTR_MEMORY_REPLAY = 0x47,
1248 ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48,
1249 ARMV7_PERFCTR_L1_DATA_MISS = 0x49,
1250 ARMV7_PERFCTR_L1_INST_MISS = 0x4A,
1251 ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B,
1252 ARMV7_PERFCTR_L1_NEON_DATA = 0x4C,
1253 ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D,
1254 ARMV7_PERFCTR_L2_NEON = 0x4E,
1255 ARMV7_PERFCTR_L2_NEON_HIT = 0x4F,
1256 ARMV7_PERFCTR_L1_INST = 0x50,
1257 ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51,
1258 ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52,
1259 ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53,
1260 ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54,
1261 ARMV7_PERFCTR_OP_EXECUTED = 0x55,
1262 ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56,
1263 ARMV7_PERFCTR_CYCLES_INST = 0x57,
1264 ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58,
1265 ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59,
1266 ARMV7_PERFCTR_NEON_CYCLES = 0x5A,
1267
1268 ARMV7_PERFCTR_PMU0_EVENTS = 0x70,
1269 ARMV7_PERFCTR_PMU1_EVENTS = 0x71,
1270 ARMV7_PERFCTR_PMU_EVENTS = 0x72,
1271};
1272
1273/* ARMv7 Cortex-A9 specific event types */
1274enum armv7_a9_perf_types {
1275 ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40,
1276 ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41,
1277 ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42,
1278
1279 ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50,
1280 ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51,
1281
1282 ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60,
1283 ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61,
1284 ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
1285 ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63,
1286 ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64,
1287 ARMV7_PERFCTR_DATA_EVICTION = 0x65,
1288 ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66,
1289 ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67,
1290 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68,
1291
1292 ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
1293
1294 ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70,
1295 ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
1296 ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72,
1297 ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73,
1298 ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74,
1299
1300 ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
1301 ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81,
1302 ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82,
1303 ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83,
1304 ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84,
1305 ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85,
1306 ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86,
1307
1308 ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A,
1309 ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
1310
1311 ARMV7_PERFCTR_ISB_INST = 0x90,
1312 ARMV7_PERFCTR_DSB_INST = 0x91,
1313 ARMV7_PERFCTR_DMB_INST = 0x92,
1314 ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93,
1315
1316 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0,
1317 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1,
1318 ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2,
1319 ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3,
1320 ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4,
1321 ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
1322};
1323
1324/*
1325 * Cortex-A8 HW events mapping
1326 *
1327 * The hardware events that we support. We do support cache operations but
1328 * we have harvard caches and no way to combine instruction and data
1329 * accesses/misses in hardware.
1330 */
1331static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
1332 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1333 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
1334 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
1335 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
1336 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1337 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1338 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1339};
1340
1341static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1342 [PERF_COUNT_HW_CACHE_OP_MAX]
1343 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1344 [C(L1D)] = {
1345 /*
1346 * The performance counters don't differentiate between read
1347 * and write accesses/misses so this isn't strictly correct,
1348 * but it's the best we can do. Writes and reads get
1349 * combined.
1350 */
1351 [C(OP_READ)] = {
1352 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1353 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1354 },
1355 [C(OP_WRITE)] = {
1356 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1357 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1358 },
1359 [C(OP_PREFETCH)] = {
1360 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1361 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1362 },
1363 },
1364 [C(L1I)] = {
1365 [C(OP_READ)] = {
1366 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1367 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1368 },
1369 [C(OP_WRITE)] = {
1370 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1371 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1372 },
1373 [C(OP_PREFETCH)] = {
1374 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1375 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1376 },
1377 },
1378 [C(LL)] = {
1379 [C(OP_READ)] = {
1380 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1381 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1382 },
1383 [C(OP_WRITE)] = {
1384 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1385 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1386 },
1387 [C(OP_PREFETCH)] = {
1388 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1389 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1390 },
1391 },
1392 [C(DTLB)] = {
1393 /*
1394 * Only ITLB misses and DTLB refills are supported.
1395 * If users want the DTLB refills misses a raw counter
1396 * must be used.
1397 */
1398 [C(OP_READ)] = {
1399 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1400 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1401 },
1402 [C(OP_WRITE)] = {
1403 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1404 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1405 },
1406 [C(OP_PREFETCH)] = {
1407 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1408 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1409 },
1410 },
1411 [C(ITLB)] = {
1412 [C(OP_READ)] = {
1413 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1414 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1415 },
1416 [C(OP_WRITE)] = {
1417 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1418 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1419 },
1420 [C(OP_PREFETCH)] = {
1421 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1422 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1423 },
1424 },
1425 [C(BPU)] = {
1426 [C(OP_READ)] = {
1427 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1428 [C(RESULT_MISS)]
1429 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1430 },
1431 [C(OP_WRITE)] = {
1432 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1433 [C(RESULT_MISS)]
1434 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1435 },
1436 [C(OP_PREFETCH)] = {
1437 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1438 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1439 },
1440 },
1441};
1442
1443/*
1444 * Cortex-A9 HW events mapping
1445 */
1446static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
1447 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1448 [PERF_COUNT_HW_INSTRUCTIONS] =
1449 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
1450 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
1451 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
1452 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1453 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1454 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1455};
1456
1457static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1458 [PERF_COUNT_HW_CACHE_OP_MAX]
1459 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1460 [C(L1D)] = {
1461 /*
1462 * The performance counters don't differentiate between read
1463 * and write accesses/misses so this isn't strictly correct,
1464 * but it's the best we can do. Writes and reads get
1465 * combined.
1466 */
1467 [C(OP_READ)] = {
1468 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1469 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1470 },
1471 [C(OP_WRITE)] = {
1472 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1473 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1474 },
1475 [C(OP_PREFETCH)] = {
1476 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1477 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1478 },
1479 },
1480 [C(L1I)] = {
1481 [C(OP_READ)] = {
1482 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1483 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1484 },
1485 [C(OP_WRITE)] = {
1486 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1487 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1488 },
1489 [C(OP_PREFETCH)] = {
1490 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1491 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1492 },
1493 },
1494 [C(LL)] = {
1495 [C(OP_READ)] = {
1496 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1497 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1498 },
1499 [C(OP_WRITE)] = {
1500 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1501 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1502 },
1503 [C(OP_PREFETCH)] = {
1504 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1505 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1506 },
1507 },
1508 [C(DTLB)] = {
1509 /*
1510 * Only ITLB misses and DTLB refills are supported.
1511 * If users want the DTLB refills misses a raw counter
1512 * must be used.
1513 */
1514 [C(OP_READ)] = {
1515 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1516 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1517 },
1518 [C(OP_WRITE)] = {
1519 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1520 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1521 },
1522 [C(OP_PREFETCH)] = {
1523 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1524 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1525 },
1526 },
1527 [C(ITLB)] = {
1528 [C(OP_READ)] = {
1529 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1530 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1531 },
1532 [C(OP_WRITE)] = {
1533 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1534 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1535 },
1536 [C(OP_PREFETCH)] = {
1537 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1538 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1539 },
1540 },
1541 [C(BPU)] = {
1542 [C(OP_READ)] = {
1543 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1544 [C(RESULT_MISS)]
1545 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1546 },
1547 [C(OP_WRITE)] = {
1548 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1549 [C(RESULT_MISS)]
1550 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1551 },
1552 [C(OP_PREFETCH)] = {
1553 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1554 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1555 },
1556 },
1557};
1558
1559/*
1560 * Perf Events counters
1561 */
1562enum armv7_counters {
1563 ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */
1564 ARMV7_COUNTER0 = 2, /* First event counter */
1565};
1566
1567/*
1568 * The cycle counter is ARMV7_CYCLE_COUNTER.
1569 * The first event counter is ARMV7_COUNTER0.
1570 * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
1571 */
1572#define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1)
1573
1574/*
1575 * ARMv7 low level PMNC access
1576 */
1577
1578/*
1579 * Per-CPU PMNC: config reg
1580 */
1581#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
1582#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
1583#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
1584#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
1585#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
1586#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
1587#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
1588#define ARMV7_PMNC_N_MASK 0x1f
1589#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
1590
1591/*
1592 * Available counters
1593 */
1594#define ARMV7_CNT0 0 /* First event counter */
1595#define ARMV7_CCNT 31 /* Cycle counter */
1596
1597/* Perf Event to low level counters mapping */
1598#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
1599
1600/*
1601 * CNTENS: counters enable reg
1602 */
1603#define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1604#define ARMV7_CNTENS_C (1 << ARMV7_CCNT)
1605
1606/*
1607 * CNTENC: counters disable reg
1608 */
1609#define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1610#define ARMV7_CNTENC_C (1 << ARMV7_CCNT)
1611
1612/*
1613 * INTENS: counters overflow interrupt enable reg
1614 */
1615#define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1616#define ARMV7_INTENS_C (1 << ARMV7_CCNT)
1617
1618/*
1619 * INTENC: counters overflow interrupt disable reg
1620 */
1621#define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1622#define ARMV7_INTENC_C (1 << ARMV7_CCNT)
1623
1624/*
1625 * EVTSEL: Event selection reg
1626 */
1627#define ARMV7_EVTSEL_MASK 0x7f /* Mask for writable bits */
1628
1629/*
1630 * SELECT: Counter selection reg
1631 */
1632#define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */
1633
1634/*
1635 * FLAG: counters overflow flag status reg
1636 */
1637#define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1638#define ARMV7_FLAG_C (1 << ARMV7_CCNT)
1639#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
1640#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
1641
1642static inline unsigned long armv7_pmnc_read(void)
1643{
1644 u32 val;
1645 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
1646 return val;
1647}
1648
1649static inline void armv7_pmnc_write(unsigned long val)
1650{
1651 val &= ARMV7_PMNC_MASK;
1652 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
1653}
1654
1655static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
1656{
1657 return pmnc & ARMV7_OVERFLOWED_MASK;
1658}
1659
1660static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
1661 enum armv7_counters counter)
1662{
1663 int ret;
1664
1665 if (counter == ARMV7_CYCLE_COUNTER)
1666 ret = pmnc & ARMV7_FLAG_C;
1667 else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
1668 ret = pmnc & ARMV7_FLAG_P(counter);
1669 else
1670 pr_err("CPU%u checking wrong counter %d overflow status\n",
1671 smp_processor_id(), counter);
1672
1673 return ret;
1674}
1675
1676static inline int armv7_pmnc_select_counter(unsigned int idx)
1677{
1678 u32 val;
1679
1680 if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
1681 pr_err("CPU%u selecting wrong PMNC counter"
1682 " %d\n", smp_processor_id(), idx);
1683 return -1;
1684 }
1685
1686 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
1687 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
1688
1689 return idx;
1690}
1691
1692static inline u32 armv7pmu_read_counter(int idx)
1693{
1694 unsigned long value = 0;
1695
1696 if (idx == ARMV7_CYCLE_COUNTER)
1697 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
1698 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1699 if (armv7_pmnc_select_counter(idx) == idx)
1700 asm volatile("mrc p15, 0, %0, c9, c13, 2"
1701 : "=r" (value));
1702 } else
1703 pr_err("CPU%u reading wrong counter %d\n",
1704 smp_processor_id(), idx);
1705
1706 return value;
1707}
1708
1709static inline void armv7pmu_write_counter(int idx, u32 value)
1710{
1711 if (idx == ARMV7_CYCLE_COUNTER)
1712 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
1713 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1714 if (armv7_pmnc_select_counter(idx) == idx)
1715 asm volatile("mcr p15, 0, %0, c9, c13, 2"
1716 : : "r" (value));
1717 } else
1718 pr_err("CPU%u writing wrong counter %d\n",
1719 smp_processor_id(), idx);
1720}
1721
1722static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
1723{
1724 if (armv7_pmnc_select_counter(idx) == idx) {
1725 val &= ARMV7_EVTSEL_MASK;
1726 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
1727 }
1728}
1729
1730static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
1731{
1732 u32 val;
1733
1734 if ((idx != ARMV7_CYCLE_COUNTER) &&
1735 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1736 pr_err("CPU%u enabling wrong PMNC counter"
1737 " %d\n", smp_processor_id(), idx);
1738 return -1;
1739 }
1740
1741 if (idx == ARMV7_CYCLE_COUNTER)
1742 val = ARMV7_CNTENS_C;
1743 else
1744 val = ARMV7_CNTENS_P(idx);
1745
1746 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
1747
1748 return idx;
1749}
1750
1751static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
1752{
1753 u32 val;
1754
1755
1756 if ((idx != ARMV7_CYCLE_COUNTER) &&
1757 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1758 pr_err("CPU%u disabling wrong PMNC counter"
1759 " %d\n", smp_processor_id(), idx);
1760 return -1;
1761 }
1762
1763 if (idx == ARMV7_CYCLE_COUNTER)
1764 val = ARMV7_CNTENC_C;
1765 else
1766 val = ARMV7_CNTENC_P(idx);
1767
1768 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
1769
1770 return idx;
1771}
1772
1773static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
1774{
1775 u32 val;
1776
1777 if ((idx != ARMV7_CYCLE_COUNTER) &&
1778 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1779 pr_err("CPU%u enabling wrong PMNC counter"
1780 " interrupt enable %d\n", smp_processor_id(), idx);
1781 return -1;
1782 }
1783
1784 if (idx == ARMV7_CYCLE_COUNTER)
1785 val = ARMV7_INTENS_C;
1786 else
1787 val = ARMV7_INTENS_P(idx);
1788
1789 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
1790
1791 return idx;
1792}
1793
1794static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
1795{
1796 u32 val;
1797
1798 if ((idx != ARMV7_CYCLE_COUNTER) &&
1799 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1800 pr_err("CPU%u disabling wrong PMNC counter"
1801 " interrupt enable %d\n", smp_processor_id(), idx);
1802 return -1;
1803 }
1804
1805 if (idx == ARMV7_CYCLE_COUNTER)
1806 val = ARMV7_INTENC_C;
1807 else
1808 val = ARMV7_INTENC_P(idx);
1809
1810 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
1811
1812 return idx;
1813}
1814
1815static inline u32 armv7_pmnc_getreset_flags(void)
1816{
1817 u32 val;
1818
1819 /* Read */
1820 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1821
1822 /* Write to clear flags */
1823 val &= ARMV7_FLAG_MASK;
1824 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
1825
1826 return val;
1827}
1828
1829#ifdef DEBUG
1830static void armv7_pmnc_dump_regs(void)
1831{
1832 u32 val;
1833 unsigned int cnt;
1834
1835 printk(KERN_INFO "PMNC registers dump:\n");
1836
1837 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
1838 printk(KERN_INFO "PMNC =0x%08x\n", val);
1839
1840 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
1841 printk(KERN_INFO "CNTENS=0x%08x\n", val);
1842
1843 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
1844 printk(KERN_INFO "INTENS=0x%08x\n", val);
1845
1846 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1847 printk(KERN_INFO "FLAGS =0x%08x\n", val);
1848
1849 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
1850 printk(KERN_INFO "SELECT=0x%08x\n", val);
1851
1852 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
1853 printk(KERN_INFO "CCNT =0x%08x\n", val);
1854
1855 for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
1856 armv7_pmnc_select_counter(cnt);
1857 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
1858 printk(KERN_INFO "CNT[%d] count =0x%08x\n",
1859 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1860 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
1861 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
1862 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1863 }
1864}
1865#endif
1866
1867void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1868{
1869 unsigned long flags;
1870
1871 /*
1872 * Enable counter and interrupt, and set the counter to count
1873 * the event that we're interested in.
1874 */
1875 spin_lock_irqsave(&pmu_lock, flags);
1876
1877 /*
1878 * Disable counter
1879 */
1880 armv7_pmnc_disable_counter(idx);
1881
1882 /*
1883 * Set event (if destined for PMNx counters)
1884 * We don't need to set the event if it's a cycle count
1885 */
1886 if (idx != ARMV7_CYCLE_COUNTER)
1887 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1888
1889 /*
1890 * Enable interrupt for this counter
1891 */
1892 armv7_pmnc_enable_intens(idx);
1893
1894 /*
1895 * Enable counter
1896 */
1897 armv7_pmnc_enable_counter(idx);
1898
1899 spin_unlock_irqrestore(&pmu_lock, flags);
1900}
1901
1902static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
1903{
1904 unsigned long flags;
1905
1906 /*
1907 * Disable counter and interrupt
1908 */
1909 spin_lock_irqsave(&pmu_lock, flags);
1910
1911 /*
1912 * Disable counter
1913 */
1914 armv7_pmnc_disable_counter(idx);
1915
1916 /*
1917 * Disable interrupt for this counter
1918 */
1919 armv7_pmnc_disable_intens(idx);
1920
1921 spin_unlock_irqrestore(&pmu_lock, flags);
1922}
1923
1924static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1925{
1926 unsigned long pmnc;
1927 struct perf_sample_data data;
1928 struct cpu_hw_events *cpuc;
1929 struct pt_regs *regs;
1930 int idx;
1931
1932 /*
1933 * Get and reset the IRQ flags
1934 */
1935 pmnc = armv7_pmnc_getreset_flags();
1936
1937 /*
1938 * Did an overflow occur?
1939 */
1940 if (!armv7_pmnc_has_overflowed(pmnc))
1941 return IRQ_NONE;
1942
1943 /*
1944 * Handle the counter(s) overflow(s)
1945 */
1946 regs = get_irq_regs();
1947
1948 data.addr = 0;
1949
1950 cpuc = &__get_cpu_var(cpu_hw_events);
1951 for (idx = 0; idx <= armpmu->num_events; ++idx) {
1952 struct perf_event *event = cpuc->events[idx];
1953 struct hw_perf_event *hwc;
1954
1955 if (!test_bit(idx, cpuc->active_mask))
1956 continue;
1957
1958 /*
1959 * We have a single interrupt for all counters. Check that
1960 * each counter has overflowed before we process it.
1961 */
1962 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
1963 continue;
1964
1965 hwc = &event->hw;
1966 armpmu_event_update(event, hwc, idx);
1967 data.period = event->hw.last_period;
1968 if (!armpmu_event_set_period(event, hwc, idx))
1969 continue;
1970
1971 if (perf_event_overflow(event, 0, &data, regs))
1972 armpmu->disable(hwc, idx);
1973 }
1974
1975 /*
1976 * Handle the pending perf events.
1977 *
1978 * Note: this call *must* be run with interrupts enabled. For
1979 * platforms that can have the PMU interrupts raised as a PMI, this
1980 * will not work.
1981 */
1982 perf_event_do_pending();
1983
1984 return IRQ_HANDLED;
1985}
1986
1987static void armv7pmu_start(void)
1988{
1989 unsigned long flags;
1990
1991 spin_lock_irqsave(&pmu_lock, flags);
1992 /* Enable all counters */
1993 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
1994 spin_unlock_irqrestore(&pmu_lock, flags);
1995}
1996
1997static void armv7pmu_stop(void)
1998{
1999 unsigned long flags;
2000
2001 spin_lock_irqsave(&pmu_lock, flags);
2002 /* Disable all counters */
2003 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
2004 spin_unlock_irqrestore(&pmu_lock, flags);
2005}
2006
2007static inline int armv7_a8_pmu_event_map(int config)
2008{
2009 int mapping = armv7_a8_perf_map[config];
2010 if (HW_OP_UNSUPPORTED == mapping)
2011 mapping = -EOPNOTSUPP;
2012 return mapping;
2013}
2014
2015static inline int armv7_a9_pmu_event_map(int config)
2016{
2017 int mapping = armv7_a9_perf_map[config];
2018 if (HW_OP_UNSUPPORTED == mapping)
2019 mapping = -EOPNOTSUPP;
2020 return mapping;
2021}
2022
2023static u64 armv7pmu_raw_event(u64 config)
2024{
2025 return config & 0xff;
2026}
2027
2028static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
2029 struct hw_perf_event *event)
2030{
2031 int idx;
2032
2033 /* Always place a cycle counter into the cycle counter. */
2034 if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
2035 if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
2036 return -EAGAIN;
2037
2038 return ARMV7_CYCLE_COUNTER;
2039 } else {
2040 /*
2041 * For anything other than a cycle counter, try and use
2042 * the events counters
2043 */
2044 for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
2045 if (!test_and_set_bit(idx, cpuc->used_mask))
2046 return idx;
2047 }
2048
2049 /* The counters are all in use. */
2050 return -EAGAIN;
2051 }
2052}
2053
2054static struct arm_pmu armv7pmu = {
2055 .handle_irq = armv7pmu_handle_irq,
2056 .enable = armv7pmu_enable_event,
2057 .disable = armv7pmu_disable_event,
2058 .raw_event = armv7pmu_raw_event,
2059 .read_counter = armv7pmu_read_counter,
2060 .write_counter = armv7pmu_write_counter,
2061 .get_event_idx = armv7pmu_get_event_idx,
2062 .start = armv7pmu_start,
2063 .stop = armv7pmu_stop,
2064 .max_period = (1LLU << 32) - 1,
2065};
2066
2067static u32 __init armv7_reset_read_pmnc(void)
2068{
2069 u32 nb_cnt;
2070
2071 /* Initialize & Reset PMNC: C and P bits */
2072 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
2073
2074 /* Read the nb of CNTx counters supported from PMNC */
2075 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
2076
2077 /* Add the CPU cycles counter and return */
2078 return nb_cnt + 1;
2079}
2080
1177static int __init 2081static int __init
1178init_hw_perf_events(void) 2082init_hw_perf_events(void)
1179{ 2083{
@@ -1199,6 +2103,30 @@ init_hw_perf_events(void)
1199 sizeof(armv6mpcore_perf_cache_map)); 2103 sizeof(armv6mpcore_perf_cache_map));
1200 perf_max_events = armv6mpcore_pmu.num_events; 2104 perf_max_events = armv6mpcore_pmu.num_events;
1201 break; 2105 break;
2106 case 0xC080: /* Cortex-A8 */
2107 armv7pmu.name = ARMV7_PMU_CORTEX_A8_NAME;
2108 memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
2109 sizeof(armv7_a8_perf_cache_map));
2110 armv7pmu.event_map = armv7_a8_pmu_event_map;
2111 armpmu = &armv7pmu;
2112
2113 /* Reset PMNC and read the nb of CNTx counters
2114 supported */
2115 armv7pmu.num_events = armv7_reset_read_pmnc();
2116 perf_max_events = armv7pmu.num_events;
2117 break;
2118 case 0xC090: /* Cortex-A9 */
2119 armv7pmu.name = ARMV7_PMU_CORTEX_A9_NAME;
2120 memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
2121 sizeof(armv7_a9_perf_cache_map));
2122 armv7pmu.event_map = armv7_a9_pmu_event_map;
2123 armpmu = &armv7pmu;
2124
2125 /* Reset PMNC and read the nb of CNTx counters
2126 supported */
2127 armv7pmu.num_events = armv7_reset_read_pmnc();
2128 perf_max_events = armv7pmu.num_events;
2129 break;
1202 default: 2130 default:
1203 pr_info("no hardware support available\n"); 2131 pr_info("no hardware support available\n");
1204 perf_max_events = -1; 2132 perf_max_events = -1;
@@ -1206,8 +2134,8 @@ init_hw_perf_events(void)
1206 } 2134 }
1207 2135
1208 if (armpmu) 2136 if (armpmu)
1209 pr_info("enabled with %s PMU driver\n", 2137 pr_info("enabled with %s PMU driver, %d counters available\n",
1210 armpmu->name); 2138 armpmu->name, armpmu->num_events);
1211 2139
1212 return 0; 2140 return 0;
1213} 2141}
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-31 14:54:00 -0500