3 files changed, 30 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 27f32962e55c..4eac8dcea423 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -34,6 +34,7 @@
                         reg = <0x0 0x0>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@1 {
                         device_type = "cpu";
@@ -41,6 +42,7 @@
                         reg = <0x0 0x1>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@2 {
                         device_type = "cpu";
@@ -48,6 +50,7 @@
                         reg = <0x0 0x2>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@3 {
                         device_type = "cpu";
@@ -55,6 +58,11 @@
                         reg = <0x0 0x3>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
+                };
+
+                L2_0: l2-cache0 {
+                        compatible = "cache";
                 };
         };
 
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index d429129ecb3d..133ee59de2d7 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -39,6 +39,7 @@
                         reg = <0x0 0x0>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A57_L2>;
                 };
 
                 A57_1: cpu@1 {
@@ -46,6 +47,7 @@
                         reg = <0x0 0x1>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A57_L2>;
                 };
 
                 A53_0: cpu@100 {
@@ -53,6 +55,7 @@
                         reg = <0x0 0x100>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
                 };
 
                 A53_1: cpu@101 {
@@ -60,6 +63,7 @@
                         reg = <0x0 0x101>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
                 };
 
                 A53_2: cpu@102 {
@@ -67,6 +71,7 @@
                         reg = <0x0 0x102>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
                 };
 
                 A53_3: cpu@103 {
@@ -74,6 +79,15 @@
                         reg = <0x0 0x103>;
                         device_type = "cpu";
                         enable-method = "psci";
+                        next-level-cache = <&A53_L2>;
+                };
+
+                A57_L2: l2-cache0 {
+                        compatible = "cache";
+                };
+
+                A53_L2: l2-cache1 {
+                        compatible = "cache";
                 };
         };
 
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index efc59b3baf63..20addabbd127 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -37,6 +37,7 @@
                         reg = <0x0 0x0>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@1 {
                         device_type = "cpu";
@@ -44,6 +45,7 @@
                         reg = <0x0 0x1>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@2 {
                         device_type = "cpu";
@@ -51,6 +53,7 @@
                         reg = <0x0 0x2>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
                 };
                 cpu@3 {
                         device_type = "cpu";
@@ -58,6 +61,11 @@
                         reg = <0x0 0x3>;
                         enable-method = "spin-table";
                         cpu-release-addr = <0x0 0x8000fff8>;
+                        next-level-cache = <&L2_0>;
+                };
+
+                L2_0: l2-cache0 {
+                        compatible = "cache";
                 };
         };