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-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c2
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h4
-rw-r--r--arch/arm/mach-mx5/mm.c2
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx2-wdt.c9
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h2
5 files changed, 17 insertions, 2 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index c66be0ee40c9..8164b1dd9520 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1336,6 +1336,8 @@ static struct clk_lookup mx53_lookups[] = {
1336 _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk) 1336 _REGISTER_CLOCK("imx53-ecspi.0", NULL, ecspi1_clk)
1337 _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk) 1337 _REGISTER_CLOCK("imx53-ecspi.1", NULL, ecspi2_clk)
1338 _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk) 1338 _REGISTER_CLOCK("imx53-cspi.0", NULL, cspi_clk)
1339 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1340 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1339}; 1341};
1340 1342
1341static void clk_tree_init(void) 1343static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 8639735a117b..9251008dad1f 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -29,3 +29,7 @@ imx53_sdhci_esdhc_imx_data[] __initconst;
29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst; 29extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
30#define imx53_add_ecspi(id, pdata) \ 30#define imx53_add_ecspi(id, pdata) \
31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata) 31 imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
32
33extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
34#define imx53_add_imx2_wdt(id, pdata) \
35 imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 8730cd1b94b1..ff557301b42b 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -66,7 +66,7 @@ void __init imx53_init_early(void)
66{ 66{
67 mxc_set_cpu_type(MXC_CPU_MX53); 67 mxc_set_cpu_type(MXC_CPU_MX53);
68 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR)); 68 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
69 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR)); 69 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
70} 70}
71 71
72int imx51_register_gpios(void); 72int imx51_register_gpios(void);
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
index e0aec61177f4..5e07ef2bf1c4 100644
--- a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -53,6 +53,15 @@ const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
53}; 53};
54#endif /* ifdef CONFIG_SOC_IMX51 */ 54#endif /* ifdef CONFIG_SOC_IMX51 */
55 55
56#ifdef CONFIG_SOC_IMX53
57const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst = {
58#define imx53_imx2_wdt_data_entry(_id, _hwid) \
59 imx_imx2_wdt_data_entry(MX53, _id, _hwid, SZ_16K)
60 imx53_imx2_wdt_data_entry(0, 1),
61 imx53_imx2_wdt_data_entry(1, 2),
62};
63#endif /* ifdef CONFIG_SOC_IMX53 */
64
56struct platform_device *__init imx_add_imx2_wdt( 65struct platform_device *__init imx_add_imx2_wdt(
57 const struct imx_imx2_wdt_data *data) 66 const struct imx_imx2_wdt_data *data)
58{ 67{
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index d7a8e52181ea..ace17864575e 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -79,7 +79,7 @@
79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000) 79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000) 80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000) 81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
82#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000) 82#define MX53_WDOG1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000) 83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000) 84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000) 85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)