diff options
| -rw-r--r-- | arch/arm/boot/dts/socfpga.dtsi | 290 |
1 files changed, 145 insertions, 145 deletions
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index e7260ca9eaf1..0207a6af5fd2 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi | |||
| @@ -243,197 +243,197 @@ | |||
| 243 | }; | 243 | }; |
| 244 | }; | 244 | }; |
| 245 | 245 | ||
| 246 | mpu_periph_clk: mpu_periph_clk { | 246 | mpu_periph_clk: mpu_periph_clk { |
| 247 | #clock-cells = <0>; | 247 | #clock-cells = <0>; |
| 248 | compatible = "altr,socfpga-gate-clk"; | 248 | compatible = "altr,socfpga-gate-clk"; |
| 249 | clocks = <&mpuclk>; | 249 | clocks = <&mpuclk>; |
| 250 | fixed-divider = <4>; | 250 | fixed-divider = <4>; |
| 251 | }; | 251 | }; |
| 252 | 252 | ||
| 253 | mpu_l2_ram_clk: mpu_l2_ram_clk { | 253 | mpu_l2_ram_clk: mpu_l2_ram_clk { |
| 254 | #clock-cells = <0>; | 254 | #clock-cells = <0>; |
| 255 | compatible = "altr,socfpga-gate-clk"; | 255 | compatible = "altr,socfpga-gate-clk"; |
| 256 | clocks = <&mpuclk>; | 256 | clocks = <&mpuclk>; |
| 257 | fixed-divider = <2>; | 257 | fixed-divider = <2>; |
| 258 | }; | 258 | }; |
| 259 | 259 | ||
| 260 | l4_main_clk: l4_main_clk { | 260 | l4_main_clk: l4_main_clk { |
| 261 | #clock-cells = <0>; | 261 | #clock-cells = <0>; |
| 262 | compatible = "altr,socfpga-gate-clk"; | 262 | compatible = "altr,socfpga-gate-clk"; |
| 263 | clocks = <&mainclk>; | 263 | clocks = <&mainclk>; |
| 264 | clk-gate = <0x60 0>; | 264 | clk-gate = <0x60 0>; |
| 265 | }; | 265 | }; |
| 266 | 266 | ||
| 267 | l3_main_clk: l3_main_clk { | 267 | l3_main_clk: l3_main_clk { |
| 268 | #clock-cells = <0>; | 268 | #clock-cells = <0>; |
| 269 | compatible = "altr,socfpga-gate-clk"; | 269 | compatible = "altr,socfpga-gate-clk"; |
| 270 | clocks = <&mainclk>; | 270 | clocks = <&mainclk>; |
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| 273 | l3_mp_clk: l3_mp_clk { | 273 | l3_mp_clk: l3_mp_clk { |
| 274 | #clock-cells = <0>; | 274 | #clock-cells = <0>; |
| 275 | compatible = "altr,socfpga-gate-clk"; | 275 | compatible = "altr,socfpga-gate-clk"; |
| 276 | clocks = <&mainclk>; | 276 | clocks = <&mainclk>; |
| 277 | div-reg = <0x64 0 2>; | 277 | div-reg = <0x64 0 2>; |
| 278 | clk-gate = <0x60 1>; | 278 | clk-gate = <0x60 1>; |
| 279 | }; | 279 | }; |
| 280 | 280 | ||
| 281 | l3_sp_clk: l3_sp_clk { | 281 | l3_sp_clk: l3_sp_clk { |
| 282 | #clock-cells = <0>; | 282 | #clock-cells = <0>; |
| 283 | compatible = "altr,socfpga-gate-clk"; | 283 | compatible = "altr,socfpga-gate-clk"; |
| 284 | clocks = <&mainclk>; | 284 | clocks = <&mainclk>; |
| 285 | div-reg = <0x64 2 2>; | 285 | div-reg = <0x64 2 2>; |
| 286 | }; | 286 | }; |
| 287 | 287 | ||
| 288 | l4_mp_clk: l4_mp_clk { | 288 | l4_mp_clk: l4_mp_clk { |
| 289 | #clock-cells = <0>; | 289 | #clock-cells = <0>; |
| 290 | compatible = "altr,socfpga-gate-clk"; | 290 | compatible = "altr,socfpga-gate-clk"; |
| 291 | clocks = <&mainclk>, <&per_base_clk>; | 291 | clocks = <&mainclk>, <&per_base_clk>; |
| 292 | div-reg = <0x64 4 3>; | 292 | div-reg = <0x64 4 3>; |
| 293 | clk-gate = <0x60 2>; | 293 | clk-gate = <0x60 2>; |
| 294 | }; | 294 | }; |
| 295 | 295 | ||
| 296 | l4_sp_clk: l4_sp_clk { | 296 | l4_sp_clk: l4_sp_clk { |
| 297 | #clock-cells = <0>; | 297 | #clock-cells = <0>; |
| 298 | compatible = "altr,socfpga-gate-clk"; | 298 | compatible = "altr,socfpga-gate-clk"; |
| 299 | clocks = <&mainclk>, <&per_base_clk>; | 299 | clocks = <&mainclk>, <&per_base_clk>; |
| 300 | div-reg = <0x64 7 3>; | 300 | div-reg = <0x64 7 3>; |
| 301 | clk-gate = <0x60 3>; | 301 | clk-gate = <0x60 3>; |
| 302 | }; | 302 | }; |
| 303 | 303 | ||
| 304 | dbg_at_clk: dbg_at_clk { | 304 | dbg_at_clk: dbg_at_clk { |
| 305 | #clock-cells = <0>; | 305 | #clock-cells = <0>; |
| 306 | compatible = "altr,socfpga-gate-clk"; | 306 | compatible = "altr,socfpga-gate-clk"; |
| 307 | clocks = <&dbg_base_clk>; | 307 | clocks = <&dbg_base_clk>; |
| 308 | div-reg = <0x68 0 2>; | 308 | div-reg = <0x68 0 2>; |
| 309 | clk-gate = <0x60 4>; | 309 | clk-gate = <0x60 4>; |
| 310 | }; | 310 | }; |
| 311 | 311 | ||
| 312 | dbg_clk: dbg_clk { | 312 | dbg_clk: dbg_clk { |
| 313 | #clock-cells = <0>; | 313 | #clock-cells = <0>; |
| 314 | compatible = "altr,socfpga-gate-clk"; | 314 | compatible = "altr,socfpga-gate-clk"; |
| 315 | clocks = <&dbg_base_clk>; | 315 | clocks = <&dbg_base_clk>; |
| 316 | div-reg = <0x68 2 2>; | 316 | div-reg = <0x68 2 2>; |
| 317 | clk-gate = <0x60 5>; | 317 | clk-gate = <0x60 5>; |
| 318 | }; | 318 | }; |
| 319 | 319 | ||
| 320 | dbg_trace_clk: dbg_trace_clk { | 320 | dbg_trace_clk: dbg_trace_clk { |
| 321 | #clock-cells = <0>; | 321 | #clock-cells = <0>; |
| 322 | compatible = "altr,socfpga-gate-clk"; | 322 | compatible = "altr,socfpga-gate-clk"; |
| 323 | clocks = <&dbg_base_clk>; | 323 | clocks = <&dbg_base_clk>; |
| 324 | div-reg = <0x6C 0 3>; | 324 | div-reg = <0x6C 0 3>; |
| 325 | clk-gate = <0x60 6>; | 325 | clk-gate = <0x60 6>; |
| 326 | }; | 326 | }; |
| 327 | 327 | ||
| 328 | dbg_timer_clk: dbg_timer_clk { | 328 | dbg_timer_clk: dbg_timer_clk { |
| 329 | #clock-cells = <0>; | 329 | #clock-cells = <0>; |
| 330 | compatible = "altr,socfpga-gate-clk"; | 330 | compatible = "altr,socfpga-gate-clk"; |
| 331 | clocks = <&dbg_base_clk>; | 331 | clocks = <&dbg_base_clk>; |
| 332 | clk-gate = <0x60 7>; | 332 | clk-gate = <0x60 7>; |
| 333 | }; | 333 | }; |
| 334 | 334 | ||
| 335 | cfg_clk: cfg_clk { | 335 | cfg_clk: cfg_clk { |
| 336 | #clock-cells = <0>; | 336 | #clock-cells = <0>; |
| 337 | compatible = "altr,socfpga-gate-clk"; | 337 | compatible = "altr,socfpga-gate-clk"; |
| 338 | clocks = <&cfg_s2f_usr0_clk>; | 338 | clocks = <&cfg_s2f_usr0_clk>; |
| 339 | clk-gate = <0x60 8>; | 339 | clk-gate = <0x60 8>; |
| 340 | }; | 340 | }; |
| 341 | 341 | ||
| 342 | s2f_user0_clk: s2f_user0_clk { | 342 | s2f_user0_clk: s2f_user0_clk { |
| 343 | #clock-cells = <0>; | 343 | #clock-cells = <0>; |
| 344 | compatible = "altr,socfpga-gate-clk"; | 344 | compatible = "altr,socfpga-gate-clk"; |
| 345 | clocks = <&cfg_s2f_usr0_clk>; | 345 | clocks = <&cfg_s2f_usr0_clk>; |
| 346 | clk-gate = <0x60 9>; | 346 | clk-gate = <0x60 9>; |
| 347 | }; | 347 | }; |
| 348 | 348 | ||
| 349 | emac_0_clk: emac_0_clk { | 349 | emac_0_clk: emac_0_clk { |
| 350 | #clock-cells = <0>; | 350 | #clock-cells = <0>; |
| 351 | compatible = "altr,socfpga-gate-clk"; | 351 | compatible = "altr,socfpga-gate-clk"; |
| 352 | clocks = <&emac0_clk>; | 352 | clocks = <&emac0_clk>; |
| 353 | clk-gate = <0xa0 0>; | 353 | clk-gate = <0xa0 0>; |
| 354 | }; | 354 | }; |
| 355 | 355 | ||
| 356 | emac_1_clk: emac_1_clk { | 356 | emac_1_clk: emac_1_clk { |
| 357 | #clock-cells = <0>; | 357 | #clock-cells = <0>; |
| 358 | compatible = "altr,socfpga-gate-clk"; | 358 | compatible = "altr,socfpga-gate-clk"; |
| 359 | clocks = <&emac1_clk>; | 359 | clocks = <&emac1_clk>; |
| 360 | clk-gate = <0xa0 1>; | 360 | clk-gate = <0xa0 1>; |
| 361 | }; | 361 | }; |
| 362 | 362 | ||
| 363 | usb_mp_clk: usb_mp_clk { | 363 | usb_mp_clk: usb_mp_clk { |
| 364 | #clock-cells = <0>; | 364 | #clock-cells = <0>; |
| 365 | compatible = "altr,socfpga-gate-clk"; | 365 | compatible = "altr,socfpga-gate-clk"; |
| 366 | clocks = <&per_base_clk>; | 366 | clocks = <&per_base_clk>; |
| 367 | clk-gate = <0xa0 2>; | 367 | clk-gate = <0xa0 2>; |
| 368 | div-reg = <0xa4 0 3>; | 368 | div-reg = <0xa4 0 3>; |
| 369 | }; | 369 | }; |
| 370 | 370 | ||
| 371 | spi_m_clk: spi_m_clk { | 371 | spi_m_clk: spi_m_clk { |
| 372 | #clock-cells = <0>; | 372 | #clock-cells = <0>; |
| 373 | compatible = "altr,socfpga-gate-clk"; | 373 | compatible = "altr,socfpga-gate-clk"; |
| 374 | clocks = <&per_base_clk>; | 374 | clocks = <&per_base_clk>; |
| 375 | clk-gate = <0xa0 3>; | 375 | clk-gate = <0xa0 3>; |
| 376 | div-reg = <0xa4 3 3>; | 376 | div-reg = <0xa4 3 3>; |
| 377 | }; | 377 | }; |
| 378 | 378 | ||
| 379 | can0_clk: can0_clk { | 379 | can0_clk: can0_clk { |
| 380 | #clock-cells = <0>; | 380 | #clock-cells = <0>; |
| 381 | compatible = "altr,socfpga-gate-clk"; | 381 | compatible = "altr,socfpga-gate-clk"; |
| 382 | clocks = <&per_base_clk>; | 382 | clocks = <&per_base_clk>; |
| 383 | clk-gate = <0xa0 4>; | 383 | clk-gate = <0xa0 4>; |
| 384 | div-reg = <0xa4 6 3>; | 384 | div-reg = <0xa4 6 3>; |
| 385 | }; | 385 | }; |
| 386 | 386 | ||
| 387 | can1_clk: can1_clk { | 387 | can1_clk: can1_clk { |
| 388 | #clock-cells = <0>; | 388 | #clock-cells = <0>; |
| 389 | compatible = "altr,socfpga-gate-clk"; | 389 | compatible = "altr,socfpga-gate-clk"; |
| 390 | clocks = <&per_base_clk>; | 390 | clocks = <&per_base_clk>; |
| 391 | clk-gate = <0xa0 5>; | 391 | clk-gate = <0xa0 5>; |
| 392 | div-reg = <0xa4 9 3>; | 392 | div-reg = <0xa4 9 3>; |
| 393 | }; | 393 | }; |
| 394 | 394 | ||
| 395 | gpio_db_clk: gpio_db_clk { | 395 | gpio_db_clk: gpio_db_clk { |
| 396 | #clock-cells = <0>; | 396 | #clock-cells = <0>; |
| 397 | compatible = "altr,socfpga-gate-clk"; | 397 | compatible = "altr,socfpga-gate-clk"; |
| 398 | clocks = <&per_base_clk>; | 398 | clocks = <&per_base_clk>; |
| 399 | clk-gate = <0xa0 6>; | 399 | clk-gate = <0xa0 6>; |
| 400 | div-reg = <0xa8 0 24>; | 400 | div-reg = <0xa8 0 24>; |
| 401 | }; | 401 | }; |
| 402 | 402 | ||
| 403 | s2f_user1_clk: s2f_user1_clk { | 403 | s2f_user1_clk: s2f_user1_clk { |
| 404 | #clock-cells = <0>; | 404 | #clock-cells = <0>; |
| 405 | compatible = "altr,socfpga-gate-clk"; | 405 | compatible = "altr,socfpga-gate-clk"; |
| 406 | clocks = <&s2f_usr1_clk>; | 406 | clocks = <&s2f_usr1_clk>; |
| 407 | clk-gate = <0xa0 7>; | 407 | clk-gate = <0xa0 7>; |
| 408 | }; | 408 | }; |
| 409 | 409 | ||
| 410 | sdmmc_clk: sdmmc_clk { | 410 | sdmmc_clk: sdmmc_clk { |
| 411 | #clock-cells = <0>; | 411 | #clock-cells = <0>; |
| 412 | compatible = "altr,socfpga-gate-clk"; | 412 | compatible = "altr,socfpga-gate-clk"; |
| 413 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | 413 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; |
| 414 | clk-gate = <0xa0 8>; | 414 | clk-gate = <0xa0 8>; |
| 415 | }; | 415 | }; |
| 416 | 416 | ||
| 417 | nand_x_clk: nand_x_clk { | 417 | nand_x_clk: nand_x_clk { |
| 418 | #clock-cells = <0>; | 418 | #clock-cells = <0>; |
| 419 | compatible = "altr,socfpga-gate-clk"; | 419 | compatible = "altr,socfpga-gate-clk"; |
| 420 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | 420 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; |
| 421 | clk-gate = <0xa0 9>; | 421 | clk-gate = <0xa0 9>; |
| 422 | }; | 422 | }; |
| 423 | 423 | ||
| 424 | nand_clk: nand_clk { | 424 | nand_clk: nand_clk { |
| 425 | #clock-cells = <0>; | 425 | #clock-cells = <0>; |
| 426 | compatible = "altr,socfpga-gate-clk"; | 426 | compatible = "altr,socfpga-gate-clk"; |
| 427 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | 427 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; |
| 428 | clk-gate = <0xa0 10>; | 428 | clk-gate = <0xa0 10>; |
| 429 | fixed-divider = <4>; | 429 | fixed-divider = <4>; |
| 430 | }; | 430 | }; |
| 431 | 431 | ||
| 432 | qspi_clk: qspi_clk { | 432 | qspi_clk: qspi_clk { |
| 433 | #clock-cells = <0>; | 433 | #clock-cells = <0>; |
| 434 | compatible = "altr,socfpga-gate-clk"; | 434 | compatible = "altr,socfpga-gate-clk"; |
| 435 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | 435 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; |
| 436 | clk-gate = <0xa0 11>; | 436 | clk-gate = <0xa0 11>; |
| 437 | }; | 437 | }; |
| 438 | }; | 438 | }; |
| 439 | }; | 439 | }; |
| @@ -517,9 +517,9 @@ | |||
| 517 | }; | 517 | }; |
| 518 | 518 | ||
| 519 | rstmgr@ffd05000 { | 519 | rstmgr@ffd05000 { |
| 520 | compatible = "altr,rst-mgr"; | 520 | compatible = "altr,rst-mgr"; |
| 521 | reg = <0xffd05000 0x1000>; | 521 | reg = <0xffd05000 0x1000>; |
| 522 | }; | 522 | }; |
| 523 | 523 | ||
| 524 | sysmgr@ffd08000 { | 524 | sysmgr@ffd08000 { |
| 525 | compatible = "altr,sys-mgr"; | 525 | compatible = "altr,sys-mgr"; |