diff options
-rw-r--r-- | drivers/clk/samsung/clk-exynos5420.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 4bc94f1c53d1..1c3674ecc0dc 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #define DIV_CPU1 0x504 | 27 | #define DIV_CPU1 0x504 |
28 | #define GATE_BUS_CPU 0x700 | 28 | #define GATE_BUS_CPU 0x700 |
29 | #define GATE_SCLK_CPU 0x800 | 29 | #define GATE_SCLK_CPU 0x800 |
30 | #define CLKOUT_CMU_CPU 0xa00 | ||
30 | #define GATE_IP_G2D 0x8800 | 31 | #define GATE_IP_G2D 0x8800 |
31 | #define CPLL_LOCK 0x10020 | 32 | #define CPLL_LOCK 0x10020 |
32 | #define DPLL_LOCK 0x10030 | 33 | #define DPLL_LOCK 0x10030 |
@@ -39,7 +40,11 @@ | |||
39 | #define CPLL_CON0 0x10120 | 40 | #define CPLL_CON0 0x10120 |
40 | #define DPLL_CON0 0x10128 | 41 | #define DPLL_CON0 0x10128 |
41 | #define EPLL_CON0 0x10130 | 42 | #define EPLL_CON0 0x10130 |
43 | #define EPLL_CON1 0x10134 | ||
44 | #define EPLL_CON2 0x10138 | ||
42 | #define RPLL_CON0 0x10140 | 45 | #define RPLL_CON0 0x10140 |
46 | #define RPLL_CON1 0x10144 | ||
47 | #define RPLL_CON2 0x10148 | ||
43 | #define IPLL_CON0 0x10150 | 48 | #define IPLL_CON0 0x10150 |
44 | #define SPLL_CON0 0x10160 | 49 | #define SPLL_CON0 0x10160 |
45 | #define VPLL_CON0 0x10170 | 50 | #define VPLL_CON0 0x10170 |
@@ -140,6 +145,13 @@ static unsigned long exynos5420_clk_regs[] __initdata = { | |||
140 | DIV_CPU1, | 145 | DIV_CPU1, |
141 | GATE_BUS_CPU, | 146 | GATE_BUS_CPU, |
142 | GATE_SCLK_CPU, | 147 | GATE_SCLK_CPU, |
148 | CLKOUT_CMU_CPU, | ||
149 | EPLL_CON0, | ||
150 | EPLL_CON1, | ||
151 | EPLL_CON2, | ||
152 | RPLL_CON0, | ||
153 | RPLL_CON1, | ||
154 | RPLL_CON2, | ||
143 | SRC_TOP0, | 155 | SRC_TOP0, |
144 | SRC_TOP1, | 156 | SRC_TOP1, |
145 | SRC_TOP2, | 157 | SRC_TOP2, |