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-rw-r--r--include/sound/rt5677.h21
-rw-r--r--sound/soc/codecs/Kconfig13
-rw-r--r--sound/soc/codecs/Makefile4
-rw-r--r--sound/soc/codecs/rl6231.c152
-rw-r--r--sound/soc/codecs/rl6231.h34
-rw-r--r--sound/soc/codecs/rt5640.c108
-rw-r--r--sound/soc/codecs/rt5640.h8
-rw-r--r--sound/soc/codecs/rt5645.c111
-rw-r--r--sound/soc/codecs/rt5645.h7
-rw-r--r--sound/soc/codecs/rt5651.c107
-rw-r--r--sound/soc/codecs/rt5651.h1
-rw-r--r--sound/soc/codecs/rt5677.c3498
-rw-r--r--sound/soc/codecs/rt5677.h1451
13 files changed, 5208 insertions, 307 deletions
diff --git a/include/sound/rt5677.h b/include/sound/rt5677.h
new file mode 100644
index 000000000000..3da14313bcfc
--- /dev/null
+++ b/include/sound/rt5677.h
@@ -0,0 +1,21 @@
1/*
2 * linux/sound/rt5677.h -- Platform data for RT5677
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __LINUX_SND_RT5677_H
13#define __LINUX_SND_RT5677_H
14
15struct rt5677_platform_data {
16 /* IN1 IN2 can optionally be differential */
17 bool in1_diff;
18 bool in2_diff;
19};
20
21#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index f1ef578229a3..cbfa1e18f651 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -78,6 +78,7 @@ config SND_SOC_ALL_CODECS
78 select SND_SOC_RT5640 if I2C 78 select SND_SOC_RT5640 if I2C
79 select SND_SOC_RT5645 if I2C 79 select SND_SOC_RT5645 if I2C
80 select SND_SOC_RT5651 if I2C 80 select SND_SOC_RT5651 if I2C
81 select SND_SOC_RT5677 if I2C
81 select SND_SOC_SGTL5000 if I2C 82 select SND_SOC_SGTL5000 if I2C
82 select SND_SOC_SI476X if MFD_SI476X_CORE 83 select SND_SOC_SI476X if MFD_SI476X_CORE
83 select SND_SOC_SIRF_AUDIO_CODEC 84 select SND_SOC_SIRF_AUDIO_CODEC
@@ -439,6 +440,15 @@ config SND_SOC_PCM512x_SPI
439 select SND_SOC_PCM512x 440 select SND_SOC_PCM512x
440 select REGMAP_SPI 441 select REGMAP_SPI
441 442
443config SND_SOC_RL6231
444 tristate
445 default y if SND_SOC_RT5640=y
446 default y if SND_SOC_RT5645=y
447 default y if SND_SOC_RT5651=y
448 default m if SND_SOC_RT5640=m
449 default m if SND_SOC_RT5645=m
450 default m if SND_SOC_RT5651=m
451
442config SND_SOC_RT5631 452config SND_SOC_RT5631
443 tristate 453 tristate
444 454
@@ -451,6 +461,9 @@ config SND_SOC_RT5645
451config SND_SOC_RT5651 461config SND_SOC_RT5651
452 tristate 462 tristate
453 463
464config SND_SOC_RT5677
465 tristate
466
454#Freescale sgtl5000 codec 467#Freescale sgtl5000 codec
455config SND_SOC_SGTL5000 468config SND_SOC_SGTL5000
456 tristate "Freescale SGTL5000 CODEC" 469 tristate "Freescale SGTL5000 CODEC"
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index bed0d984c97c..be3377b8d73f 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -67,10 +67,12 @@ snd-soc-pcm3008-objs := pcm3008.o
67snd-soc-pcm512x-objs := pcm512x.o 67snd-soc-pcm512x-objs := pcm512x.o
68snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o 68snd-soc-pcm512x-i2c-objs := pcm512x-i2c.o
69snd-soc-pcm512x-spi-objs := pcm512x-spi.o 69snd-soc-pcm512x-spi-objs := pcm512x-spi.o
70snd-soc-rl6231-objs := rl6231.o
70snd-soc-rt5631-objs := rt5631.o 71snd-soc-rt5631-objs := rt5631.o
71snd-soc-rt5640-objs := rt5640.o 72snd-soc-rt5640-objs := rt5640.o
72snd-soc-rt5645-objs := rt5645.o 73snd-soc-rt5645-objs := rt5645.o
73snd-soc-rt5651-objs := rt5651.o 74snd-soc-rt5651-objs := rt5651.o
75snd-soc-rt5677-objs := rt5677.o
74snd-soc-sgtl5000-objs := sgtl5000.o 76snd-soc-sgtl5000-objs := sgtl5000.o
75snd-soc-alc5623-objs := alc5623.o 77snd-soc-alc5623-objs := alc5623.o
76snd-soc-alc5632-objs := alc5632.o 78snd-soc-alc5632-objs := alc5632.o
@@ -230,10 +232,12 @@ obj-$(CONFIG_SND_SOC_PCM3008) += snd-soc-pcm3008.o
230obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o 232obj-$(CONFIG_SND_SOC_PCM512x) += snd-soc-pcm512x.o
231obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o 233obj-$(CONFIG_SND_SOC_PCM512x_I2C) += snd-soc-pcm512x-i2c.o
232obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o 234obj-$(CONFIG_SND_SOC_PCM512x_SPI) += snd-soc-pcm512x-spi.o
235obj-$(CONFIG_SND_SOC_RL6231) += snd-soc-rl6231.o
233obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o 236obj-$(CONFIG_SND_SOC_RT5631) += snd-soc-rt5631.o
234obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o 237obj-$(CONFIG_SND_SOC_RT5640) += snd-soc-rt5640.o
235obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o 238obj-$(CONFIG_SND_SOC_RT5645) += snd-soc-rt5645.o
236obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o 239obj-$(CONFIG_SND_SOC_RT5651) += snd-soc-rt5651.o
240obj-$(CONFIG_SND_SOC_RT5677) += snd-soc-rt5677.o
237obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o 241obj-$(CONFIG_SND_SOC_SGTL5000) += snd-soc-sgtl5000.o
238obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o 242obj-$(CONFIG_SND_SOC_SIGMADSP) += snd-soc-sigmadsp.o
239obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o 243obj-$(CONFIG_SND_SOC_SI476X) += snd-soc-si476x.o
diff --git a/sound/soc/codecs/rl6231.c b/sound/soc/codecs/rl6231.c
new file mode 100644
index 000000000000..7b82fbe0d14c
--- /dev/null
+++ b/sound/soc/codecs/rl6231.c
@@ -0,0 +1,152 @@
1/*
2 * rl6231.c - RL6231 class device shared support
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 *
6 * Author: Oder Chiou <oder_chiou@realtek.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/regmap.h>
21#include <linux/of.h>
22#include <linux/of_gpio.h>
23#include <linux/platform_device.h>
24#include <linux/spi/spi.h>
25#include <linux/acpi.h>
26#include <sound/core.h>
27#include <sound/pcm.h>
28#include <sound/pcm_params.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33
34#include "rl6231.h"
35
36/**
37 * rl6231_calc_dmic_clk - Calculate the parameter of dmic.
38 *
39 * @rate: base clock rate.
40 *
41 * Choose dmic clock between 1MHz and 3MHz.
42 * It is better for clock to approximate 3MHz.
43 */
44int rl6231_calc_dmic_clk(int rate)
45{
46 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL;
47 int i, red, bound, temp;
48
49 red = 3000000 * 12;
50 for (i = 0; i < ARRAY_SIZE(div); i++) {
51 bound = div[i] * 3000000;
52 if (rate > bound)
53 continue;
54 temp = bound - rate;
55 if (temp < red) {
56 red = temp;
57 idx = i;
58 }
59 }
60
61 return idx;
62}
63EXPORT_SYMBOL_GPL(rl6231_calc_dmic_clk);
64
65/**
66 * rl6231_pll_calc - Calcualte PLL M/N/K code.
67 * @freq_in: external clock provided to codec.
68 * @freq_out: target clock which codec works on.
69 * @pll_code: Pointer to structure with M, N, K and bypass flag.
70 *
71 * Calcualte M/N/K code to configure PLL for codec.
72 *
73 * Returns 0 for success or negative error code.
74 */
75int rl6231_pll_calc(const unsigned int freq_in,
76 const unsigned int freq_out, struct rl6231_pll_code *pll_code)
77{
78 int max_n = RL6231_PLL_N_MAX, max_m = RL6231_PLL_M_MAX;
79 int k, red, n_t, pll_out, in_t, out_t;
80 int n = 0, m = 0, m_t = 0;
81 int red_t = abs(freq_out - freq_in);
82 bool bypass = false;
83
84 if (RL6231_PLL_INP_MAX < freq_in || RL6231_PLL_INP_MIN > freq_in)
85 return -EINVAL;
86
87 k = 100000000 / freq_out - 2;
88 if (k > RL6231_PLL_K_MAX)
89 k = RL6231_PLL_K_MAX;
90 for (n_t = 0; n_t <= max_n; n_t++) {
91 in_t = freq_in / (k + 2);
92 pll_out = freq_out / (n_t + 2);
93 if (in_t < 0)
94 continue;
95 if (in_t == pll_out) {
96 bypass = true;
97 n = n_t;
98 goto code_find;
99 }
100 red = abs(in_t - pll_out);
101 if (red < red_t) {
102 bypass = true;
103 n = n_t;
104 m = m_t;
105 if (red == 0)
106 goto code_find;
107 red_t = red;
108 }
109 for (m_t = 0; m_t <= max_m; m_t++) {
110 out_t = in_t / (m_t + 2);
111 red = abs(out_t - pll_out);
112 if (red < red_t) {
113 bypass = false;
114 n = n_t;
115 m = m_t;
116 if (red == 0)
117 goto code_find;
118 red_t = red;
119 }
120 }
121 }
122 pr_debug("Only get approximation about PLL\n");
123
124code_find:
125
126 pll_code->m_bp = bypass;
127 pll_code->m_code = m;
128 pll_code->n_code = n;
129 pll_code->k_code = k;
130 return 0;
131}
132EXPORT_SYMBOL_GPL(rl6231_pll_calc);
133
134int rl6231_get_clk_info(int sclk, int rate)
135{
136 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
137
138 if (sclk <= 0 || rate <= 0)
139 return -EINVAL;
140
141 rate = rate << 8;
142 for (i = 0; i < ARRAY_SIZE(pd); i++)
143 if (sclk == rate * pd[i])
144 return i;
145
146 return -EINVAL;
147}
148EXPORT_SYMBOL_GPL(rl6231_get_clk_info);
149
150MODULE_DESCRIPTION("RL6231 class device shared support");
151MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
152MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rl6231.h b/sound/soc/codecs/rl6231.h
new file mode 100644
index 000000000000..0f7b057ed736
--- /dev/null
+++ b/sound/soc/codecs/rl6231.h
@@ -0,0 +1,34 @@
1/*
2 * rl6231.h - RL6231 class device shared support
3 *
4 * Copyright 2014 Realtek Semiconductor Corp.
5 *
6 * Author: Oder Chiou <oder_chiou@realtek.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __RL6231_H__
14#define __RL6231_H__
15
16#define RL6231_PLL_INP_MAX 40000000
17#define RL6231_PLL_INP_MIN 256000
18#define RL6231_PLL_N_MAX 0x1ff
19#define RL6231_PLL_K_MAX 0x1f
20#define RL6231_PLL_M_MAX 0xf
21
22struct rl6231_pll_code {
23 bool m_bp; /* Indicates bypass m code or not. */
24 int m_code;
25 int n_code;
26 int k_code;
27};
28
29int rl6231_calc_dmic_clk(int rate);
30int rl6231_pll_calc(const unsigned int freq_in,
31 const unsigned int freq_out, struct rl6231_pll_code *pll_code);
32int rl6231_get_clk_info(int sclk, int rate);
33
34#endif /* __RL6231_H__ */
diff --git a/sound/soc/codecs/rt5640.c b/sound/soc/codecs/rt5640.c
index 9e0d48f98927..de80e89b5fd8 100644
--- a/sound/soc/codecs/rt5640.c
+++ b/sound/soc/codecs/rt5640.c
@@ -31,6 +31,7 @@
31#include <sound/initval.h> 31#include <sound/initval.h>
32#include <sound/tlv.h> 32#include <sound/tlv.h>
33 33
34#include "rl6231.h"
34#include "rt5640.h" 35#include "rt5640.h"
35 36
36#define RT5640_DEVICE_ID 0x6231 37#define RT5640_DEVICE_ID 0x6231
@@ -453,30 +454,16 @@ static const struct snd_kcontrol_new rt5640_specific_snd_controls[] = {
453 * @kcontrol: The kcontrol of this widget. 454 * @kcontrol: The kcontrol of this widget.
454 * @event: Event id. 455 * @event: Event id.
455 * 456 *
456 * Choose dmic clock between 1MHz and 3MHz.
457 * It is better for clock to approximate 3MHz.
458 */ 457 */
459static int set_dmic_clk(struct snd_soc_dapm_widget *w, 458static int set_dmic_clk(struct snd_soc_dapm_widget *w,
460 struct snd_kcontrol *kcontrol, int event) 459 struct snd_kcontrol *kcontrol, int event)
461{ 460{
462 struct snd_soc_codec *codec = w->codec; 461 struct snd_soc_codec *codec = w->codec;
463 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec); 462 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
464 int div[] = {2, 3, 4, 6, 8, 12}; 463 int idx = -EINVAL;
465 int idx = -EINVAL, i; 464
466 int rate, red, bound, temp; 465 idx = rl6231_calc_dmic_clk(rt5640->sysclk);
467 466
468 rate = rt5640->sysclk;
469 red = 3000000 * 12;
470 for (i = 0; i < ARRAY_SIZE(div); i++) {
471 bound = div[i] * 3000000;
472 if (rate > bound)
473 continue;
474 temp = bound - rate;
475 if (temp < red) {
476 red = temp;
477 idx = i;
478 }
479 }
480 if (idx < 0) 467 if (idx < 0)
481 dev_err(codec->dev, "Failed to set DMIC clock\n"); 468 dev_err(codec->dev, "Failed to set DMIC clock\n");
482 else 469 else
@@ -1639,21 +1626,6 @@ static int get_sdp_info(struct snd_soc_codec *codec, int dai_id)
1639 return ret; 1626 return ret;
1640} 1627}
1641 1628
1642static int get_clk_info(int sclk, int rate)
1643{
1644 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1645
1646 if (sclk <= 0 || rate <= 0)
1647 return -EINVAL;
1648
1649 rate = rate << 8;
1650 for (i = 0; i < ARRAY_SIZE(pd); i++)
1651 if (sclk == rate * pd[i])
1652 return i;
1653
1654 return -EINVAL;
1655}
1656
1657static int rt5640_hw_params(struct snd_pcm_substream *substream, 1629static int rt5640_hw_params(struct snd_pcm_substream *substream,
1658 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1630 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1659{ 1631{
@@ -1663,7 +1635,7 @@ static int rt5640_hw_params(struct snd_pcm_substream *substream,
1663 int dai_sel, pre_div, bclk_ms, frame_size; 1635 int dai_sel, pre_div, bclk_ms, frame_size;
1664 1636
1665 rt5640->lrck[dai->id] = params_rate(params); 1637 rt5640->lrck[dai->id] = params_rate(params);
1666 pre_div = get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]); 1638 pre_div = rl6231_get_clk_info(rt5640->sysclk, rt5640->lrck[dai->id]);
1667 if (pre_div < 0) { 1639 if (pre_div < 0) {
1668 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n", 1640 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
1669 rt5640->lrck[dai->id], dai->id); 1641 rt5640->lrck[dai->id], dai->id);
@@ -1820,65 +1792,12 @@ static int rt5640_set_dai_sysclk(struct snd_soc_dai *dai,
1820 return 0; 1792 return 0;
1821} 1793}
1822 1794
1823/**
1824 * rt5640_pll_calc - Calculate PLL M/N/K code.
1825 * @freq_in: external clock provided to codec.
1826 * @freq_out: target clock which codec works on.
1827 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1828 *
1829 * Calculate M/N/K code to configure PLL for codec. And K is assigned to 2
1830 * which make calculation more efficiently.
1831 *
1832 * Returns 0 for success or negative error code.
1833 */
1834static int rt5640_pll_calc(const unsigned int freq_in,
1835 const unsigned int freq_out, struct rt5640_pll_code *pll_code)
1836{
1837 int max_n = RT5640_PLL_N_MAX, max_m = RT5640_PLL_M_MAX;
1838 int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
1839 int red_t = abs(freq_out - freq_in);
1840 bool bypass = false;
1841
1842 if (RT5640_PLL_INP_MAX < freq_in || RT5640_PLL_INP_MIN > freq_in)
1843 return -EINVAL;
1844
1845 for (n_t = 0; n_t <= max_n; n_t++) {
1846 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
1847 if (in_t < 0)
1848 continue;
1849 if (in_t == freq_out) {
1850 bypass = true;
1851 n = n_t;
1852 goto code_find;
1853 }
1854 for (m_t = 0; m_t <= max_m; m_t++) {
1855 out_t = in_t / (m_t + 2);
1856 red = abs(out_t - freq_out);
1857 if (red < red_t) {
1858 n = n_t;
1859 m = m_t;
1860 if (red == 0)
1861 goto code_find;
1862 red_t = red;
1863 }
1864 }
1865 }
1866 pr_debug("Only get approximation about PLL\n");
1867
1868code_find:
1869 pll_code->m_bp = bypass;
1870 pll_code->m_code = m;
1871 pll_code->n_code = n;
1872 pll_code->k_code = 2;
1873 return 0;
1874}
1875
1876static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 1795static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1877 unsigned int freq_in, unsigned int freq_out) 1796 unsigned int freq_in, unsigned int freq_out)
1878{ 1797{
1879 struct snd_soc_codec *codec = dai->codec; 1798 struct snd_soc_codec *codec = dai->codec;
1880 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec); 1799 struct rt5640_priv *rt5640 = snd_soc_codec_get_drvdata(codec);
1881 struct rt5640_pll_code *pll_code = &rt5640->pll_code; 1800 struct rl6231_pll_code pll_code;
1882 int ret, dai_sel; 1801 int ret, dai_sel;
1883 1802
1884 if (source == rt5640->pll_src && freq_in == rt5640->pll_in && 1803 if (source == rt5640->pll_src && freq_in == rt5640->pll_in &&
@@ -1922,20 +1841,21 @@ static int rt5640_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1922 return -EINVAL; 1841 return -EINVAL;
1923 } 1842 }
1924 1843
1925 ret = rt5640_pll_calc(freq_in, freq_out, pll_code); 1844 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1926 if (ret < 0) { 1845 if (ret < 0) {
1927 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 1846 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1928 return ret; 1847 return ret;
1929 } 1848 }
1930 1849
1931 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp, 1850 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
1932 (pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code); 1851 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1852 pll_code.n_code, pll_code.k_code);
1933 1853
1934 snd_soc_write(codec, RT5640_PLL_CTRL1, 1854 snd_soc_write(codec, RT5640_PLL_CTRL1,
1935 pll_code->n_code << RT5640_PLL_N_SFT | pll_code->k_code); 1855 pll_code.n_code << RT5640_PLL_N_SFT | pll_code.k_code);
1936 snd_soc_write(codec, RT5640_PLL_CTRL2, 1856 snd_soc_write(codec, RT5640_PLL_CTRL2,
1937 (pll_code->m_bp ? 0 : pll_code->m_code) << RT5640_PLL_M_SFT | 1857 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5640_PLL_M_SFT |
1938 pll_code->m_bp << RT5640_PLL_M_BP_SFT); 1858 pll_code.m_bp << RT5640_PLL_M_BP_SFT);
1939 1859
1940 rt5640->pll_in = freq_in; 1860 rt5640->pll_in = freq_in;
1941 rt5640->pll_out = freq_out; 1861 rt5640->pll_out = freq_out;
diff --git a/sound/soc/codecs/rt5640.h b/sound/soc/codecs/rt5640.h
index 895ca149db2e..58ebe96b86da 100644
--- a/sound/soc/codecs/rt5640.h
+++ b/sound/soc/codecs/rt5640.h
@@ -2079,13 +2079,6 @@ enum {
2079 RT5640_DMIC2, 2079 RT5640_DMIC2,
2080}; 2080};
2081 2081
2082struct rt5640_pll_code {
2083 bool m_bp; /* Indicates bypass m code or not. */
2084 int m_code;
2085 int n_code;
2086 int k_code;
2087};
2088
2089struct rt5640_priv { 2082struct rt5640_priv {
2090 struct snd_soc_codec *codec; 2083 struct snd_soc_codec *codec;
2091 struct rt5640_platform_data pdata; 2084 struct rt5640_platform_data pdata;
@@ -2097,7 +2090,6 @@ struct rt5640_priv {
2097 int bclk[RT5640_AIFS]; 2090 int bclk[RT5640_AIFS];
2098 int master[RT5640_AIFS]; 2091 int master[RT5640_AIFS];
2099 2092
2100 struct rt5640_pll_code pll_code;
2101 int pll_src; 2093 int pll_src;
2102 int pll_in; 2094 int pll_in;
2103 int pll_out; 2095 int pll_out;
diff --git a/sound/soc/codecs/rt5645.c b/sound/soc/codecs/rt5645.c
index ab97d722e15d..02147be2b302 100644
--- a/sound/soc/codecs/rt5645.c
+++ b/sound/soc/codecs/rt5645.c
@@ -26,6 +26,7 @@
26#include <sound/initval.h> 26#include <sound/initval.h>
27#include <sound/tlv.h> 27#include <sound/tlv.h>
28 28
29#include "rl6231.h"
29#include "rt5645.h" 30#include "rt5645.h"
30 31
31#define RT5645_DEVICE_ID 0x6308 32#define RT5645_DEVICE_ID 0x6308
@@ -519,30 +520,15 @@ static const struct snd_kcontrol_new rt5645_snd_controls[] = {
519 * @kcontrol: The kcontrol of this widget. 520 * @kcontrol: The kcontrol of this widget.
520 * @event: Event id. 521 * @event: Event id.
521 * 522 *
522 * Choose dmic clock between 1MHz and 3MHz.
523 * It is better for clock to approximate 3MHz.
524 */ 523 */
525static int set_dmic_clk(struct snd_soc_dapm_widget *w, 524static int set_dmic_clk(struct snd_soc_dapm_widget *w,
526 struct snd_kcontrol *kcontrol, int event) 525 struct snd_kcontrol *kcontrol, int event)
527{ 526{
528 struct snd_soc_codec *codec = w->codec; 527 struct snd_soc_codec *codec = w->codec;
529 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 528 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
530 int div[] = {2, 3, 4, 6, 8, 12}; 529 int idx = -EINVAL;
531 int idx = -EINVAL, i; 530
532 int rate, red, bound, temp; 531 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
533
534 rate = rt5645->sysclk;
535 red = 3000000 * 12;
536 for (i = 0; i < ARRAY_SIZE(div); i++) {
537 bound = div[i] * 3000000;
538 if (rate > bound)
539 continue;
540 temp = bound - rate;
541 if (temp < red) {
542 red = temp;
543 idx = i;
544 }
545 }
546 532
547 if (idx < 0) 533 if (idx < 0)
548 dev_err(codec->dev, "Failed to set DMIC clock\n"); 534 dev_err(codec->dev, "Failed to set DMIC clock\n");
@@ -1800,21 +1786,6 @@ static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
1800 { "SPOR", NULL, "SPK amp" }, 1786 { "SPOR", NULL, "SPK amp" },
1801}; 1787};
1802 1788
1803static int get_clk_info(int sclk, int rate)
1804{
1805 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1806
1807 if (sclk <= 0 || rate <= 0)
1808 return -EINVAL;
1809
1810 rate = rate << 8;
1811 for (i = 0; i < ARRAY_SIZE(pd); i++)
1812 if (sclk == rate * pd[i])
1813 return i;
1814
1815 return -EINVAL;
1816}
1817
1818static int rt5645_hw_params(struct snd_pcm_substream *substream, 1789static int rt5645_hw_params(struct snd_pcm_substream *substream,
1819 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1790 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1820{ 1791{
@@ -1824,7 +1795,7 @@ static int rt5645_hw_params(struct snd_pcm_substream *substream,
1824 int pre_div, bclk_ms, frame_size; 1795 int pre_div, bclk_ms, frame_size;
1825 1796
1826 rt5645->lrck[dai->id] = params_rate(params); 1797 rt5645->lrck[dai->id] = params_rate(params);
1827 pre_div = get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]); 1798 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
1828 if (pre_div < 0) { 1799 if (pre_div < 0) {
1829 dev_err(codec->dev, "Unsupported clock setting\n"); 1800 dev_err(codec->dev, "Unsupported clock setting\n");
1830 return -EINVAL; 1801 return -EINVAL;
@@ -1978,80 +1949,12 @@ static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
1978 return 0; 1949 return 0;
1979} 1950}
1980 1951
1981/**
1982 * rt5645_pll_calc - Calcualte PLL M/N/K code.
1983 * @freq_in: external clock provided to codec.
1984 * @freq_out: target clock which codec works on.
1985 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1986 *
1987 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1988 * which make calculation more efficiently.
1989 *
1990 * Returns 0 for success or negative error code.
1991 */
1992static int rt5645_pll_calc(const unsigned int freq_in,
1993 const unsigned int freq_out, struct rt5645_pll_code *pll_code)
1994{
1995 int max_n = RT5645_PLL_N_MAX, max_m = RT5645_PLL_M_MAX;
1996 int k, n = 0, m = 0, red, n_t, m_t, pll_out, in_t, out_t;
1997 int red_t = abs(freq_out - freq_in);
1998 bool bypass = false;
1999
2000 if (RT5645_PLL_INP_MAX < freq_in || RT5645_PLL_INP_MIN > freq_in)
2001 return -EINVAL;
2002
2003 k = 100000000 / freq_out - 2;
2004 if (k > RT5645_PLL_K_MAX)
2005 k = RT5645_PLL_K_MAX;
2006 for (n_t = 0; n_t <= max_n; n_t++) {
2007 in_t = freq_in / (k + 2);
2008 pll_out = freq_out / (n_t + 2);
2009 if (in_t < 0)
2010 continue;
2011 if (in_t == pll_out) {
2012 bypass = true;
2013 n = n_t;
2014 goto code_find;
2015 }
2016 red = abs(in_t - pll_out);
2017 if (red < red_t) {
2018 bypass = true;
2019 n = n_t;
2020 m = m_t;
2021 if (red == 0)
2022 goto code_find;
2023 red_t = red;
2024 }
2025 for (m_t = 0; m_t <= max_m; m_t++) {
2026 out_t = in_t / (m_t + 2);
2027 red = abs(out_t - pll_out);
2028 if (red < red_t) {
2029 bypass = false;
2030 n = n_t;
2031 m = m_t;
2032 if (red == 0)
2033 goto code_find;
2034 red_t = red;
2035 }
2036 }
2037 }
2038 pr_debug("Only get approximation about PLL\n");
2039
2040code_find:
2041
2042 pll_code->m_bp = bypass;
2043 pll_code->m_code = m;
2044 pll_code->n_code = n;
2045 pll_code->k_code = k;
2046 return 0;
2047}
2048
2049static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 1952static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2050 unsigned int freq_in, unsigned int freq_out) 1953 unsigned int freq_in, unsigned int freq_out)
2051{ 1954{
2052 struct snd_soc_codec *codec = dai->codec; 1955 struct snd_soc_codec *codec = dai->codec;
2053 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec); 1956 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2054 struct rt5645_pll_code pll_code; 1957 struct rl6231_pll_code pll_code;
2055 int ret; 1958 int ret;
2056 1959
2057 if (source == rt5645->pll_src && freq_in == rt5645->pll_in && 1960 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
@@ -2094,7 +1997,7 @@ static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2094 return -EINVAL; 1997 return -EINVAL;
2095 } 1998 }
2096 1999
2097 ret = rt5645_pll_calc(freq_in, freq_out, &pll_code); 2000 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2098 if (ret < 0) { 2001 if (ret < 0) {
2099 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 2002 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2100 return ret; 2003 return ret;
diff --git a/sound/soc/codecs/rt5645.h b/sound/soc/codecs/rt5645.h
index 345aa3f5d14f..355b7e9eefab 100644
--- a/sound/soc/codecs/rt5645.h
+++ b/sound/soc/codecs/rt5645.h
@@ -2162,13 +2162,6 @@ enum {
2162 RT5645_DMIC_DATA_GPIO11, 2162 RT5645_DMIC_DATA_GPIO11,
2163}; 2163};
2164 2164
2165struct rt5645_pll_code {
2166 bool m_bp; /* Indicates bypass m code or not. */
2167 int m_code;
2168 int n_code;
2169 int k_code;
2170};
2171
2172struct rt5645_priv { 2165struct rt5645_priv {
2173 struct snd_soc_codec *codec; 2166 struct snd_soc_codec *codec;
2174 struct rt5645_platform_data pdata; 2167 struct rt5645_platform_data pdata;
diff --git a/sound/soc/codecs/rt5651.c b/sound/soc/codecs/rt5651.c
index 9c88d89f41f0..ea4b1c652a26 100644
--- a/sound/soc/codecs/rt5651.c
+++ b/sound/soc/codecs/rt5651.c
@@ -26,6 +26,7 @@
26#include <sound/initval.h> 26#include <sound/initval.h>
27#include <sound/tlv.h> 27#include <sound/tlv.h>
28 28
29#include "rl6231.h"
29#include "rt5651.h" 30#include "rt5651.h"
30 31
31#define RT5651_DEVICE_ID_VALUE 0x6281 32#define RT5651_DEVICE_ID_VALUE 0x6281
@@ -371,29 +372,16 @@ static const struct snd_kcontrol_new rt5651_snd_controls[] = {
371 * @kcontrol: The kcontrol of this widget. 372 * @kcontrol: The kcontrol of this widget.
372 * @event: Event id. 373 * @event: Event id.
373 * 374 *
374 * Choose dmic clock between 1MHz and 3MHz.
375 * It is better for clock to approximate 3MHz.
376 */ 375 */
377static int set_dmic_clk(struct snd_soc_dapm_widget *w, 376static int set_dmic_clk(struct snd_soc_dapm_widget *w,
378 struct snd_kcontrol *kcontrol, int event) 377 struct snd_kcontrol *kcontrol, int event)
379{ 378{
380 struct snd_soc_codec *codec = w->codec; 379 struct snd_soc_codec *codec = w->codec;
381 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 380 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
382 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL; 381 int idx = -EINVAL;
383 int i, rate, red, bound, temp; 382
384 383 idx = rl6231_calc_dmic_clk(rt5651->sysclk);
385 rate = rt5651->sysclk; 384
386 red = 3000000 * 12;
387 for (i = 0; i < ARRAY_SIZE(div); i++) {
388 bound = div[i] * 3000000;
389 if (rate > bound)
390 continue;
391 temp = bound - rate;
392 if (temp < red) {
393 red = temp;
394 idx = i;
395 }
396 }
397 if (idx < 0) 385 if (idx < 0)
398 dev_err(codec->dev, "Failed to set DMIC clock\n"); 386 dev_err(codec->dev, "Failed to set DMIC clock\n");
399 else 387 else
@@ -1350,21 +1338,6 @@ static const struct snd_soc_dapm_route rt5651_dapm_routes[] = {
1350 {"PDMR", NULL, "PDM R Mux"}, 1338 {"PDMR", NULL, "PDM R Mux"},
1351}; 1339};
1352 1340
1353static int get_clk_info(int sclk, int rate)
1354{
1355 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1356
1357 if (sclk <= 0 || rate <= 0)
1358 return -EINVAL;
1359
1360 rate = rate << 8;
1361 for (i = 0; i < ARRAY_SIZE(pd); i++)
1362 if (sclk == rate * pd[i])
1363 return i;
1364
1365 return -EINVAL;
1366}
1367
1368static int rt5651_hw_params(struct snd_pcm_substream *substream, 1341static int rt5651_hw_params(struct snd_pcm_substream *substream,
1369 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) 1342 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1370{ 1343{
@@ -1374,7 +1347,7 @@ static int rt5651_hw_params(struct snd_pcm_substream *substream,
1374 int pre_div, bclk_ms, frame_size; 1347 int pre_div, bclk_ms, frame_size;
1375 1348
1376 rt5651->lrck[dai->id] = params_rate(params); 1349 rt5651->lrck[dai->id] = params_rate(params);
1377 pre_div = get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]); 1350 pre_div = rl6231_get_clk_info(rt5651->sysclk, rt5651->lrck[dai->id]);
1378 1351
1379 if (pre_div < 0) { 1352 if (pre_div < 0) {
1380 dev_err(codec->dev, "Unsupported clock setting\n"); 1353 dev_err(codec->dev, "Unsupported clock setting\n");
@@ -1528,65 +1501,12 @@ static int rt5651_set_dai_sysclk(struct snd_soc_dai *dai,
1528 return 0; 1501 return 0;
1529} 1502}
1530 1503
1531/**
1532 * rt5651_pll_calc - Calcualte PLL M/N/K code.
1533 * @freq_in: external clock provided to codec.
1534 * @freq_out: target clock which codec works on.
1535 * @pll_code: Pointer to structure with M, N, K and bypass flag.
1536 *
1537 * Calcualte M/N/K code to configure PLL for codec. And K is assigned to 2
1538 * which make calculation more efficiently.
1539 *
1540 * Returns 0 for success or negative error code.
1541 */
1542static int rt5651_pll_calc(const unsigned int freq_in,
1543 const unsigned int freq_out, struct rt5651_pll_code *pll_code)
1544{
1545 int max_n = RT5651_PLL_N_MAX, max_m = RT5651_PLL_M_MAX;
1546 int n = 0, m = 0, red, n_t, m_t, in_t, out_t;
1547 int red_t = abs(freq_out - freq_in);
1548 bool bypass = false;
1549
1550 if (RT5651_PLL_INP_MAX < freq_in || RT5651_PLL_INP_MIN > freq_in)
1551 return -EINVAL;
1552
1553 for (n_t = 0; n_t <= max_n; n_t++) {
1554 in_t = (freq_in >> 1) + (freq_in >> 2) * n_t;
1555 if (in_t < 0)
1556 continue;
1557 if (in_t == freq_out) {
1558 bypass = true;
1559 n = n_t;
1560 goto code_find;
1561 }
1562 for (m_t = 0; m_t <= max_m; m_t++) {
1563 out_t = in_t / (m_t + 2);
1564 red = abs(out_t - freq_out);
1565 if (red < red_t) {
1566 n = n_t;
1567 m = m_t;
1568 if (red == 0)
1569 goto code_find;
1570 red_t = red;
1571 }
1572 }
1573 }
1574 pr_debug("Only get approximation about PLL\n");
1575
1576code_find:
1577 pll_code->m_bp = bypass;
1578 pll_code->m_code = m;
1579 pll_code->n_code = n;
1580 pll_code->k_code = 2;
1581 return 0;
1582}
1583
1584static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source, 1504static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1585 unsigned int freq_in, unsigned int freq_out) 1505 unsigned int freq_in, unsigned int freq_out)
1586{ 1506{
1587 struct snd_soc_codec *codec = dai->codec; 1507 struct snd_soc_codec *codec = dai->codec;
1588 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec); 1508 struct rt5651_priv *rt5651 = snd_soc_codec_get_drvdata(codec);
1589 struct rt5651_pll_code *pll_code = &rt5651->pll_code; 1509 struct rl6231_pll_code pll_code;
1590 int ret; 1510 int ret;
1591 1511
1592 if (source == rt5651->pll_src && freq_in == rt5651->pll_in && 1512 if (source == rt5651->pll_src && freq_in == rt5651->pll_in &&
@@ -1621,20 +1541,21 @@ static int rt5651_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
1621 return -EINVAL; 1541 return -EINVAL;
1622 } 1542 }
1623 1543
1624 ret = rt5651_pll_calc(freq_in, freq_out, pll_code); 1544 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1625 if (ret < 0) { 1545 if (ret < 0) {
1626 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in); 1546 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
1627 return ret; 1547 return ret;
1628 } 1548 }
1629 1549
1630 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=2\n", pll_code->m_bp, 1550 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
1631 (pll_code->m_bp ? 0 : pll_code->m_code), pll_code->n_code); 1551 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1552 pll_code.n_code, pll_code.k_code);
1632 1553
1633 snd_soc_write(codec, RT5651_PLL_CTRL1, 1554 snd_soc_write(codec, RT5651_PLL_CTRL1,
1634 pll_code->n_code << RT5651_PLL_N_SFT | pll_code->k_code); 1555 pll_code.n_code << RT5651_PLL_N_SFT | pll_code.k_code);
1635 snd_soc_write(codec, RT5651_PLL_CTRL2, 1556 snd_soc_write(codec, RT5651_PLL_CTRL2,
1636 (pll_code->m_bp ? 0 : pll_code->m_code) << RT5651_PLL_M_SFT | 1557 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5651_PLL_M_SFT |
1637 pll_code->m_bp << RT5651_PLL_M_BP_SFT); 1558 pll_code.m_bp << RT5651_PLL_M_BP_SFT);
1638 1559
1639 rt5651->pll_in = freq_in; 1560 rt5651->pll_in = freq_in;
1640 rt5651->pll_out = freq_out; 1561 rt5651->pll_out = freq_out;
diff --git a/sound/soc/codecs/rt5651.h b/sound/soc/codecs/rt5651.h
index a28bd0c3d613..1bd33cfa6411 100644
--- a/sound/soc/codecs/rt5651.h
+++ b/sound/soc/codecs/rt5651.h
@@ -2069,7 +2069,6 @@ struct rt5651_priv {
2069 int bclk[RT5651_AIFS]; 2069 int bclk[RT5651_AIFS];
2070 int master[RT5651_AIFS]; 2070 int master[RT5651_AIFS];
2071 2071
2072 struct rt5651_pll_code pll_code;
2073 int pll_src; 2072 int pll_src;
2074 int pll_in; 2073 int pll_in;
2075 int pll_out; 2074 int pll_out;
diff --git a/sound/soc/codecs/rt5677.c b/sound/soc/codecs/rt5677.c
new file mode 100644
index 000000000000..833231e27340
--- /dev/null
+++ b/sound/soc/codecs/rt5677.c
@@ -0,0 +1,3498 @@
1/*
2 * rt5677.c -- RT5677 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/fs.h>
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/i2c.h>
20#include <linux/platform_device.h>
21#include <linux/spi/spi.h>
22#include <sound/core.h>
23#include <sound/pcm.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
30#include "rt5677.h"
31
32#define RT5677_DEVICE_ID 0x6327
33
34#define RT5677_PR_RANGE_BASE (0xff + 1)
35#define RT5677_PR_SPACING 0x100
36
37#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))
38
39static const struct regmap_range_cfg rt5677_ranges[] = {
40 {
41 .name = "PR",
42 .range_min = RT5677_PR_BASE,
43 .range_max = RT5677_PR_BASE + 0xfd,
44 .selector_reg = RT5677_PRIV_INDEX,
45 .selector_mask = 0xff,
46 .selector_shift = 0x0,
47 .window_start = RT5677_PRIV_DATA,
48 .window_len = 0x1,
49 },
50};
51
52static const struct reg_default init_list[] = {
53 {RT5677_PR_BASE + 0x3d, 0x364d},
54 {RT5677_PR_BASE + 0x17, 0x4fc0},
55 {RT5677_PR_BASE + 0x13, 0x0312},
56 {RT5677_PR_BASE + 0x1e, 0x0000},
57 {RT5677_PR_BASE + 0x12, 0x0eaa},
58 {RT5677_PR_BASE + 0x14, 0x018a},
59};
60#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)
61
62static const struct reg_default rt5677_reg[] = {
63 {RT5677_RESET , 0x0000},
64 {RT5677_LOUT1 , 0xa800},
65 {RT5677_IN1 , 0x0000},
66 {RT5677_MICBIAS , 0x0000},
67 {RT5677_SLIMBUS_PARAM , 0x0000},
68 {RT5677_SLIMBUS_RX , 0x0000},
69 {RT5677_SLIMBUS_CTRL , 0x0000},
70 {RT5677_SIDETONE_CTRL , 0x000b},
71 {RT5677_ANA_DAC1_2_3_SRC , 0x0000},
72 {RT5677_IF_DSP_DAC3_4_MIXER , 0x1111},
73 {RT5677_DAC4_DIG_VOL , 0xafaf},
74 {RT5677_DAC3_DIG_VOL , 0xafaf},
75 {RT5677_DAC1_DIG_VOL , 0xafaf},
76 {RT5677_DAC2_DIG_VOL , 0xafaf},
77 {RT5677_IF_DSP_DAC2_MIXER , 0x0011},
78 {RT5677_STO1_ADC_DIG_VOL , 0x2f2f},
79 {RT5677_MONO_ADC_DIG_VOL , 0x2f2f},
80 {RT5677_STO1_2_ADC_BST , 0x0000},
81 {RT5677_STO2_ADC_DIG_VOL , 0x2f2f},
82 {RT5677_ADC_BST_CTRL2 , 0x0000},
83 {RT5677_STO3_4_ADC_BST , 0x0000},
84 {RT5677_STO3_ADC_DIG_VOL , 0x2f2f},
85 {RT5677_STO4_ADC_DIG_VOL , 0x2f2f},
86 {RT5677_STO4_ADC_MIXER , 0xd4c0},
87 {RT5677_STO3_ADC_MIXER , 0xd4c0},
88 {RT5677_STO2_ADC_MIXER , 0xd4c0},
89 {RT5677_STO1_ADC_MIXER , 0xd4c0},
90 {RT5677_MONO_ADC_MIXER , 0xd4d1},
91 {RT5677_ADC_IF_DSP_DAC1_MIXER , 0x8080},
92 {RT5677_STO1_DAC_MIXER , 0xaaaa},
93 {RT5677_MONO_DAC_MIXER , 0xaaaa},
94 {RT5677_DD1_MIXER , 0xaaaa},
95 {RT5677_DD2_MIXER , 0xaaaa},
96 {RT5677_IF3_DATA , 0x0000},
97 {RT5677_IF4_DATA , 0x0000},
98 {RT5677_PDM_OUT_CTRL , 0x8888},
99 {RT5677_PDM_DATA_CTRL1 , 0x0000},
100 {RT5677_PDM_DATA_CTRL2 , 0x0000},
101 {RT5677_PDM1_DATA_CTRL2 , 0x0000},
102 {RT5677_PDM1_DATA_CTRL3 , 0x0000},
103 {RT5677_PDM1_DATA_CTRL4 , 0x0000},
104 {RT5677_PDM2_DATA_CTRL2 , 0x0000},
105 {RT5677_PDM2_DATA_CTRL3 , 0x0000},
106 {RT5677_PDM2_DATA_CTRL4 , 0x0000},
107 {RT5677_TDM1_CTRL1 , 0x0300},
108 {RT5677_TDM1_CTRL2 , 0x0000},
109 {RT5677_TDM1_CTRL3 , 0x4000},
110 {RT5677_TDM1_CTRL4 , 0x0123},
111 {RT5677_TDM1_CTRL5 , 0x4567},
112 {RT5677_TDM2_CTRL1 , 0x0300},
113 {RT5677_TDM2_CTRL2 , 0x0000},
114 {RT5677_TDM2_CTRL3 , 0x4000},
115 {RT5677_TDM2_CTRL4 , 0x0123},
116 {RT5677_TDM2_CTRL5 , 0x4567},
117 {RT5677_I2C_MASTER_CTRL1 , 0x0001},
118 {RT5677_I2C_MASTER_CTRL2 , 0x0000},
119 {RT5677_I2C_MASTER_CTRL3 , 0x0000},
120 {RT5677_I2C_MASTER_CTRL4 , 0x0000},
121 {RT5677_I2C_MASTER_CTRL5 , 0x0000},
122 {RT5677_I2C_MASTER_CTRL6 , 0x0000},
123 {RT5677_I2C_MASTER_CTRL7 , 0x0000},
124 {RT5677_I2C_MASTER_CTRL8 , 0x0000},
125 {RT5677_DMIC_CTRL1 , 0x1505},
126 {RT5677_DMIC_CTRL2 , 0x0055},
127 {RT5677_HAP_GENE_CTRL1 , 0x0111},
128 {RT5677_HAP_GENE_CTRL2 , 0x0064},
129 {RT5677_HAP_GENE_CTRL3 , 0xef0e},
130 {RT5677_HAP_GENE_CTRL4 , 0xf0f0},
131 {RT5677_HAP_GENE_CTRL5 , 0xef0e},
132 {RT5677_HAP_GENE_CTRL6 , 0xf0f0},
133 {RT5677_HAP_GENE_CTRL7 , 0xef0e},
134 {RT5677_HAP_GENE_CTRL8 , 0xf0f0},
135 {RT5677_HAP_GENE_CTRL9 , 0xf000},
136 {RT5677_HAP_GENE_CTRL10 , 0x0000},
137 {RT5677_PWR_DIG1 , 0x0000},
138 {RT5677_PWR_DIG2 , 0x0000},
139 {RT5677_PWR_ANLG1 , 0x0055},
140 {RT5677_PWR_ANLG2 , 0x0000},
141 {RT5677_PWR_DSP1 , 0x0001},
142 {RT5677_PWR_DSP_ST , 0x0000},
143 {RT5677_PWR_DSP2 , 0x0000},
144 {RT5677_ADC_DAC_HPF_CTRL1 , 0x0e00},
145 {RT5677_PRIV_INDEX , 0x0000},
146 {RT5677_PRIV_DATA , 0x0000},
147 {RT5677_I2S4_SDP , 0x8000},
148 {RT5677_I2S1_SDP , 0x8000},
149 {RT5677_I2S2_SDP , 0x8000},
150 {RT5677_I2S3_SDP , 0x8000},
151 {RT5677_CLK_TREE_CTRL1 , 0x1111},
152 {RT5677_CLK_TREE_CTRL2 , 0x1111},
153 {RT5677_CLK_TREE_CTRL3 , 0x0000},
154 {RT5677_PLL1_CTRL1 , 0x0000},
155 {RT5677_PLL1_CTRL2 , 0x0000},
156 {RT5677_PLL2_CTRL1 , 0x0c60},
157 {RT5677_PLL2_CTRL2 , 0x2000},
158 {RT5677_GLB_CLK1 , 0x0000},
159 {RT5677_GLB_CLK2 , 0x0000},
160 {RT5677_ASRC_1 , 0x0000},
161 {RT5677_ASRC_2 , 0x0000},
162 {RT5677_ASRC_3 , 0x0000},
163 {RT5677_ASRC_4 , 0x0000},
164 {RT5677_ASRC_5 , 0x0000},
165 {RT5677_ASRC_6 , 0x0000},
166 {RT5677_ASRC_7 , 0x0000},
167 {RT5677_ASRC_8 , 0x0000},
168 {RT5677_ASRC_9 , 0x0000},
169 {RT5677_ASRC_10 , 0x0000},
170 {RT5677_ASRC_11 , 0x0000},
171 {RT5677_ASRC_12 , 0x0008},
172 {RT5677_ASRC_13 , 0x0000},
173 {RT5677_ASRC_14 , 0x0000},
174 {RT5677_ASRC_15 , 0x0000},
175 {RT5677_ASRC_16 , 0x0000},
176 {RT5677_ASRC_17 , 0x0000},
177 {RT5677_ASRC_18 , 0x0000},
178 {RT5677_ASRC_19 , 0x0000},
179 {RT5677_ASRC_20 , 0x0000},
180 {RT5677_ASRC_21 , 0x000c},
181 {RT5677_ASRC_22 , 0x0000},
182 {RT5677_ASRC_23 , 0x0000},
183 {RT5677_VAD_CTRL1 , 0x2184},
184 {RT5677_VAD_CTRL2 , 0x010a},
185 {RT5677_VAD_CTRL3 , 0x0aea},
186 {RT5677_VAD_CTRL4 , 0x000c},
187 {RT5677_VAD_CTRL5 , 0x0000},
188 {RT5677_DSP_INB_CTRL1 , 0x0000},
189 {RT5677_DSP_INB_CTRL2 , 0x0000},
190 {RT5677_DSP_IN_OUTB_CTRL , 0x0000},
191 {RT5677_DSP_OUTB0_1_DIG_VOL , 0x2f2f},
192 {RT5677_DSP_OUTB2_3_DIG_VOL , 0x2f2f},
193 {RT5677_DSP_OUTB4_5_DIG_VOL , 0x2f2f},
194 {RT5677_DSP_OUTB6_7_DIG_VOL , 0x2f2f},
195 {RT5677_ADC_EQ_CTRL1 , 0x6000},
196 {RT5677_ADC_EQ_CTRL2 , 0x0000},
197 {RT5677_EQ_CTRL1 , 0xc000},
198 {RT5677_EQ_CTRL2 , 0x0000},
199 {RT5677_EQ_CTRL3 , 0x0000},
200 {RT5677_SOFT_VOL_ZERO_CROSS1 , 0x0009},
201 {RT5677_JD_CTRL1 , 0x0000},
202 {RT5677_JD_CTRL2 , 0x0000},
203 {RT5677_JD_CTRL3 , 0x0000},
204 {RT5677_IRQ_CTRL1 , 0x0000},
205 {RT5677_IRQ_CTRL2 , 0x0000},
206 {RT5677_GPIO_ST , 0x0000},
207 {RT5677_GPIO_CTRL1 , 0x0000},
208 {RT5677_GPIO_CTRL2 , 0x0000},
209 {RT5677_GPIO_CTRL3 , 0x0000},
210 {RT5677_STO1_ADC_HI_FILTER1 , 0xb320},
211 {RT5677_STO1_ADC_HI_FILTER2 , 0x0000},
212 {RT5677_MONO_ADC_HI_FILTER1 , 0xb300},
213 {RT5677_MONO_ADC_HI_FILTER2 , 0x0000},
214 {RT5677_STO2_ADC_HI_FILTER1 , 0xb300},
215 {RT5677_STO2_ADC_HI_FILTER2 , 0x0000},
216 {RT5677_STO3_ADC_HI_FILTER1 , 0xb300},
217 {RT5677_STO3_ADC_HI_FILTER2 , 0x0000},
218 {RT5677_STO4_ADC_HI_FILTER1 , 0xb300},
219 {RT5677_STO4_ADC_HI_FILTER2 , 0x0000},
220 {RT5677_MB_DRC_CTRL1 , 0x0f20},
221 {RT5677_DRC1_CTRL1 , 0x001f},
222 {RT5677_DRC1_CTRL2 , 0x020c},
223 {RT5677_DRC1_CTRL3 , 0x1f00},
224 {RT5677_DRC1_CTRL4 , 0x0000},
225 {RT5677_DRC1_CTRL5 , 0x0000},
226 {RT5677_DRC1_CTRL6 , 0x0029},
227 {RT5677_DRC2_CTRL1 , 0x001f},
228 {RT5677_DRC2_CTRL2 , 0x020c},
229 {RT5677_DRC2_CTRL3 , 0x1f00},
230 {RT5677_DRC2_CTRL4 , 0x0000},
231 {RT5677_DRC2_CTRL5 , 0x0000},
232 {RT5677_DRC2_CTRL6 , 0x0029},
233 {RT5677_DRC1_HL_CTRL1 , 0x8000},
234 {RT5677_DRC1_HL_CTRL2 , 0x0200},
235 {RT5677_DRC2_HL_CTRL1 , 0x8000},
236 {RT5677_DRC2_HL_CTRL2 , 0x0200},
237 {RT5677_DSP_INB1_SRC_CTRL1 , 0x5800},
238 {RT5677_DSP_INB1_SRC_CTRL2 , 0x0000},
239 {RT5677_DSP_INB1_SRC_CTRL3 , 0x0000},
240 {RT5677_DSP_INB1_SRC_CTRL4 , 0x0800},
241 {RT5677_DSP_INB2_SRC_CTRL1 , 0x5800},
242 {RT5677_DSP_INB2_SRC_CTRL2 , 0x0000},
243 {RT5677_DSP_INB2_SRC_CTRL3 , 0x0000},
244 {RT5677_DSP_INB2_SRC_CTRL4 , 0x0800},
245 {RT5677_DSP_INB3_SRC_CTRL1 , 0x5800},
246 {RT5677_DSP_INB3_SRC_CTRL2 , 0x0000},
247 {RT5677_DSP_INB3_SRC_CTRL3 , 0x0000},
248 {RT5677_DSP_INB3_SRC_CTRL4 , 0x0800},
249 {RT5677_DSP_OUTB1_SRC_CTRL1 , 0x5800},
250 {RT5677_DSP_OUTB1_SRC_CTRL2 , 0x0000},
251 {RT5677_DSP_OUTB1_SRC_CTRL3 , 0x0000},
252 {RT5677_DSP_OUTB1_SRC_CTRL4 , 0x0800},
253 {RT5677_DSP_OUTB2_SRC_CTRL1 , 0x5800},
254 {RT5677_DSP_OUTB2_SRC_CTRL2 , 0x0000},
255 {RT5677_DSP_OUTB2_SRC_CTRL3 , 0x0000},
256 {RT5677_DSP_OUTB2_SRC_CTRL4 , 0x0800},
257 {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
258 {RT5677_DSP_OUTB_45_MIXER_CTRL , 0xfefe},
259 {RT5677_DSP_OUTB_67_MIXER_CTRL , 0xfefe},
260 {RT5677_DIG_MISC , 0x0000},
261 {RT5677_GEN_CTRL1 , 0x0000},
262 {RT5677_GEN_CTRL2 , 0x0000},
263 {RT5677_VENDOR_ID , 0x0000},
264 {RT5677_VENDOR_ID1 , 0x10ec},
265 {RT5677_VENDOR_ID2 , 0x6327},
266};
267
268static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
269{
270 int i;
271
272 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
273 if (reg >= rt5677_ranges[i].range_min &&
274 reg <= rt5677_ranges[i].range_max) {
275 return true;
276 }
277 }
278
279 switch (reg) {
280 case RT5677_RESET:
281 case RT5677_SLIMBUS_PARAM:
282 case RT5677_PDM_DATA_CTRL1:
283 case RT5677_PDM_DATA_CTRL2:
284 case RT5677_PDM1_DATA_CTRL4:
285 case RT5677_PDM2_DATA_CTRL4:
286 case RT5677_I2C_MASTER_CTRL1:
287 case RT5677_I2C_MASTER_CTRL7:
288 case RT5677_I2C_MASTER_CTRL8:
289 case RT5677_HAP_GENE_CTRL2:
290 case RT5677_PWR_DSP_ST:
291 case RT5677_PRIV_DATA:
292 case RT5677_PLL1_CTRL2:
293 case RT5677_PLL2_CTRL2:
294 case RT5677_ASRC_22:
295 case RT5677_ASRC_23:
296 case RT5677_VAD_CTRL5:
297 case RT5677_ADC_EQ_CTRL1:
298 case RT5677_EQ_CTRL1:
299 case RT5677_IRQ_CTRL1:
300 case RT5677_IRQ_CTRL2:
301 case RT5677_GPIO_ST:
302 case RT5677_DSP_INB1_SRC_CTRL4:
303 case RT5677_DSP_INB2_SRC_CTRL4:
304 case RT5677_DSP_INB3_SRC_CTRL4:
305 case RT5677_DSP_OUTB1_SRC_CTRL4:
306 case RT5677_DSP_OUTB2_SRC_CTRL4:
307 case RT5677_VENDOR_ID:
308 case RT5677_VENDOR_ID1:
309 case RT5677_VENDOR_ID2:
310 return true;
311 default:
312 return false;
313 }
314}
315
316static bool rt5677_readable_register(struct device *dev, unsigned int reg)
317{
318 int i;
319
320 for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
321 if (reg >= rt5677_ranges[i].range_min &&
322 reg <= rt5677_ranges[i].range_max) {
323 return true;
324 }
325 }
326
327 switch (reg) {
328 case RT5677_RESET:
329 case RT5677_LOUT1:
330 case RT5677_IN1:
331 case RT5677_MICBIAS:
332 case RT5677_SLIMBUS_PARAM:
333 case RT5677_SLIMBUS_RX:
334 case RT5677_SLIMBUS_CTRL:
335 case RT5677_SIDETONE_CTRL:
336 case RT5677_ANA_DAC1_2_3_SRC:
337 case RT5677_IF_DSP_DAC3_4_MIXER:
338 case RT5677_DAC4_DIG_VOL:
339 case RT5677_DAC3_DIG_VOL:
340 case RT5677_DAC1_DIG_VOL:
341 case RT5677_DAC2_DIG_VOL:
342 case RT5677_IF_DSP_DAC2_MIXER:
343 case RT5677_STO1_ADC_DIG_VOL:
344 case RT5677_MONO_ADC_DIG_VOL:
345 case RT5677_STO1_2_ADC_BST:
346 case RT5677_STO2_ADC_DIG_VOL:
347 case RT5677_ADC_BST_CTRL2:
348 case RT5677_STO3_4_ADC_BST:
349 case RT5677_STO3_ADC_DIG_VOL:
350 case RT5677_STO4_ADC_DIG_VOL:
351 case RT5677_STO4_ADC_MIXER:
352 case RT5677_STO3_ADC_MIXER:
353 case RT5677_STO2_ADC_MIXER:
354 case RT5677_STO1_ADC_MIXER:
355 case RT5677_MONO_ADC_MIXER:
356 case RT5677_ADC_IF_DSP_DAC1_MIXER:
357 case RT5677_STO1_DAC_MIXER:
358 case RT5677_MONO_DAC_MIXER:
359 case RT5677_DD1_MIXER:
360 case RT5677_DD2_MIXER:
361 case RT5677_IF3_DATA:
362 case RT5677_IF4_DATA:
363 case RT5677_PDM_OUT_CTRL:
364 case RT5677_PDM_DATA_CTRL1:
365 case RT5677_PDM_DATA_CTRL2:
366 case RT5677_PDM1_DATA_CTRL2:
367 case RT5677_PDM1_DATA_CTRL3:
368 case RT5677_PDM1_DATA_CTRL4:
369 case RT5677_PDM2_DATA_CTRL2:
370 case RT5677_PDM2_DATA_CTRL3:
371 case RT5677_PDM2_DATA_CTRL4:
372 case RT5677_TDM1_CTRL1:
373 case RT5677_TDM1_CTRL2:
374 case RT5677_TDM1_CTRL3:
375 case RT5677_TDM1_CTRL4:
376 case RT5677_TDM1_CTRL5:
377 case RT5677_TDM2_CTRL1:
378 case RT5677_TDM2_CTRL2:
379 case RT5677_TDM2_CTRL3:
380 case RT5677_TDM2_CTRL4:
381 case RT5677_TDM2_CTRL5:
382 case RT5677_I2C_MASTER_CTRL1:
383 case RT5677_I2C_MASTER_CTRL2:
384 case RT5677_I2C_MASTER_CTRL3:
385 case RT5677_I2C_MASTER_CTRL4:
386 case RT5677_I2C_MASTER_CTRL5:
387 case RT5677_I2C_MASTER_CTRL6:
388 case RT5677_I2C_MASTER_CTRL7:
389 case RT5677_I2C_MASTER_CTRL8:
390 case RT5677_DMIC_CTRL1:
391 case RT5677_DMIC_CTRL2:
392 case RT5677_HAP_GENE_CTRL1:
393 case RT5677_HAP_GENE_CTRL2:
394 case RT5677_HAP_GENE_CTRL3:
395 case RT5677_HAP_GENE_CTRL4:
396 case RT5677_HAP_GENE_CTRL5:
397 case RT5677_HAP_GENE_CTRL6:
398 case RT5677_HAP_GENE_CTRL7:
399 case RT5677_HAP_GENE_CTRL8:
400 case RT5677_HAP_GENE_CTRL9:
401 case RT5677_HAP_GENE_CTRL10:
402 case RT5677_PWR_DIG1:
403 case RT5677_PWR_DIG2:
404 case RT5677_PWR_ANLG1:
405 case RT5677_PWR_ANLG2:
406 case RT5677_PWR_DSP1:
407 case RT5677_PWR_DSP_ST:
408 case RT5677_PWR_DSP2:
409 case RT5677_ADC_DAC_HPF_CTRL1:
410 case RT5677_PRIV_INDEX:
411 case RT5677_PRIV_DATA:
412 case RT5677_I2S4_SDP:
413 case RT5677_I2S1_SDP:
414 case RT5677_I2S2_SDP:
415 case RT5677_I2S3_SDP:
416 case RT5677_CLK_TREE_CTRL1:
417 case RT5677_CLK_TREE_CTRL2:
418 case RT5677_CLK_TREE_CTRL3:
419 case RT5677_PLL1_CTRL1:
420 case RT5677_PLL1_CTRL2:
421 case RT5677_PLL2_CTRL1:
422 case RT5677_PLL2_CTRL2:
423 case RT5677_GLB_CLK1:
424 case RT5677_GLB_CLK2:
425 case RT5677_ASRC_1:
426 case RT5677_ASRC_2:
427 case RT5677_ASRC_3:
428 case RT5677_ASRC_4:
429 case RT5677_ASRC_5:
430 case RT5677_ASRC_6:
431 case RT5677_ASRC_7:
432 case RT5677_ASRC_8:
433 case RT5677_ASRC_9:
434 case RT5677_ASRC_10:
435 case RT5677_ASRC_11:
436 case RT5677_ASRC_12:
437 case RT5677_ASRC_13:
438 case RT5677_ASRC_14:
439 case RT5677_ASRC_15:
440 case RT5677_ASRC_16:
441 case RT5677_ASRC_17:
442 case RT5677_ASRC_18:
443 case RT5677_ASRC_19:
444 case RT5677_ASRC_20:
445 case RT5677_ASRC_21:
446 case RT5677_ASRC_22:
447 case RT5677_ASRC_23:
448 case RT5677_VAD_CTRL1:
449 case RT5677_VAD_CTRL2:
450 case RT5677_VAD_CTRL3:
451 case RT5677_VAD_CTRL4:
452 case RT5677_VAD_CTRL5:
453 case RT5677_DSP_INB_CTRL1:
454 case RT5677_DSP_INB_CTRL2:
455 case RT5677_DSP_IN_OUTB_CTRL:
456 case RT5677_DSP_OUTB0_1_DIG_VOL:
457 case RT5677_DSP_OUTB2_3_DIG_VOL:
458 case RT5677_DSP_OUTB4_5_DIG_VOL:
459 case RT5677_DSP_OUTB6_7_DIG_VOL:
460 case RT5677_ADC_EQ_CTRL1:
461 case RT5677_ADC_EQ_CTRL2:
462 case RT5677_EQ_CTRL1:
463 case RT5677_EQ_CTRL2:
464 case RT5677_EQ_CTRL3:
465 case RT5677_SOFT_VOL_ZERO_CROSS1:
466 case RT5677_JD_CTRL1:
467 case RT5677_JD_CTRL2:
468 case RT5677_JD_CTRL3:
469 case RT5677_IRQ_CTRL1:
470 case RT5677_IRQ_CTRL2:
471 case RT5677_GPIO_ST:
472 case RT5677_GPIO_CTRL1:
473 case RT5677_GPIO_CTRL2:
474 case RT5677_GPIO_CTRL3:
475 case RT5677_STO1_ADC_HI_FILTER1:
476 case RT5677_STO1_ADC_HI_FILTER2:
477 case RT5677_MONO_ADC_HI_FILTER1:
478 case RT5677_MONO_ADC_HI_FILTER2:
479 case RT5677_STO2_ADC_HI_FILTER1:
480 case RT5677_STO2_ADC_HI_FILTER2:
481 case RT5677_STO3_ADC_HI_FILTER1:
482 case RT5677_STO3_ADC_HI_FILTER2:
483 case RT5677_STO4_ADC_HI_FILTER1:
484 case RT5677_STO4_ADC_HI_FILTER2:
485 case RT5677_MB_DRC_CTRL1:
486 case RT5677_DRC1_CTRL1:
487 case RT5677_DRC1_CTRL2:
488 case RT5677_DRC1_CTRL3:
489 case RT5677_DRC1_CTRL4:
490 case RT5677_DRC1_CTRL5:
491 case RT5677_DRC1_CTRL6:
492 case RT5677_DRC2_CTRL1:
493 case RT5677_DRC2_CTRL2:
494 case RT5677_DRC2_CTRL3:
495 case RT5677_DRC2_CTRL4:
496 case RT5677_DRC2_CTRL5:
497 case RT5677_DRC2_CTRL6:
498 case RT5677_DRC1_HL_CTRL1:
499 case RT5677_DRC1_HL_CTRL2:
500 case RT5677_DRC2_HL_CTRL1:
501 case RT5677_DRC2_HL_CTRL2:
502 case RT5677_DSP_INB1_SRC_CTRL1:
503 case RT5677_DSP_INB1_SRC_CTRL2:
504 case RT5677_DSP_INB1_SRC_CTRL3:
505 case RT5677_DSP_INB1_SRC_CTRL4:
506 case RT5677_DSP_INB2_SRC_CTRL1:
507 case RT5677_DSP_INB2_SRC_CTRL2:
508 case RT5677_DSP_INB2_SRC_CTRL3:
509 case RT5677_DSP_INB2_SRC_CTRL4:
510 case RT5677_DSP_INB3_SRC_CTRL1:
511 case RT5677_DSP_INB3_SRC_CTRL2:
512 case RT5677_DSP_INB3_SRC_CTRL3:
513 case RT5677_DSP_INB3_SRC_CTRL4:
514 case RT5677_DSP_OUTB1_SRC_CTRL1:
515 case RT5677_DSP_OUTB1_SRC_CTRL2:
516 case RT5677_DSP_OUTB1_SRC_CTRL3:
517 case RT5677_DSP_OUTB1_SRC_CTRL4:
518 case RT5677_DSP_OUTB2_SRC_CTRL1:
519 case RT5677_DSP_OUTB2_SRC_CTRL2:
520 case RT5677_DSP_OUTB2_SRC_CTRL3:
521 case RT5677_DSP_OUTB2_SRC_CTRL4:
522 case RT5677_DSP_OUTB_0123_MIXER_CTRL:
523 case RT5677_DSP_OUTB_45_MIXER_CTRL:
524 case RT5677_DSP_OUTB_67_MIXER_CTRL:
525 case RT5677_DIG_MISC:
526 case RT5677_GEN_CTRL1:
527 case RT5677_GEN_CTRL2:
528 case RT5677_VENDOR_ID:
529 case RT5677_VENDOR_ID1:
530 case RT5677_VENDOR_ID2:
531 return true;
532 default:
533 return false;
534 }
535}
536
537static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
538static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
539static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
540static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
541static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
542
543/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
544static unsigned int bst_tlv[] = {
545 TLV_DB_RANGE_HEAD(7),
546 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
547 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
548 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
549 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
550 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
551 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
552 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
553};
554
555static const struct snd_kcontrol_new rt5677_snd_controls[] = {
556 /* OUTPUT Control */
557 SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
558 RT5677_LOUT1_L_MUTE_SFT, 1, 1),
559 SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
560 RT5677_LOUT2_L_MUTE_SFT, 1, 1),
561 SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
562 RT5677_LOUT3_L_MUTE_SFT, 1, 1),
563
564 /* DAC Digital Volume */
565 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
566 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
567 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
568 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
569 SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
570 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
571 SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
572 RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 175, 0, dac_vol_tlv),
573
574 /* IN1/IN2 Control */
575 SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
576 SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),
577
578 /* ADC Digital Volume Control */
579 SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
580 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
581 SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
582 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
583 SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
584 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
585 SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
586 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
587 SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
588 RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
589
590 SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
591 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
592 adc_vol_tlv),
593 SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
594 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
595 adc_vol_tlv),
596 SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
597 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
598 adc_vol_tlv),
599 SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
600 RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 127, 0,
601 adc_vol_tlv),
602 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
603 RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 127, 0,
604 adc_vol_tlv),
605
606 /* ADC Boost Volume Control */
607 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
608 RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
609 adc_bst_tlv),
610 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5677_STO1_2_ADC_BST,
611 RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
612 adc_bst_tlv),
613 SOC_DOUBLE_TLV("STO3 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
614 RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
615 adc_bst_tlv),
616 SOC_DOUBLE_TLV("STO4 ADC Boost Gain", RT5677_STO3_4_ADC_BST,
617 RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
618 adc_bst_tlv),
619 SOC_DOUBLE_TLV("Mono ADC Boost Gain", RT5677_ADC_BST_CTRL2,
620 RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
621 adc_bst_tlv),
622};
623
624/**
625 * set_dmic_clk - Set parameter of dmic.
626 *
627 * @w: DAPM widget.
628 * @kcontrol: The kcontrol of this widget.
629 * @event: Event id.
630 *
631 * Choose dmic clock between 1MHz and 3MHz.
632 * It is better for clock to approximate 3MHz.
633 */
634static int set_dmic_clk(struct snd_soc_dapm_widget *w,
635 struct snd_kcontrol *kcontrol, int event)
636{
637 struct snd_soc_codec *codec = w->codec;
638 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
639 int div[] = {2, 3, 4, 6, 8, 12}, idx = -EINVAL, i;
640 int rate, red, bound, temp;
641
642 rate = rt5677->sysclk;
643 red = 3000000 * 12;
644 for (i = 0; i < ARRAY_SIZE(div); i++) {
645 bound = div[i] * 3000000;
646 if (rate > bound)
647 continue;
648 temp = bound - rate;
649 if (temp < red) {
650 red = temp;
651 idx = i;
652 }
653 }
654
655 if (idx < 0)
656 dev_err(codec->dev, "Failed to set DMIC clock\n");
657 else
658 regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
659 RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
660 return idx;
661}
662
663static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
664 struct snd_soc_dapm_widget *sink)
665{
666 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(source->codec);
667 unsigned int val;
668
669 regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
670 val &= RT5677_SCLK_SRC_MASK;
671 if (val == RT5677_SCLK_SRC_PLL1)
672 return 1;
673 else
674 return 0;
675}
676
677/* Digital Mixer */
678static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
679 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
680 RT5677_M_STO1_ADC_L1_SFT, 1, 1),
681 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
682 RT5677_M_STO1_ADC_L2_SFT, 1, 1),
683};
684
685static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
686 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
687 RT5677_M_STO1_ADC_R1_SFT, 1, 1),
688 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
689 RT5677_M_STO1_ADC_R2_SFT, 1, 1),
690};
691
692static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
693 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
694 RT5677_M_STO2_ADC_L1_SFT, 1, 1),
695 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
696 RT5677_M_STO2_ADC_L2_SFT, 1, 1),
697};
698
699static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
700 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
701 RT5677_M_STO2_ADC_R1_SFT, 1, 1),
702 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
703 RT5677_M_STO2_ADC_R2_SFT, 1, 1),
704};
705
706static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
707 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
708 RT5677_M_STO3_ADC_L1_SFT, 1, 1),
709 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
710 RT5677_M_STO3_ADC_L2_SFT, 1, 1),
711};
712
713static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
714 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
715 RT5677_M_STO3_ADC_R1_SFT, 1, 1),
716 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
717 RT5677_M_STO3_ADC_R2_SFT, 1, 1),
718};
719
720static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
721 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
722 RT5677_M_STO4_ADC_L1_SFT, 1, 1),
723 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
724 RT5677_M_STO4_ADC_L2_SFT, 1, 1),
725};
726
727static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
728 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
729 RT5677_M_STO4_ADC_R1_SFT, 1, 1),
730 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
731 RT5677_M_STO4_ADC_R2_SFT, 1, 1),
732};
733
734static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
735 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
736 RT5677_M_MONO_ADC_L1_SFT, 1, 1),
737 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
738 RT5677_M_MONO_ADC_L2_SFT, 1, 1),
739};
740
741static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
742 SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
743 RT5677_M_MONO_ADC_R1_SFT, 1, 1),
744 SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
745 RT5677_M_MONO_ADC_R2_SFT, 1, 1),
746};
747
748static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
749 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
750 RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
751 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
752 RT5677_M_DAC1_L_SFT, 1, 1),
753};
754
755static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
756 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
757 RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
758 SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
759 RT5677_M_DAC1_R_SFT, 1, 1),
760};
761
762static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
763 SOC_DAPM_SINGLE("ST L Switch", RT5677_STO1_DAC_MIXER,
764 RT5677_M_ST_DAC1_L_SFT, 1, 1),
765 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
766 RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
767 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
768 RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
769 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
770 RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
771};
772
773static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
774 SOC_DAPM_SINGLE("ST R Switch", RT5677_STO1_DAC_MIXER,
775 RT5677_M_ST_DAC1_R_SFT, 1, 1),
776 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
777 RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
778 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
779 RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
780 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
781 RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
782};
783
784static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
785 SOC_DAPM_SINGLE("ST L Switch", RT5677_MONO_DAC_MIXER,
786 RT5677_M_ST_DAC2_L_SFT, 1, 1),
787 SOC_DAPM_SINGLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
788 RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
789 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
790 RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
791 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
792 RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
793};
794
795static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
796 SOC_DAPM_SINGLE("ST R Switch", RT5677_MONO_DAC_MIXER,
797 RT5677_M_ST_DAC2_R_SFT, 1, 1),
798 SOC_DAPM_SINGLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
799 RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
800 SOC_DAPM_SINGLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
801 RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
802 SOC_DAPM_SINGLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
803 RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
804};
805
806static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
807 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
808 RT5677_M_STO_L_DD1_L_SFT, 1, 1),
809 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
810 RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
811 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
812 RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
813 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
814 RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
815};
816
817static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
818 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
819 RT5677_M_STO_R_DD1_R_SFT, 1, 1),
820 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
821 RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
822 SOC_DAPM_SINGLE("DAC3 R Switch", RT5677_DD1_MIXER,
823 RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
824 SOC_DAPM_SINGLE("DAC3 L Switch", RT5677_DD1_MIXER,
825 RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
826};
827
828static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
829 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
830 RT5677_M_STO_L_DD2_L_SFT, 1, 1),
831 SOC_DAPM_SINGLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
832 RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
833 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
834 RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
835 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
836 RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
837};
838
839static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
840 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
841 RT5677_M_STO_R_DD2_R_SFT, 1, 1),
842 SOC_DAPM_SINGLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
843 RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
844 SOC_DAPM_SINGLE("DAC4 R Switch", RT5677_DD2_MIXER,
845 RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
846 SOC_DAPM_SINGLE("DAC4 L Switch", RT5677_DD2_MIXER,
847 RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
848};
849
850static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
851 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
852 RT5677_DSP_IB_01_H_SFT, 1, 1),
853 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
854 RT5677_DSP_IB_23_H_SFT, 1, 1),
855 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
856 RT5677_DSP_IB_45_H_SFT, 1, 1),
857 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
858 RT5677_DSP_IB_6_H_SFT, 1, 1),
859 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
860 RT5677_DSP_IB_7_H_SFT, 1, 1),
861 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
862 RT5677_DSP_IB_8_H_SFT, 1, 1),
863 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
864 RT5677_DSP_IB_9_H_SFT, 1, 1),
865};
866
867static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
868 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
869 RT5677_DSP_IB_01_L_SFT, 1, 1),
870 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
871 RT5677_DSP_IB_23_L_SFT, 1, 1),
872 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
873 RT5677_DSP_IB_45_L_SFT, 1, 1),
874 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
875 RT5677_DSP_IB_6_L_SFT, 1, 1),
876 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
877 RT5677_DSP_IB_7_L_SFT, 1, 1),
878 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
879 RT5677_DSP_IB_8_L_SFT, 1, 1),
880 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
881 RT5677_DSP_IB_9_L_SFT, 1, 1),
882};
883
884static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
885 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
886 RT5677_DSP_IB_01_H_SFT, 1, 1),
887 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
888 RT5677_DSP_IB_23_H_SFT, 1, 1),
889 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
890 RT5677_DSP_IB_45_H_SFT, 1, 1),
891 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
892 RT5677_DSP_IB_6_H_SFT, 1, 1),
893 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
894 RT5677_DSP_IB_7_H_SFT, 1, 1),
895 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
896 RT5677_DSP_IB_8_H_SFT, 1, 1),
897 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
898 RT5677_DSP_IB_9_H_SFT, 1, 1),
899};
900
901static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
902 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
903 RT5677_DSP_IB_01_L_SFT, 1, 1),
904 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
905 RT5677_DSP_IB_23_L_SFT, 1, 1),
906 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
907 RT5677_DSP_IB_45_L_SFT, 1, 1),
908 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
909 RT5677_DSP_IB_6_L_SFT, 1, 1),
910 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
911 RT5677_DSP_IB_7_L_SFT, 1, 1),
912 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
913 RT5677_DSP_IB_8_L_SFT, 1, 1),
914 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
915 RT5677_DSP_IB_9_L_SFT, 1, 1),
916};
917
918static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
919 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
920 RT5677_DSP_IB_01_H_SFT, 1, 1),
921 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
922 RT5677_DSP_IB_23_H_SFT, 1, 1),
923 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
924 RT5677_DSP_IB_45_H_SFT, 1, 1),
925 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
926 RT5677_DSP_IB_6_H_SFT, 1, 1),
927 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
928 RT5677_DSP_IB_7_H_SFT, 1, 1),
929 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
930 RT5677_DSP_IB_8_H_SFT, 1, 1),
931 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
932 RT5677_DSP_IB_9_H_SFT, 1, 1),
933};
934
935static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
936 SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
937 RT5677_DSP_IB_01_L_SFT, 1, 1),
938 SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
939 RT5677_DSP_IB_23_L_SFT, 1, 1),
940 SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
941 RT5677_DSP_IB_45_L_SFT, 1, 1),
942 SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
943 RT5677_DSP_IB_6_L_SFT, 1, 1),
944 SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
945 RT5677_DSP_IB_7_L_SFT, 1, 1),
946 SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
947 RT5677_DSP_IB_8_L_SFT, 1, 1),
948 SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
949 RT5677_DSP_IB_9_L_SFT, 1, 1),
950};
951
952
953/* Mux */
954/* DAC1 L/R source */ /* MX-29 [10:8] */
955static const char * const rt5677_dac1_src[] = {
956 "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
957 "OB 01"
958};
959
960static SOC_ENUM_SINGLE_DECL(
961 rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
962 RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);
963
964static const struct snd_kcontrol_new rt5677_dac1_mux =
965 SOC_DAPM_ENUM("DAC1 source", rt5677_dac1_enum);
966
967/* ADDA1 L/R source */ /* MX-29 [1:0] */
968static const char * const rt5677_adda1_src[] = {
969 "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
970};
971
972static SOC_ENUM_SINGLE_DECL(
973 rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
974 RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);
975
976static const struct snd_kcontrol_new rt5677_adda1_mux =
977 SOC_DAPM_ENUM("ADDA1 source", rt5677_adda1_enum);
978
979
980/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
981static const char * const rt5677_dac2l_src[] = {
982 "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
983 "OB 2",
984};
985
986static SOC_ENUM_SINGLE_DECL(
987 rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
988 RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);
989
990static const struct snd_kcontrol_new rt5677_dac2_l_mux =
991 SOC_DAPM_ENUM("DAC2 L source", rt5677_dac2l_enum);
992
993static const char * const rt5677_dac2r_src[] = {
994 "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
995 "OB 3", "Haptic Generator", "VAD ADC"
996};
997
998static SOC_ENUM_SINGLE_DECL(
999 rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
1000 RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);
1001
1002static const struct snd_kcontrol_new rt5677_dac2_r_mux =
1003 SOC_DAPM_ENUM("DAC2 R source", rt5677_dac2r_enum);
1004
1005/*DAC3 L/R source*/ /* MX-16 [6:4] [2:0] */
1006static const char * const rt5677_dac3l_src[] = {
1007 "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
1008 "SLB DAC 4", "OB 4"
1009};
1010
1011static SOC_ENUM_SINGLE_DECL(
1012 rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1013 RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);
1014
1015static const struct snd_kcontrol_new rt5677_dac3_l_mux =
1016 SOC_DAPM_ENUM("DAC3 L source", rt5677_dac3l_enum);
1017
1018static const char * const rt5677_dac3r_src[] = {
1019 "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
1020 "SLB DAC 5", "OB 5"
1021};
1022
1023static SOC_ENUM_SINGLE_DECL(
1024 rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1025 RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);
1026
1027static const struct snd_kcontrol_new rt5677_dac3_r_mux =
1028 SOC_DAPM_ENUM("DAC3 R source", rt5677_dac3r_enum);
1029
1030/*DAC4 L/R source*/ /* MX-16 [14:12] [10:8] */
1031static const char * const rt5677_dac4l_src[] = {
1032 "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
1033 "SLB DAC 6", "OB 6"
1034};
1035
1036static SOC_ENUM_SINGLE_DECL(
1037 rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1038 RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);
1039
1040static const struct snd_kcontrol_new rt5677_dac4_l_mux =
1041 SOC_DAPM_ENUM("DAC4 L source", rt5677_dac4l_enum);
1042
1043static const char * const rt5677_dac4r_src[] = {
1044 "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
1045 "SLB DAC 7", "OB 7"
1046};
1047
1048static SOC_ENUM_SINGLE_DECL(
1049 rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
1050 RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);
1051
1052static const struct snd_kcontrol_new rt5677_dac4_r_mux =
1053 SOC_DAPM_ENUM("DAC4 R source", rt5677_dac4r_enum);
1054
1055/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
1056static const char * const rt5677_iob_bypass_src[] = {
1057 "Bypass", "Pass SRC"
1058};
1059
1060static SOC_ENUM_SINGLE_DECL(
1061 rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1062 RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);
1063
1064static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
1065 SOC_DAPM_ENUM("OB01 Bypass source", rt5677_ob01_bypass_src_enum);
1066
1067static SOC_ENUM_SINGLE_DECL(
1068 rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1069 RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);
1070
1071static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
1072 SOC_DAPM_ENUM("OB23 Bypass source", rt5677_ob23_bypass_src_enum);
1073
1074static SOC_ENUM_SINGLE_DECL(
1075 rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1076 RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);
1077
1078static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
1079 SOC_DAPM_ENUM("IB01 Bypass source", rt5677_ib01_bypass_src_enum);
1080
1081static SOC_ENUM_SINGLE_DECL(
1082 rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1083 RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);
1084
1085static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
1086 SOC_DAPM_ENUM("IB23 Bypass source", rt5677_ib23_bypass_src_enum);
1087
1088static SOC_ENUM_SINGLE_DECL(
1089 rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
1090 RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);
1091
1092static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
1093 SOC_DAPM_ENUM("IB45 Bypass source", rt5677_ib45_bypass_src_enum);
1094
1095/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
1096static const char * const rt5677_stereo_adc2_src[] = {
1097 "DD MIX1", "DMIC", "Stereo DAC MIX"
1098};
1099
1100static SOC_ENUM_SINGLE_DECL(
1101 rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
1102 RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);
1103
1104static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
1105 SOC_DAPM_ENUM("Stereo1 ADC2 source", rt5677_stereo1_adc2_enum);
1106
1107static SOC_ENUM_SINGLE_DECL(
1108 rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
1109 RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);
1110
1111static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
1112 SOC_DAPM_ENUM("Stereo2 ADC2 source", rt5677_stereo2_adc2_enum);
1113
1114static SOC_ENUM_SINGLE_DECL(
1115 rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
1116 RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);
1117
1118static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
1119 SOC_DAPM_ENUM("Stereo3 ADC2 source", rt5677_stereo3_adc2_enum);
1120
1121/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
1122static const char * const rt5677_dmic_src[] = {
1123 "DMIC1", "DMIC2", "DMIC3", "DMIC4"
1124};
1125
1126static SOC_ENUM_SINGLE_DECL(
1127 rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
1128 RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);
1129
1130static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
1131 SOC_DAPM_ENUM("Mono DMIC L source", rt5677_mono_dmic_l_enum);
1132
1133static SOC_ENUM_SINGLE_DECL(
1134 rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
1135 RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);
1136
1137static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
1138 SOC_DAPM_ENUM("Mono DMIC R source", rt5677_mono_dmic_r_enum);
1139
1140static SOC_ENUM_SINGLE_DECL(
1141 rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
1142 RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);
1143
1144static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
1145 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5677_stereo1_dmic_enum);
1146
1147static SOC_ENUM_SINGLE_DECL(
1148 rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
1149 RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);
1150
1151static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
1152 SOC_DAPM_ENUM("Stereo2 DMIC source", rt5677_stereo2_dmic_enum);
1153
1154static SOC_ENUM_SINGLE_DECL(
1155 rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
1156 RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);
1157
1158static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
1159 SOC_DAPM_ENUM("Stereo3 DMIC source", rt5677_stereo3_dmic_enum);
1160
1161static SOC_ENUM_SINGLE_DECL(
1162 rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
1163 RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);
1164
1165static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
1166 SOC_DAPM_ENUM("Stereo4 DMIC source", rt5677_stereo4_dmic_enum);
1167
1168/* Stereo2 ADC source */ /* MX-26 [0] */
1169static const char * const rt5677_stereo2_adc_lr_src[] = {
1170 "L", "LR"
1171};
1172
1173static SOC_ENUM_SINGLE_DECL(
1174 rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
1175 RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);
1176
1177static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
1178 SOC_DAPM_ENUM("Stereo2 ADC LR source", rt5677_stereo2_adc_lr_enum);
1179
1180/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
1181static const char * const rt5677_stereo_adc1_src[] = {
1182 "DD MIX1", "ADC1/2", "Stereo DAC MIX"
1183};
1184
1185static SOC_ENUM_SINGLE_DECL(
1186 rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
1187 RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);
1188
1189static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
1190 SOC_DAPM_ENUM("Stereo1 ADC1 source", rt5677_stereo1_adc1_enum);
1191
1192static SOC_ENUM_SINGLE_DECL(
1193 rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
1194 RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);
1195
1196static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
1197 SOC_DAPM_ENUM("Stereo2 ADC1 source", rt5677_stereo2_adc1_enum);
1198
1199static SOC_ENUM_SINGLE_DECL(
1200 rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
1201 RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);
1202
1203static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
1204 SOC_DAPM_ENUM("Stereo3 ADC1 source", rt5677_stereo3_adc1_enum);
1205
1206/* Mono ADC Left source 2 */ /* MX-28 [11:10] */
1207static const char * const rt5677_mono_adc2_l_src[] = {
1208 "DD MIX1L", "DMIC", "MONO DAC MIXL"
1209};
1210
1211static SOC_ENUM_SINGLE_DECL(
1212 rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
1213 RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);
1214
1215static const struct snd_kcontrol_new rt5677_mono_adc2_l_mux =
1216 SOC_DAPM_ENUM("Mono ADC2 L source", rt5677_mono_adc2_l_enum);
1217
1218/* Mono ADC Left source 1 */ /* MX-28 [13:12] */
1219static const char * const rt5677_mono_adc1_l_src[] = {
1220 "DD MIX1L", "ADC1", "MONO DAC MIXL"
1221};
1222
1223static SOC_ENUM_SINGLE_DECL(
1224 rt5677_mono_adc1_l_enum, RT5677_MONO_ADC_MIXER,
1225 RT5677_SEL_MONO_ADC_L1_SFT, rt5677_mono_adc1_l_src);
1226
1227static const struct snd_kcontrol_new rt5677_mono_adc1_l_mux =
1228 SOC_DAPM_ENUM("Mono ADC1 L source", rt5677_mono_adc1_l_enum);
1229
1230/* Mono ADC Right source 2 */ /* MX-28 [3:2] */
1231static const char * const rt5677_mono_adc2_r_src[] = {
1232 "DD MIX1R", "DMIC", "MONO DAC MIXR"
1233};
1234
1235static SOC_ENUM_SINGLE_DECL(
1236 rt5677_mono_adc2_r_enum, RT5677_MONO_ADC_MIXER,
1237 RT5677_SEL_MONO_ADC_R2_SFT, rt5677_mono_adc2_r_src);
1238
1239static const struct snd_kcontrol_new rt5677_mono_adc2_r_mux =
1240 SOC_DAPM_ENUM("Mono ADC2 R source", rt5677_mono_adc2_r_enum);
1241
1242/* Mono ADC Right source 1 */ /* MX-28 [5:4] */
1243static const char * const rt5677_mono_adc1_r_src[] = {
1244 "DD MIX1R", "ADC2", "MONO DAC MIXR"
1245};
1246
1247static SOC_ENUM_SINGLE_DECL(
1248 rt5677_mono_adc1_r_enum, RT5677_MONO_ADC_MIXER,
1249 RT5677_SEL_MONO_ADC_R1_SFT, rt5677_mono_adc1_r_src);
1250
1251static const struct snd_kcontrol_new rt5677_mono_adc1_r_mux =
1252 SOC_DAPM_ENUM("Mono ADC1 R source", rt5677_mono_adc1_r_enum);
1253
1254/* Stereo4 ADC Source 2 */ /* MX-24 [11:10] */
1255static const char * const rt5677_stereo4_adc2_src[] = {
1256 "DD MIX1", "DMIC", "DD MIX2"
1257};
1258
1259static SOC_ENUM_SINGLE_DECL(
1260 rt5677_stereo4_adc2_enum, RT5677_STO4_ADC_MIXER,
1261 RT5677_SEL_STO4_ADC2_SFT, rt5677_stereo4_adc2_src);
1262
1263static const struct snd_kcontrol_new rt5677_sto4_adc2_mux =
1264 SOC_DAPM_ENUM("Stereo4 ADC2 source", rt5677_stereo4_adc2_enum);
1265
1266
1267/* Stereo4 ADC Source 1 */ /* MX-24 [13:12] */
1268static const char * const rt5677_stereo4_adc1_src[] = {
1269 "DD MIX1", "ADC1/2", "DD MIX2"
1270};
1271
1272static SOC_ENUM_SINGLE_DECL(
1273 rt5677_stereo4_adc1_enum, RT5677_STO4_ADC_MIXER,
1274 RT5677_SEL_STO4_ADC1_SFT, rt5677_stereo4_adc1_src);
1275
1276static const struct snd_kcontrol_new rt5677_sto4_adc1_mux =
1277 SOC_DAPM_ENUM("Stereo4 ADC1 source", rt5677_stereo4_adc1_enum);
1278
1279/* InBound0/1 Source */ /* MX-A3 [14:12] */
1280static const char * const rt5677_inbound01_src[] = {
1281 "IF1 DAC 01", "IF2 DAC 01", "SLB DAC 01", "STO1 ADC MIX",
1282 "VAD ADC/DAC1 FS"
1283};
1284
1285static SOC_ENUM_SINGLE_DECL(
1286 rt5677_inbound01_enum, RT5677_DSP_INB_CTRL1,
1287 RT5677_IB01_SRC_SFT, rt5677_inbound01_src);
1288
1289static const struct snd_kcontrol_new rt5677_ib01_src_mux =
1290 SOC_DAPM_ENUM("InBound0/1 Source", rt5677_inbound01_enum);
1291
1292/* InBound2/3 Source */ /* MX-A3 [10:8] */
1293static const char * const rt5677_inbound23_src[] = {
1294 "IF1 DAC 23", "IF2 DAC 23", "SLB DAC 23", "STO2 ADC MIX",
1295 "DAC1 FS", "IF4 DAC"
1296};
1297
1298static SOC_ENUM_SINGLE_DECL(
1299 rt5677_inbound23_enum, RT5677_DSP_INB_CTRL1,
1300 RT5677_IB23_SRC_SFT, rt5677_inbound23_src);
1301
1302static const struct snd_kcontrol_new rt5677_ib23_src_mux =
1303 SOC_DAPM_ENUM("InBound2/3 Source", rt5677_inbound23_enum);
1304
1305/* InBound4/5 Source */ /* MX-A3 [6:4] */
1306static const char * const rt5677_inbound45_src[] = {
1307 "IF1 DAC 45", "IF2 DAC 45", "SLB DAC 45", "STO3 ADC MIX",
1308 "IF3 DAC"
1309};
1310
1311static SOC_ENUM_SINGLE_DECL(
1312 rt5677_inbound45_enum, RT5677_DSP_INB_CTRL1,
1313 RT5677_IB45_SRC_SFT, rt5677_inbound45_src);
1314
1315static const struct snd_kcontrol_new rt5677_ib45_src_mux =
1316 SOC_DAPM_ENUM("InBound4/5 Source", rt5677_inbound45_enum);
1317
1318/* InBound6 Source */ /* MX-A3 [2:0] */
1319static const char * const rt5677_inbound6_src[] = {
1320 "IF1 DAC 6", "IF2 DAC 6", "SLB DAC 6", "STO4 ADC MIX L",
1321 "IF4 DAC L", "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L"
1322};
1323
1324static SOC_ENUM_SINGLE_DECL(
1325 rt5677_inbound6_enum, RT5677_DSP_INB_CTRL1,
1326 RT5677_IB6_SRC_SFT, rt5677_inbound6_src);
1327
1328static const struct snd_kcontrol_new rt5677_ib6_src_mux =
1329 SOC_DAPM_ENUM("InBound6 Source", rt5677_inbound6_enum);
1330
1331/* InBound7 Source */ /* MX-A4 [14:12] */
1332static const char * const rt5677_inbound7_src[] = {
1333 "IF1 DAC 7", "IF2 DAC 7", "SLB DAC 7", "STO4 ADC MIX R",
1334 "IF4 DAC R", "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R"
1335};
1336
1337static SOC_ENUM_SINGLE_DECL(
1338 rt5677_inbound7_enum, RT5677_DSP_INB_CTRL2,
1339 RT5677_IB7_SRC_SFT, rt5677_inbound7_src);
1340
1341static const struct snd_kcontrol_new rt5677_ib7_src_mux =
1342 SOC_DAPM_ENUM("InBound7 Source", rt5677_inbound7_enum);
1343
1344/* InBound8 Source */ /* MX-A4 [10:8] */
1345static const char * const rt5677_inbound8_src[] = {
1346 "STO1 ADC MIX L", "STO2 ADC MIX L", "STO3 ADC MIX L", "STO4 ADC MIX L",
1347 "MONO ADC MIX L", "DACL1 FS"
1348};
1349
1350static SOC_ENUM_SINGLE_DECL(
1351 rt5677_inbound8_enum, RT5677_DSP_INB_CTRL2,
1352 RT5677_IB8_SRC_SFT, rt5677_inbound8_src);
1353
1354static const struct snd_kcontrol_new rt5677_ib8_src_mux =
1355 SOC_DAPM_ENUM("InBound8 Source", rt5677_inbound8_enum);
1356
1357/* InBound9 Source */ /* MX-A4 [6:4] */
1358static const char * const rt5677_inbound9_src[] = {
1359 "STO1 ADC MIX R", "STO2 ADC MIX R", "STO3 ADC MIX R", "STO4 ADC MIX R",
1360 "MONO ADC MIX R", "DACR1 FS", "DAC1 FS"
1361};
1362
1363static SOC_ENUM_SINGLE_DECL(
1364 rt5677_inbound9_enum, RT5677_DSP_INB_CTRL2,
1365 RT5677_IB9_SRC_SFT, rt5677_inbound9_src);
1366
1367static const struct snd_kcontrol_new rt5677_ib9_src_mux =
1368 SOC_DAPM_ENUM("InBound9 Source", rt5677_inbound9_enum);
1369
1370/* VAD Source */ /* MX-9F [6:4] */
1371static const char * const rt5677_vad_src[] = {
1372 "STO1 ADC MIX L", "MONO ADC MIX L", "MONO ADC MIX R", "STO2 ADC MIX L",
1373 "STO3 ADC MIX L"
1374};
1375
1376static SOC_ENUM_SINGLE_DECL(
1377 rt5677_vad_enum, RT5677_VAD_CTRL4,
1378 RT5677_VAD_SRC_SFT, rt5677_vad_src);
1379
1380static const struct snd_kcontrol_new rt5677_vad_src_mux =
1381 SOC_DAPM_ENUM("VAD Source", rt5677_vad_enum);
1382
1383/* Sidetone Source */ /* MX-13 [11:9] */
1384static const char * const rt5677_sidetone_src[] = {
1385 "DMIC1 L", "DMIC2 L", "DMIC3 L", "DMIC4 L", "ADC1", "ADC2"
1386};
1387
1388static SOC_ENUM_SINGLE_DECL(
1389 rt5677_sidetone_enum, RT5677_SIDETONE_CTRL,
1390 RT5677_ST_SEL_SFT, rt5677_sidetone_src);
1391
1392static const struct snd_kcontrol_new rt5677_sidetone_mux =
1393 SOC_DAPM_ENUM("Sidetone Source", rt5677_sidetone_enum);
1394
1395/* DAC1/2 Source */ /* MX-15 [1:0] */
1396static const char * const rt5677_dac12_src[] = {
1397 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1398};
1399
1400static SOC_ENUM_SINGLE_DECL(
1401 rt5677_dac12_enum, RT5677_ANA_DAC1_2_3_SRC,
1402 RT5677_ANA_DAC1_2_SRC_SEL_SFT, rt5677_dac12_src);
1403
1404static const struct snd_kcontrol_new rt5677_dac12_mux =
1405 SOC_DAPM_ENUM("Analog DAC1/2 Source", rt5677_dac12_enum);
1406
1407/* DAC3 Source */ /* MX-15 [5:4] */
1408static const char * const rt5677_dac3_src[] = {
1409 "MONO DAC MIXL", "MONO DAC MIXR", "DD MIX1L", "DD MIX2L"
1410};
1411
1412static SOC_ENUM_SINGLE_DECL(
1413 rt5677_dac3_enum, RT5677_ANA_DAC1_2_3_SRC,
1414 RT5677_ANA_DAC3_SRC_SEL_SFT, rt5677_dac3_src);
1415
1416static const struct snd_kcontrol_new rt5677_dac3_mux =
1417 SOC_DAPM_ENUM("Analog DAC3 Source", rt5677_dac3_enum);
1418
1419/* PDM channel source */ /* MX-31 [13:12][9:8][5:4][1:0] */
1420static const char * const rt5677_pdm_src[] = {
1421 "STO1 DAC MIX", "MONO DAC MIX", "DD MIX1", "DD MIX2"
1422};
1423
1424static SOC_ENUM_SINGLE_DECL(
1425 rt5677_pdm1_l_enum, RT5677_PDM_OUT_CTRL,
1426 RT5677_SEL_PDM1_L_SFT, rt5677_pdm_src);
1427
1428static const struct snd_kcontrol_new rt5677_pdm1_l_mux =
1429 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_l_enum);
1430
1431static SOC_ENUM_SINGLE_DECL(
1432 rt5677_pdm2_l_enum, RT5677_PDM_OUT_CTRL,
1433 RT5677_SEL_PDM2_L_SFT, rt5677_pdm_src);
1434
1435static const struct snd_kcontrol_new rt5677_pdm2_l_mux =
1436 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_l_enum);
1437
1438static SOC_ENUM_SINGLE_DECL(
1439 rt5677_pdm1_r_enum, RT5677_PDM_OUT_CTRL,
1440 RT5677_SEL_PDM1_R_SFT, rt5677_pdm_src);
1441
1442static const struct snd_kcontrol_new rt5677_pdm1_r_mux =
1443 SOC_DAPM_ENUM("PDM1 source", rt5677_pdm1_r_enum);
1444
1445static SOC_ENUM_SINGLE_DECL(
1446 rt5677_pdm2_r_enum, RT5677_PDM_OUT_CTRL,
1447 RT5677_SEL_PDM2_R_SFT, rt5677_pdm_src);
1448
1449static const struct snd_kcontrol_new rt5677_pdm2_r_mux =
1450 SOC_DAPM_ENUM("PDM2 source", rt5677_pdm2_r_enum);
1451
1452/* TDM IF1/2 SLB ADC1 Data Selection */ /* MX-3C MX-41 [5:4] MX-08 [1:0]*/
1453static const char * const rt5677_if12_adc1_src[] = {
1454 "STO1 ADC MIX", "OB01", "VAD ADC"
1455};
1456
1457static SOC_ENUM_SINGLE_DECL(
1458 rt5677_if1_adc1_enum, RT5677_TDM1_CTRL2,
1459 RT5677_IF1_ADC1_SFT, rt5677_if12_adc1_src);
1460
1461static const struct snd_kcontrol_new rt5677_if1_adc1_mux =
1462 SOC_DAPM_ENUM("IF1 ADC1 source", rt5677_if1_adc1_enum);
1463
1464static SOC_ENUM_SINGLE_DECL(
1465 rt5677_if2_adc1_enum, RT5677_TDM2_CTRL2,
1466 RT5677_IF2_ADC1_SFT, rt5677_if12_adc1_src);
1467
1468static const struct snd_kcontrol_new rt5677_if2_adc1_mux =
1469 SOC_DAPM_ENUM("IF2 ADC1 source", rt5677_if2_adc1_enum);
1470
1471static SOC_ENUM_SINGLE_DECL(
1472 rt5677_slb_adc1_enum, RT5677_SLIMBUS_RX,
1473 RT5677_SLB_ADC1_SFT, rt5677_if12_adc1_src);
1474
1475static const struct snd_kcontrol_new rt5677_slb_adc1_mux =
1476 SOC_DAPM_ENUM("SLB ADC1 source", rt5677_slb_adc1_enum);
1477
1478/* TDM IF1/2 SLB ADC2 Data Selection */ /* MX-3C MX-41 [7:6] MX-08 [3:2] */
1479static const char * const rt5677_if12_adc2_src[] = {
1480 "STO2 ADC MIX", "OB23"
1481};
1482
1483static SOC_ENUM_SINGLE_DECL(
1484 rt5677_if1_adc2_enum, RT5677_TDM1_CTRL2,
1485 RT5677_IF1_ADC2_SFT, rt5677_if12_adc2_src);
1486
1487static const struct snd_kcontrol_new rt5677_if1_adc2_mux =
1488 SOC_DAPM_ENUM("IF1 ADC2 source", rt5677_if1_adc2_enum);
1489
1490static SOC_ENUM_SINGLE_DECL(
1491 rt5677_if2_adc2_enum, RT5677_TDM2_CTRL2,
1492 RT5677_IF2_ADC2_SFT, rt5677_if12_adc2_src);
1493
1494static const struct snd_kcontrol_new rt5677_if2_adc2_mux =
1495 SOC_DAPM_ENUM("IF2 ADC2 source", rt5677_if2_adc2_enum);
1496
1497static SOC_ENUM_SINGLE_DECL(
1498 rt5677_slb_adc2_enum, RT5677_SLIMBUS_RX,
1499 RT5677_SLB_ADC2_SFT, rt5677_if12_adc2_src);
1500
1501static const struct snd_kcontrol_new rt5677_slb_adc2_mux =
1502 SOC_DAPM_ENUM("SLB ADC2 source", rt5677_slb_adc2_enum);
1503
1504/* TDM IF1/2 SLB ADC3 Data Selection */ /* MX-3C MX-41 [9:8] MX-08 [5:4] */
1505static const char * const rt5677_if12_adc3_src[] = {
1506 "STO3 ADC MIX", "MONO ADC MIX", "OB45"
1507};
1508
1509static SOC_ENUM_SINGLE_DECL(
1510 rt5677_if1_adc3_enum, RT5677_TDM1_CTRL2,
1511 RT5677_IF1_ADC3_SFT, rt5677_if12_adc3_src);
1512
1513static const struct snd_kcontrol_new rt5677_if1_adc3_mux =
1514 SOC_DAPM_ENUM("IF1 ADC3 source", rt5677_if1_adc3_enum);
1515
1516static SOC_ENUM_SINGLE_DECL(
1517 rt5677_if2_adc3_enum, RT5677_TDM2_CTRL2,
1518 RT5677_IF2_ADC3_SFT, rt5677_if12_adc3_src);
1519
1520static const struct snd_kcontrol_new rt5677_if2_adc3_mux =
1521 SOC_DAPM_ENUM("IF2 ADC3 source", rt5677_if2_adc3_enum);
1522
1523static SOC_ENUM_SINGLE_DECL(
1524 rt5677_slb_adc3_enum, RT5677_SLIMBUS_RX,
1525 RT5677_SLB_ADC3_SFT, rt5677_if12_adc3_src);
1526
1527static const struct snd_kcontrol_new rt5677_slb_adc3_mux =
1528 SOC_DAPM_ENUM("SLB ADC3 source", rt5677_slb_adc3_enum);
1529
1530/* TDM IF1/2 SLB ADC4 Data Selection */ /* MX-3C MX-41 [11:10] MX-08 [7:6] */
1531static const char * const rt5677_if12_adc4_src[] = {
1532 "STO4 ADC MIX", "OB67", "OB01"
1533};
1534
1535static SOC_ENUM_SINGLE_DECL(
1536 rt5677_if1_adc4_enum, RT5677_TDM1_CTRL2,
1537 RT5677_IF1_ADC4_SFT, rt5677_if12_adc4_src);
1538
1539static const struct snd_kcontrol_new rt5677_if1_adc4_mux =
1540 SOC_DAPM_ENUM("IF1 ADC4 source", rt5677_if1_adc4_enum);
1541
1542static SOC_ENUM_SINGLE_DECL(
1543 rt5677_if2_adc4_enum, RT5677_TDM2_CTRL2,
1544 RT5677_IF2_ADC4_SFT, rt5677_if12_adc4_src);
1545
1546static const struct snd_kcontrol_new rt5677_if2_adc4_mux =
1547 SOC_DAPM_ENUM("IF2 ADC4 source", rt5677_if2_adc4_enum);
1548
1549static SOC_ENUM_SINGLE_DECL(
1550 rt5677_slb_adc4_enum, RT5677_SLIMBUS_RX,
1551 RT5677_SLB_ADC4_SFT, rt5677_if12_adc4_src);
1552
1553static const struct snd_kcontrol_new rt5677_slb_adc4_mux =
1554 SOC_DAPM_ENUM("SLB ADC4 source", rt5677_slb_adc4_enum);
1555
1556/* Interface3/4 ADC Data Input */ /* MX-2F [3:0] MX-30 [7:4]*/
1557static const char * const rt5677_if34_adc_src[] = {
1558 "STO1 ADC MIX", "STO2 ADC MIX", "STO3 ADC MIX", "STO4 ADC MIX",
1559 "MONO ADC MIX", "OB01", "OB23", "VAD ADC"
1560};
1561
1562static SOC_ENUM_SINGLE_DECL(
1563 rt5677_if3_adc_enum, RT5677_IF3_DATA,
1564 RT5677_IF3_ADC_IN_SFT, rt5677_if34_adc_src);
1565
1566static const struct snd_kcontrol_new rt5677_if3_adc_mux =
1567 SOC_DAPM_ENUM("IF3 ADC source", rt5677_if3_adc_enum);
1568
1569static SOC_ENUM_SINGLE_DECL(
1570 rt5677_if4_adc_enum, RT5677_IF4_DATA,
1571 RT5677_IF4_ADC_IN_SFT, rt5677_if34_adc_src);
1572
1573static const struct snd_kcontrol_new rt5677_if4_adc_mux =
1574 SOC_DAPM_ENUM("IF4 ADC source", rt5677_if4_adc_enum);
1575
1576static int rt5677_bst1_event(struct snd_soc_dapm_widget *w,
1577 struct snd_kcontrol *kcontrol, int event)
1578{
1579 struct snd_soc_codec *codec = w->codec;
1580 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1581
1582 switch (event) {
1583 case SND_SOC_DAPM_POST_PMU:
1584 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1585 RT5677_PWR_BST1_P, RT5677_PWR_BST1_P);
1586 break;
1587
1588 case SND_SOC_DAPM_PRE_PMD:
1589 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1590 RT5677_PWR_BST1_P, 0);
1591 break;
1592
1593 default:
1594 return 0;
1595 }
1596
1597 return 0;
1598}
1599
1600static int rt5677_bst2_event(struct snd_soc_dapm_widget *w,
1601 struct snd_kcontrol *kcontrol, int event)
1602{
1603 struct snd_soc_codec *codec = w->codec;
1604 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1605
1606 switch (event) {
1607 case SND_SOC_DAPM_POST_PMU:
1608 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1609 RT5677_PWR_BST2_P, RT5677_PWR_BST2_P);
1610 break;
1611
1612 case SND_SOC_DAPM_PRE_PMD:
1613 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1614 RT5677_PWR_BST2_P, 0);
1615 break;
1616
1617 default:
1618 return 0;
1619 }
1620
1621 return 0;
1622}
1623
1624static int rt5677_set_pll1_event(struct snd_soc_dapm_widget *w,
1625 struct snd_kcontrol *kcontrol, int event)
1626{
1627 struct snd_soc_codec *codec = w->codec;
1628 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1629
1630 switch (event) {
1631 case SND_SOC_DAPM_POST_PMU:
1632 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x2);
1633 regmap_update_bits(rt5677->regmap, RT5677_PLL1_CTRL2, 0x2, 0x0);
1634 break;
1635 default:
1636 return 0;
1637 }
1638
1639 return 0;
1640}
1641
1642static int rt5677_set_pll2_event(struct snd_soc_dapm_widget *w,
1643 struct snd_kcontrol *kcontrol, int event)
1644{
1645 struct snd_soc_codec *codec = w->codec;
1646 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1647
1648 switch (event) {
1649 case SND_SOC_DAPM_POST_PMU:
1650 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x2);
1651 regmap_update_bits(rt5677->regmap, RT5677_PLL2_CTRL2, 0x2, 0x0);
1652 break;
1653 default:
1654 return 0;
1655 }
1656
1657 return 0;
1658}
1659
1660static int rt5677_set_micbias1_event(struct snd_soc_dapm_widget *w,
1661 struct snd_kcontrol *kcontrol, int event)
1662{
1663 struct snd_soc_codec *codec = w->codec;
1664 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
1665
1666 switch (event) {
1667 case SND_SOC_DAPM_POST_PMU:
1668 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
1669 RT5677_PWR_CLK_MB1 | RT5677_PWR_PP_MB1 |
1670 RT5677_PWR_CLK_MB, RT5677_PWR_CLK_MB1 |
1671 RT5677_PWR_PP_MB1 | RT5677_PWR_CLK_MB);
1672 break;
1673 default:
1674 return 0;
1675 }
1676
1677 return 0;
1678}
1679
1680static const struct snd_soc_dapm_widget rt5677_dapm_widgets[] = {
1681 SND_SOC_DAPM_SUPPLY("PLL1", RT5677_PWR_ANLG2, RT5677_PWR_PLL1_BIT,
1682 0, rt5677_set_pll1_event, SND_SOC_DAPM_POST_PMU),
1683 SND_SOC_DAPM_SUPPLY("PLL2", RT5677_PWR_ANLG2, RT5677_PWR_PLL2_BIT,
1684 0, rt5677_set_pll2_event, SND_SOC_DAPM_POST_PMU),
1685
1686 /* Input Side */
1687 /* micbias */
1688 SND_SOC_DAPM_SUPPLY("micbias1", RT5677_PWR_ANLG2, RT5677_PWR_MB1_BIT,
1689 0, rt5677_set_micbias1_event, SND_SOC_DAPM_POST_PMU),
1690
1691 /* Input Lines */
1692 SND_SOC_DAPM_INPUT("DMIC L1"),
1693 SND_SOC_DAPM_INPUT("DMIC R1"),
1694 SND_SOC_DAPM_INPUT("DMIC L2"),
1695 SND_SOC_DAPM_INPUT("DMIC R2"),
1696 SND_SOC_DAPM_INPUT("DMIC L3"),
1697 SND_SOC_DAPM_INPUT("DMIC R3"),
1698 SND_SOC_DAPM_INPUT("DMIC L4"),
1699 SND_SOC_DAPM_INPUT("DMIC R4"),
1700
1701 SND_SOC_DAPM_INPUT("IN1P"),
1702 SND_SOC_DAPM_INPUT("IN1N"),
1703 SND_SOC_DAPM_INPUT("IN2P"),
1704 SND_SOC_DAPM_INPUT("IN2N"),
1705
1706 SND_SOC_DAPM_INPUT("Haptic Generator"),
1707
1708 SND_SOC_DAPM_PGA("DMIC1", RT5677_DMIC_CTRL1, RT5677_DMIC_1_EN_SFT, 0,
1709 NULL, 0),
1710 SND_SOC_DAPM_PGA("DMIC2", RT5677_DMIC_CTRL1, RT5677_DMIC_2_EN_SFT, 0,
1711 NULL, 0),
1712 SND_SOC_DAPM_PGA("DMIC3", RT5677_DMIC_CTRL1, RT5677_DMIC_3_EN_SFT, 0,
1713 NULL, 0),
1714 SND_SOC_DAPM_PGA("DMIC4", RT5677_DMIC_CTRL2, RT5677_DMIC_4_EN_SFT, 0,
1715 NULL, 0),
1716
1717 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1718 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1719
1720 /* Boost */
1721 SND_SOC_DAPM_PGA_E("BST1", RT5677_PWR_ANLG2,
1722 RT5677_PWR_BST1_BIT, 0, NULL, 0, rt5677_bst1_event,
1723 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1724 SND_SOC_DAPM_PGA_E("BST2", RT5677_PWR_ANLG2,
1725 RT5677_PWR_BST2_BIT, 0, NULL, 0, rt5677_bst2_event,
1726 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1727
1728 /* ADCs */
1729 SND_SOC_DAPM_ADC("ADC 1", NULL, SND_SOC_NOPM,
1730 0, 0),
1731 SND_SOC_DAPM_ADC("ADC 2", NULL, SND_SOC_NOPM,
1732 0, 0),
1733 SND_SOC_DAPM_PGA("ADC 1_2", SND_SOC_NOPM, 0, 0, NULL, 0),
1734
1735 SND_SOC_DAPM_SUPPLY("ADC 1 power", RT5677_PWR_DIG1,
1736 RT5677_PWR_ADC_L_BIT, 0, NULL, 0),
1737 SND_SOC_DAPM_SUPPLY("ADC 2 power", RT5677_PWR_DIG1,
1738 RT5677_PWR_ADC_R_BIT, 0, NULL, 0),
1739 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5677_PWR_DIG1,
1740 RT5677_PWR_ADCFED1_BIT, 0, NULL, 0),
1741 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5677_PWR_DIG1,
1742 RT5677_PWR_ADCFED2_BIT, 0, NULL, 0),
1743
1744 /* ADC Mux */
1745 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1746 &rt5677_sto1_dmic_mux),
1747 SND_SOC_DAPM_MUX("Stereo1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1748 &rt5677_sto1_adc1_mux),
1749 SND_SOC_DAPM_MUX("Stereo1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1750 &rt5677_sto1_adc2_mux),
1751 SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
1752 &rt5677_sto2_dmic_mux),
1753 SND_SOC_DAPM_MUX("Stereo2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1754 &rt5677_sto2_adc1_mux),
1755 SND_SOC_DAPM_MUX("Stereo2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1756 &rt5677_sto2_adc2_mux),
1757 SND_SOC_DAPM_MUX("Stereo2 ADC LR Mux", SND_SOC_NOPM, 0, 0,
1758 &rt5677_sto2_adc_lr_mux),
1759 SND_SOC_DAPM_MUX("Stereo3 DMIC Mux", SND_SOC_NOPM, 0, 0,
1760 &rt5677_sto3_dmic_mux),
1761 SND_SOC_DAPM_MUX("Stereo3 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1762 &rt5677_sto3_adc1_mux),
1763 SND_SOC_DAPM_MUX("Stereo3 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1764 &rt5677_sto3_adc2_mux),
1765 SND_SOC_DAPM_MUX("Stereo4 DMIC Mux", SND_SOC_NOPM, 0, 0,
1766 &rt5677_sto4_dmic_mux),
1767 SND_SOC_DAPM_MUX("Stereo4 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1768 &rt5677_sto4_adc1_mux),
1769 SND_SOC_DAPM_MUX("Stereo4 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1770 &rt5677_sto4_adc2_mux),
1771 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1772 &rt5677_mono_dmic_l_mux),
1773 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1774 &rt5677_mono_dmic_r_mux),
1775 SND_SOC_DAPM_MUX("Mono ADC2 L Mux", SND_SOC_NOPM, 0, 0,
1776 &rt5677_mono_adc2_l_mux),
1777 SND_SOC_DAPM_MUX("Mono ADC1 L Mux", SND_SOC_NOPM, 0, 0,
1778 &rt5677_mono_adc1_l_mux),
1779 SND_SOC_DAPM_MUX("Mono ADC1 R Mux", SND_SOC_NOPM, 0, 0,
1780 &rt5677_mono_adc1_r_mux),
1781 SND_SOC_DAPM_MUX("Mono ADC2 R Mux", SND_SOC_NOPM, 0, 0,
1782 &rt5677_mono_adc2_r_mux),
1783
1784 /* ADC Mixer */
1785 SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5677_PWR_DIG2,
1786 RT5677_PWR_ADC_S1F_BIT, 0, NULL, 0),
1787 SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5677_PWR_DIG2,
1788 RT5677_PWR_ADC_S2F_BIT, 0, NULL, 0),
1789 SND_SOC_DAPM_SUPPLY("adc stereo3 filter", RT5677_PWR_DIG2,
1790 RT5677_PWR_ADC_S3F_BIT, 0, NULL, 0),
1791 SND_SOC_DAPM_SUPPLY("adc stereo4 filter", RT5677_PWR_DIG2,
1792 RT5677_PWR_ADC_S4F_BIT, 0, NULL, 0),
1793 SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1794 rt5677_sto1_adc_l_mix, ARRAY_SIZE(rt5677_sto1_adc_l_mix)),
1795 SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1796 rt5677_sto1_adc_r_mix, ARRAY_SIZE(rt5677_sto1_adc_r_mix)),
1797 SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
1798 rt5677_sto2_adc_l_mix, ARRAY_SIZE(rt5677_sto2_adc_l_mix)),
1799 SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
1800 rt5677_sto2_adc_r_mix, ARRAY_SIZE(rt5677_sto2_adc_r_mix)),
1801 SND_SOC_DAPM_MIXER("Sto3 ADC MIXL", SND_SOC_NOPM, 0, 0,
1802 rt5677_sto3_adc_l_mix, ARRAY_SIZE(rt5677_sto3_adc_l_mix)),
1803 SND_SOC_DAPM_MIXER("Sto3 ADC MIXR", SND_SOC_NOPM, 0, 0,
1804 rt5677_sto3_adc_r_mix, ARRAY_SIZE(rt5677_sto3_adc_r_mix)),
1805 SND_SOC_DAPM_MIXER("Sto4 ADC MIXL", SND_SOC_NOPM, 0, 0,
1806 rt5677_sto4_adc_l_mix, ARRAY_SIZE(rt5677_sto4_adc_l_mix)),
1807 SND_SOC_DAPM_MIXER("Sto4 ADC MIXR", SND_SOC_NOPM, 0, 0,
1808 rt5677_sto4_adc_r_mix, ARRAY_SIZE(rt5677_sto4_adc_r_mix)),
1809 SND_SOC_DAPM_SUPPLY("adc mono left filter", RT5677_PWR_DIG2,
1810 RT5677_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1811 SND_SOC_DAPM_MIXER("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1812 rt5677_mono_adc_l_mix, ARRAY_SIZE(rt5677_mono_adc_l_mix)),
1813 SND_SOC_DAPM_SUPPLY("adc mono right filter", RT5677_PWR_DIG2,
1814 RT5677_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1815 SND_SOC_DAPM_MIXER("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1816 rt5677_mono_adc_r_mix, ARRAY_SIZE(rt5677_mono_adc_r_mix)),
1817
1818 /* ADC PGA */
1819 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1820 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1821 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1822 SND_SOC_DAPM_PGA("Stereo2 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1823 SND_SOC_DAPM_PGA("Stereo2 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1824 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1825 SND_SOC_DAPM_PGA("Stereo3 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1826 SND_SOC_DAPM_PGA("Stereo3 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1827 SND_SOC_DAPM_PGA("Stereo3 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1828 SND_SOC_DAPM_PGA("Stereo4 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1829 SND_SOC_DAPM_PGA("Stereo4 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1830 SND_SOC_DAPM_PGA("Stereo4 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1831 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1832 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1833 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1834 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1835 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1836 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1837
1838 /* DSP */
1839 SND_SOC_DAPM_MUX("IB9 Mux", SND_SOC_NOPM, 0, 0,
1840 &rt5677_ib9_src_mux),
1841 SND_SOC_DAPM_MUX("IB8 Mux", SND_SOC_NOPM, 0, 0,
1842 &rt5677_ib8_src_mux),
1843 SND_SOC_DAPM_MUX("IB7 Mux", SND_SOC_NOPM, 0, 0,
1844 &rt5677_ib7_src_mux),
1845 SND_SOC_DAPM_MUX("IB6 Mux", SND_SOC_NOPM, 0, 0,
1846 &rt5677_ib6_src_mux),
1847 SND_SOC_DAPM_MUX("IB45 Mux", SND_SOC_NOPM, 0, 0,
1848 &rt5677_ib45_src_mux),
1849 SND_SOC_DAPM_MUX("IB23 Mux", SND_SOC_NOPM, 0, 0,
1850 &rt5677_ib23_src_mux),
1851 SND_SOC_DAPM_MUX("IB01 Mux", SND_SOC_NOPM, 0, 0,
1852 &rt5677_ib01_src_mux),
1853 SND_SOC_DAPM_MUX("IB45 Bypass Mux", SND_SOC_NOPM, 0, 0,
1854 &rt5677_ib45_bypass_src_mux),
1855 SND_SOC_DAPM_MUX("IB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1856 &rt5677_ib23_bypass_src_mux),
1857 SND_SOC_DAPM_MUX("IB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1858 &rt5677_ib01_bypass_src_mux),
1859 SND_SOC_DAPM_MUX("OB23 Bypass Mux", SND_SOC_NOPM, 0, 0,
1860 &rt5677_ob23_bypass_src_mux),
1861 SND_SOC_DAPM_MUX("OB01 Bypass Mux", SND_SOC_NOPM, 0, 0,
1862 &rt5677_ob01_bypass_src_mux),
1863
1864 SND_SOC_DAPM_PGA("OB45", SND_SOC_NOPM, 0, 0, NULL, 0),
1865 SND_SOC_DAPM_PGA("OB67", SND_SOC_NOPM, 0, 0, NULL, 0),
1866
1867 SND_SOC_DAPM_PGA("OutBound2", SND_SOC_NOPM, 0, 0, NULL, 0),
1868 SND_SOC_DAPM_PGA("OutBound3", SND_SOC_NOPM, 0, 0, NULL, 0),
1869 SND_SOC_DAPM_PGA("OutBound4", SND_SOC_NOPM, 0, 0, NULL, 0),
1870 SND_SOC_DAPM_PGA("OutBound5", SND_SOC_NOPM, 0, 0, NULL, 0),
1871 SND_SOC_DAPM_PGA("OutBound6", SND_SOC_NOPM, 0, 0, NULL, 0),
1872 SND_SOC_DAPM_PGA("OutBound7", SND_SOC_NOPM, 0, 0, NULL, 0),
1873
1874 /* Digital Interface */
1875 SND_SOC_DAPM_SUPPLY("I2S1", RT5677_PWR_DIG1,
1876 RT5677_PWR_I2S1_BIT, 0, NULL, 0),
1877 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1878 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1879 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1880 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1881 SND_SOC_DAPM_PGA("IF1 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1882 SND_SOC_DAPM_PGA("IF1 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1883 SND_SOC_DAPM_PGA("IF1 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1884 SND_SOC_DAPM_PGA("IF1 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1885 SND_SOC_DAPM_PGA("IF1 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1886 SND_SOC_DAPM_PGA("IF1 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1887 SND_SOC_DAPM_PGA("IF1 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1888 SND_SOC_DAPM_PGA("IF1 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1889 SND_SOC_DAPM_PGA("IF1 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1890 SND_SOC_DAPM_PGA("IF1 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1891 SND_SOC_DAPM_PGA("IF1 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1892 SND_SOC_DAPM_PGA("IF1 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1893
1894 SND_SOC_DAPM_SUPPLY("I2S2", RT5677_PWR_DIG1,
1895 RT5677_PWR_I2S2_BIT, 0, NULL, 0),
1896 SND_SOC_DAPM_PGA("IF2 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1897 SND_SOC_DAPM_PGA("IF2 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1898 SND_SOC_DAPM_PGA("IF2 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1899 SND_SOC_DAPM_PGA("IF2 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1900 SND_SOC_DAPM_PGA("IF2 DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1901 SND_SOC_DAPM_PGA("IF2 DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1902 SND_SOC_DAPM_PGA("IF2 DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1903 SND_SOC_DAPM_PGA("IF2 DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1904 SND_SOC_DAPM_PGA("IF2 DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1905 SND_SOC_DAPM_PGA("IF2 DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1906 SND_SOC_DAPM_PGA("IF2 DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1907 SND_SOC_DAPM_PGA("IF2 DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1908 SND_SOC_DAPM_PGA("IF2 ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1909 SND_SOC_DAPM_PGA("IF2 ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1910 SND_SOC_DAPM_PGA("IF2 ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1911 SND_SOC_DAPM_PGA("IF2 ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1912
1913 SND_SOC_DAPM_SUPPLY("I2S3", RT5677_PWR_DIG1,
1914 RT5677_PWR_I2S3_BIT, 0, NULL, 0),
1915 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1916 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1917 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1918 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1919 SND_SOC_DAPM_PGA("IF3 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1920 SND_SOC_DAPM_PGA("IF3 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1921
1922 SND_SOC_DAPM_SUPPLY("I2S4", RT5677_PWR_DIG1,
1923 RT5677_PWR_I2S4_BIT, 0, NULL, 0),
1924 SND_SOC_DAPM_PGA("IF4 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1925 SND_SOC_DAPM_PGA("IF4 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1926 SND_SOC_DAPM_PGA("IF4 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1927 SND_SOC_DAPM_PGA("IF4 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1928 SND_SOC_DAPM_PGA("IF4 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1929 SND_SOC_DAPM_PGA("IF4 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1930
1931 SND_SOC_DAPM_SUPPLY("SLB", RT5677_PWR_DIG1,
1932 RT5677_PWR_SLB_BIT, 0, NULL, 0),
1933 SND_SOC_DAPM_PGA("SLB DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
1934 SND_SOC_DAPM_PGA("SLB DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1935 SND_SOC_DAPM_PGA("SLB DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1936 SND_SOC_DAPM_PGA("SLB DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1937 SND_SOC_DAPM_PGA("SLB DAC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1938 SND_SOC_DAPM_PGA("SLB DAC5", SND_SOC_NOPM, 0, 0, NULL, 0),
1939 SND_SOC_DAPM_PGA("SLB DAC6", SND_SOC_NOPM, 0, 0, NULL, 0),
1940 SND_SOC_DAPM_PGA("SLB DAC7", SND_SOC_NOPM, 0, 0, NULL, 0),
1941 SND_SOC_DAPM_PGA("SLB DAC01", SND_SOC_NOPM, 0, 0, NULL, 0),
1942 SND_SOC_DAPM_PGA("SLB DAC23", SND_SOC_NOPM, 0, 0, NULL, 0),
1943 SND_SOC_DAPM_PGA("SLB DAC45", SND_SOC_NOPM, 0, 0, NULL, 0),
1944 SND_SOC_DAPM_PGA("SLB DAC67", SND_SOC_NOPM, 0, 0, NULL, 0),
1945 SND_SOC_DAPM_PGA("SLB ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1946 SND_SOC_DAPM_PGA("SLB ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1947 SND_SOC_DAPM_PGA("SLB ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1948 SND_SOC_DAPM_PGA("SLB ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1949
1950 /* Digital Interface Select */
1951 SND_SOC_DAPM_MUX("IF1 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1952 &rt5677_if1_adc1_mux),
1953 SND_SOC_DAPM_MUX("IF1 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1954 &rt5677_if1_adc2_mux),
1955 SND_SOC_DAPM_MUX("IF1 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1956 &rt5677_if1_adc3_mux),
1957 SND_SOC_DAPM_MUX("IF1 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1958 &rt5677_if1_adc4_mux),
1959 SND_SOC_DAPM_MUX("IF2 ADC1 Mux", SND_SOC_NOPM, 0, 0,
1960 &rt5677_if2_adc1_mux),
1961 SND_SOC_DAPM_MUX("IF2 ADC2 Mux", SND_SOC_NOPM, 0, 0,
1962 &rt5677_if2_adc2_mux),
1963 SND_SOC_DAPM_MUX("IF2 ADC3 Mux", SND_SOC_NOPM, 0, 0,
1964 &rt5677_if2_adc3_mux),
1965 SND_SOC_DAPM_MUX("IF2 ADC4 Mux", SND_SOC_NOPM, 0, 0,
1966 &rt5677_if2_adc4_mux),
1967 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
1968 &rt5677_if3_adc_mux),
1969 SND_SOC_DAPM_MUX("IF4 ADC Mux", SND_SOC_NOPM, 0, 0,
1970 &rt5677_if4_adc_mux),
1971 SND_SOC_DAPM_MUX("SLB ADC1 Mux", SND_SOC_NOPM, 0, 0,
1972 &rt5677_slb_adc1_mux),
1973 SND_SOC_DAPM_MUX("SLB ADC2 Mux", SND_SOC_NOPM, 0, 0,
1974 &rt5677_slb_adc2_mux),
1975 SND_SOC_DAPM_MUX("SLB ADC3 Mux", SND_SOC_NOPM, 0, 0,
1976 &rt5677_slb_adc3_mux),
1977 SND_SOC_DAPM_MUX("SLB ADC4 Mux", SND_SOC_NOPM, 0, 0,
1978 &rt5677_slb_adc4_mux),
1979
1980 /* Audio Interface */
1981 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1982 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1983 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1984 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1985 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1986 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1987 SND_SOC_DAPM_AIF_IN("AIF4RX", "AIF4 Playback", 0, SND_SOC_NOPM, 0, 0),
1988 SND_SOC_DAPM_AIF_OUT("AIF4TX", "AIF4 Capture", 0, SND_SOC_NOPM, 0, 0),
1989 SND_SOC_DAPM_AIF_IN("SLBRX", "SLIMBus Playback", 0, SND_SOC_NOPM, 0, 0),
1990 SND_SOC_DAPM_AIF_OUT("SLBTX", "SLIMBus Capture", 0, SND_SOC_NOPM, 0, 0),
1991
1992 /* Sidetone Mux */
1993 SND_SOC_DAPM_MUX("Sidetone Mux", SND_SOC_NOPM, 0, 0,
1994 &rt5677_sidetone_mux),
1995 /* VAD Mux*/
1996 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM, 0, 0,
1997 &rt5677_vad_src_mux),
1998
1999 /* Tensilica DSP */
2000 SND_SOC_DAPM_PGA("Tensilica DSP", SND_SOC_NOPM, 0, 0, NULL, 0),
2001 SND_SOC_DAPM_MIXER("OB01 MIX", SND_SOC_NOPM, 0, 0,
2002 rt5677_ob_01_mix, ARRAY_SIZE(rt5677_ob_01_mix)),
2003 SND_SOC_DAPM_MIXER("OB23 MIX", SND_SOC_NOPM, 0, 0,
2004 rt5677_ob_23_mix, ARRAY_SIZE(rt5677_ob_23_mix)),
2005 SND_SOC_DAPM_MIXER("OB4 MIX", SND_SOC_NOPM, 0, 0,
2006 rt5677_ob_4_mix, ARRAY_SIZE(rt5677_ob_4_mix)),
2007 SND_SOC_DAPM_MIXER("OB5 MIX", SND_SOC_NOPM, 0, 0,
2008 rt5677_ob_5_mix, ARRAY_SIZE(rt5677_ob_5_mix)),
2009 SND_SOC_DAPM_MIXER("OB6 MIX", SND_SOC_NOPM, 0, 0,
2010 rt5677_ob_6_mix, ARRAY_SIZE(rt5677_ob_6_mix)),
2011 SND_SOC_DAPM_MIXER("OB7 MIX", SND_SOC_NOPM, 0, 0,
2012 rt5677_ob_7_mix, ARRAY_SIZE(rt5677_ob_7_mix)),
2013
2014 /* Output Side */
2015 /* DAC mixer before sound effect */
2016 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2017 rt5677_dac_l_mix, ARRAY_SIZE(rt5677_dac_l_mix)),
2018 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2019 rt5677_dac_r_mix, ARRAY_SIZE(rt5677_dac_r_mix)),
2020 SND_SOC_DAPM_PGA("DAC1 FS", SND_SOC_NOPM, 0, 0, NULL, 0),
2021
2022 /* DAC Mux */
2023 SND_SOC_DAPM_MUX("DAC1 Mux", SND_SOC_NOPM, 0, 0,
2024 &rt5677_dac1_mux),
2025 SND_SOC_DAPM_MUX("ADDA1 Mux", SND_SOC_NOPM, 0, 0,
2026 &rt5677_adda1_mux),
2027 SND_SOC_DAPM_MUX("DAC12 SRC Mux", SND_SOC_NOPM, 0, 0,
2028 &rt5677_dac12_mux),
2029 SND_SOC_DAPM_MUX("DAC3 SRC Mux", SND_SOC_NOPM, 0, 0,
2030 &rt5677_dac3_mux),
2031
2032 /* DAC2 channel Mux */
2033 SND_SOC_DAPM_MUX("DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2034 &rt5677_dac2_l_mux),
2035 SND_SOC_DAPM_MUX("DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2036 &rt5677_dac2_r_mux),
2037
2038 /* DAC3 channel Mux */
2039 SND_SOC_DAPM_MUX("DAC3 L Mux", SND_SOC_NOPM, 0, 0,
2040 &rt5677_dac3_l_mux),
2041 SND_SOC_DAPM_MUX("DAC3 R Mux", SND_SOC_NOPM, 0, 0,
2042 &rt5677_dac3_r_mux),
2043
2044 /* DAC4 channel Mux */
2045 SND_SOC_DAPM_MUX("DAC4 L Mux", SND_SOC_NOPM, 0, 0,
2046 &rt5677_dac4_l_mux),
2047 SND_SOC_DAPM_MUX("DAC4 R Mux", SND_SOC_NOPM, 0, 0,
2048 &rt5677_dac4_r_mux),
2049
2050 /* DAC Mixer */
2051 SND_SOC_DAPM_SUPPLY("dac stereo1 filter", RT5677_PWR_DIG2,
2052 RT5677_PWR_DAC_S1F_BIT, 0, NULL, 0),
2053 SND_SOC_DAPM_SUPPLY("dac mono left filter", RT5677_PWR_DIG2,
2054 RT5677_PWR_DAC_M2F_L_BIT, 0, NULL, 0),
2055 SND_SOC_DAPM_SUPPLY("dac mono right filter", RT5677_PWR_DIG2,
2056 RT5677_PWR_DAC_M2F_R_BIT, 0, NULL, 0),
2057
2058 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2059 rt5677_sto1_dac_l_mix, ARRAY_SIZE(rt5677_sto1_dac_l_mix)),
2060 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2061 rt5677_sto1_dac_r_mix, ARRAY_SIZE(rt5677_sto1_dac_r_mix)),
2062 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2063 rt5677_mono_dac_l_mix, ARRAY_SIZE(rt5677_mono_dac_l_mix)),
2064 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2065 rt5677_mono_dac_r_mix, ARRAY_SIZE(rt5677_mono_dac_r_mix)),
2066 SND_SOC_DAPM_MIXER("DD1 MIXL", SND_SOC_NOPM, 0, 0,
2067 rt5677_dd1_l_mix, ARRAY_SIZE(rt5677_dd1_l_mix)),
2068 SND_SOC_DAPM_MIXER("DD1 MIXR", SND_SOC_NOPM, 0, 0,
2069 rt5677_dd1_r_mix, ARRAY_SIZE(rt5677_dd1_r_mix)),
2070 SND_SOC_DAPM_MIXER("DD2 MIXL", SND_SOC_NOPM, 0, 0,
2071 rt5677_dd2_l_mix, ARRAY_SIZE(rt5677_dd2_l_mix)),
2072 SND_SOC_DAPM_MIXER("DD2 MIXR", SND_SOC_NOPM, 0, 0,
2073 rt5677_dd2_r_mix, ARRAY_SIZE(rt5677_dd2_r_mix)),
2074 SND_SOC_DAPM_PGA("Stereo DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2075 SND_SOC_DAPM_PGA("Mono DAC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2076 SND_SOC_DAPM_PGA("DD1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2077 SND_SOC_DAPM_PGA("DD2 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2078
2079 /* DACs */
2080 SND_SOC_DAPM_DAC("DAC 1", NULL, RT5677_PWR_DIG1,
2081 RT5677_PWR_DAC1_BIT, 0),
2082 SND_SOC_DAPM_DAC("DAC 2", NULL, RT5677_PWR_DIG1,
2083 RT5677_PWR_DAC2_BIT, 0),
2084 SND_SOC_DAPM_DAC("DAC 3", NULL, RT5677_PWR_DIG1,
2085 RT5677_PWR_DAC3_BIT, 0),
2086
2087 /* PDM */
2088 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5677_PWR_DIG2,
2089 RT5677_PWR_PDM1_BIT, 0, NULL, 0),
2090 SND_SOC_DAPM_SUPPLY("PDM2 Power", RT5677_PWR_DIG2,
2091 RT5677_PWR_PDM2_BIT, 0, NULL, 0),
2092
2093 SND_SOC_DAPM_MUX("PDM1 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_L_SFT,
2094 1, &rt5677_pdm1_l_mux),
2095 SND_SOC_DAPM_MUX("PDM1 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM1_R_SFT,
2096 1, &rt5677_pdm1_r_mux),
2097 SND_SOC_DAPM_MUX("PDM2 L Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_L_SFT,
2098 1, &rt5677_pdm2_l_mux),
2099 SND_SOC_DAPM_MUX("PDM2 R Mux", RT5677_PDM_OUT_CTRL, RT5677_M_PDM2_R_SFT,
2100 1, &rt5677_pdm2_r_mux),
2101
2102 SND_SOC_DAPM_PGA_S("LOUT1 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO1_BIT,
2103 0, NULL, 0),
2104 SND_SOC_DAPM_PGA_S("LOUT2 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO2_BIT,
2105 0, NULL, 0),
2106 SND_SOC_DAPM_PGA_S("LOUT3 amp", 1, RT5677_PWR_ANLG1, RT5677_PWR_LO3_BIT,
2107 0, NULL, 0),
2108
2109 /* Output Lines */
2110 SND_SOC_DAPM_OUTPUT("LOUT1"),
2111 SND_SOC_DAPM_OUTPUT("LOUT2"),
2112 SND_SOC_DAPM_OUTPUT("LOUT3"),
2113 SND_SOC_DAPM_OUTPUT("PDM1L"),
2114 SND_SOC_DAPM_OUTPUT("PDM1R"),
2115 SND_SOC_DAPM_OUTPUT("PDM2L"),
2116 SND_SOC_DAPM_OUTPUT("PDM2R"),
2117};
2118
2119static const struct snd_soc_dapm_route rt5677_dapm_routes[] = {
2120 { "DMIC1", NULL, "DMIC L1" },
2121 { "DMIC1", NULL, "DMIC R1" },
2122 { "DMIC2", NULL, "DMIC L2" },
2123 { "DMIC2", NULL, "DMIC R2" },
2124 { "DMIC3", NULL, "DMIC L3" },
2125 { "DMIC3", NULL, "DMIC R3" },
2126 { "DMIC4", NULL, "DMIC L4" },
2127 { "DMIC4", NULL, "DMIC R4" },
2128
2129 { "DMIC L1", NULL, "DMIC CLK" },
2130 { "DMIC R1", NULL, "DMIC CLK" },
2131 { "DMIC L2", NULL, "DMIC CLK" },
2132 { "DMIC R2", NULL, "DMIC CLK" },
2133 { "DMIC L3", NULL, "DMIC CLK" },
2134 { "DMIC R3", NULL, "DMIC CLK" },
2135 { "DMIC L4", NULL, "DMIC CLK" },
2136 { "DMIC R4", NULL, "DMIC CLK" },
2137
2138 { "BST1", NULL, "IN1P" },
2139 { "BST1", NULL, "IN1N" },
2140 { "BST2", NULL, "IN2P" },
2141 { "BST2", NULL, "IN2N" },
2142
2143 { "IN1P", NULL, "micbias1" },
2144 { "IN1N", NULL, "micbias1" },
2145 { "IN2P", NULL, "micbias1" },
2146 { "IN2N", NULL, "micbias1" },
2147
2148 { "ADC 1", NULL, "BST1" },
2149 { "ADC 1", NULL, "ADC 1 power" },
2150 { "ADC 1", NULL, "ADC1 clock" },
2151 { "ADC 2", NULL, "BST2" },
2152 { "ADC 2", NULL, "ADC 2 power" },
2153 { "ADC 2", NULL, "ADC2 clock" },
2154
2155 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2156 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2157 { "Stereo1 DMIC Mux", "DMIC3", "DMIC3" },
2158 { "Stereo1 DMIC Mux", "DMIC4", "DMIC4" },
2159
2160 { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
2161 { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
2162 { "Stereo2 DMIC Mux", "DMIC3", "DMIC3" },
2163 { "Stereo2 DMIC Mux", "DMIC4", "DMIC4" },
2164
2165 { "Stereo3 DMIC Mux", "DMIC1", "DMIC1" },
2166 { "Stereo3 DMIC Mux", "DMIC2", "DMIC2" },
2167 { "Stereo3 DMIC Mux", "DMIC3", "DMIC3" },
2168 { "Stereo3 DMIC Mux", "DMIC4", "DMIC4" },
2169
2170 { "Stereo4 DMIC Mux", "DMIC1", "DMIC1" },
2171 { "Stereo4 DMIC Mux", "DMIC2", "DMIC2" },
2172 { "Stereo4 DMIC Mux", "DMIC3", "DMIC3" },
2173 { "Stereo4 DMIC Mux", "DMIC4", "DMIC4" },
2174
2175 { "Mono DMIC L Mux", "DMIC1", "DMIC1" },
2176 { "Mono DMIC L Mux", "DMIC2", "DMIC2" },
2177 { "Mono DMIC L Mux", "DMIC3", "DMIC3" },
2178 { "Mono DMIC L Mux", "DMIC4", "DMIC4" },
2179
2180 { "Mono DMIC R Mux", "DMIC1", "DMIC1" },
2181 { "Mono DMIC R Mux", "DMIC2", "DMIC2" },
2182 { "Mono DMIC R Mux", "DMIC3", "DMIC3" },
2183 { "Mono DMIC R Mux", "DMIC4", "DMIC4" },
2184
2185 { "ADC 1_2", NULL, "ADC 1" },
2186 { "ADC 1_2", NULL, "ADC 2" },
2187
2188 { "Stereo1 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2189 { "Stereo1 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2190 { "Stereo1 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2191
2192 { "Stereo1 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2193 { "Stereo1 ADC2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2194 { "Stereo1 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2195
2196 { "Stereo2 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2197 { "Stereo2 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2198 { "Stereo2 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2199
2200 { "Stereo2 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2201 { "Stereo2 ADC2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2202 { "Stereo2 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2203
2204 { "Stereo3 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2205 { "Stereo3 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2206 { "Stereo3 ADC1 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2207
2208 { "Stereo3 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2209 { "Stereo3 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2210 { "Stereo3 ADC2 Mux", "Stereo DAC MIX", "Stereo DAC MIX" },
2211
2212 { "Stereo4 ADC1 Mux", "DD MIX1", "DD1 MIX" },
2213 { "Stereo4 ADC1 Mux", "ADC1/2", "ADC 1_2" },
2214 { "Stereo4 ADC1 Mux", "DD MIX2", "DD2 MIX" },
2215
2216 { "Stereo4 ADC2 Mux", "DD MIX1", "DD1 MIX" },
2217 { "Stereo4 ADC2 Mux", "DMIC", "Stereo3 DMIC Mux" },
2218 { "Stereo4 ADC2 Mux", "DD MIX2", "DD2 MIX" },
2219
2220 { "Mono ADC2 L Mux", "DD MIX1L", "DD1 MIXL" },
2221 { "Mono ADC2 L Mux", "DMIC", "Mono DMIC L Mux" },
2222 { "Mono ADC2 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2223
2224 { "Mono ADC1 L Mux", "DD MIX1L", "DD1 MIXL" },
2225 { "Mono ADC1 L Mux", "ADC1", "ADC 1" },
2226 { "Mono ADC1 L Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2227
2228 { "Mono ADC1 R Mux", "DD MIX1R", "DD1 MIXR" },
2229 { "Mono ADC1 R Mux", "ADC2", "ADC 2" },
2230 { "Mono ADC1 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2231
2232 { "Mono ADC2 R Mux", "DD MIX1R", "DD1 MIXR" },
2233 { "Mono ADC2 R Mux", "DMIC", "Mono DMIC R Mux" },
2234 { "Mono ADC2 R Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2235
2236 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2237 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2238 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC1 Mux" },
2239 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC2 Mux" },
2240
2241 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2242 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2243 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2244
2245 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2246 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2247 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2248
2249 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
2250 { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
2251
2252 { "Sto2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2253 { "Sto2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2254 { "Sto2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC1 Mux" },
2255 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC2 Mux" },
2256
2257 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXL" },
2258 { "Sto2 ADC LR MIX", NULL, "Sto2 ADC MIXR" },
2259
2260 { "Stereo2 ADC LR Mux", "L", "Sto2 ADC MIXL" },
2261 { "Stereo2 ADC LR Mux", "LR", "Sto2 ADC LR MIX" },
2262
2263 { "Stereo2 ADC MIXL", NULL, "Stereo2 ADC LR Mux" },
2264 { "Stereo2 ADC MIXL", NULL, "adc stereo2 filter" },
2265 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2266
2267 { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
2268 { "Stereo2 ADC MIXR", NULL, "adc stereo2 filter" },
2269 { "adc stereo2 filter", NULL, "PLL1", is_sys_clk_from_pll },
2270
2271 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
2272 { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
2273
2274 { "Sto3 ADC MIXL", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2275 { "Sto3 ADC MIXL", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2276 { "Sto3 ADC MIXR", "ADC1 Switch", "Stereo3 ADC1 Mux" },
2277 { "Sto3 ADC MIXR", "ADC2 Switch", "Stereo3 ADC2 Mux" },
2278
2279 { "Stereo3 ADC MIXL", NULL, "Sto3 ADC MIXL" },
2280 { "Stereo3 ADC MIXL", NULL, "adc stereo3 filter" },
2281 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2282
2283 { "Stereo3 ADC MIXR", NULL, "Sto3 ADC MIXR" },
2284 { "Stereo3 ADC MIXR", NULL, "adc stereo3 filter" },
2285 { "adc stereo3 filter", NULL, "PLL1", is_sys_clk_from_pll },
2286
2287 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXL" },
2288 { "Stereo3 ADC MIX", NULL, "Stereo3 ADC MIXR" },
2289
2290 { "Sto4 ADC MIXL", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2291 { "Sto4 ADC MIXL", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2292 { "Sto4 ADC MIXR", "ADC1 Switch", "Stereo4 ADC1 Mux" },
2293 { "Sto4 ADC MIXR", "ADC2 Switch", "Stereo4 ADC2 Mux" },
2294
2295 { "Stereo4 ADC MIXL", NULL, "Sto4 ADC MIXL" },
2296 { "Stereo4 ADC MIXL", NULL, "adc stereo4 filter" },
2297 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2298
2299 { "Stereo4 ADC MIXR", NULL, "Sto4 ADC MIXR" },
2300 { "Stereo4 ADC MIXR", NULL, "adc stereo4 filter" },
2301 { "adc stereo4 filter", NULL, "PLL1", is_sys_clk_from_pll },
2302
2303 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXL" },
2304 { "Stereo4 ADC MIX", NULL, "Stereo4 ADC MIXR" },
2305
2306 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC1 L Mux" },
2307 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC2 L Mux" },
2308 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2309 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2310
2311 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC1 R Mux" },
2312 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC2 R Mux" },
2313 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2314 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2315
2316 { "Mono ADC MIX", NULL, "Mono ADC MIXL" },
2317 { "Mono ADC MIX", NULL, "Mono ADC MIXR" },
2318
2319 { "VAD ADC Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2320 { "VAD ADC Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2321 { "VAD ADC Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2322 { "VAD ADC Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2323 { "VAD ADC Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2324
2325 { "IF1 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2326 { "IF1 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2327 { "IF1 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2328
2329 { "IF1 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2330 { "IF1 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2331
2332 { "IF1 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2333 { "IF1 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2334 { "IF1 ADC3 Mux", "OB45", "OB45" },
2335
2336 { "IF1 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2337 { "IF1 ADC4 Mux", "OB67", "OB67" },
2338 { "IF1 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2339
2340 { "AIF1TX", NULL, "I2S1" },
2341 { "AIF1TX", NULL, "IF1 ADC1 Mux" },
2342 { "AIF1TX", NULL, "IF1 ADC2 Mux" },
2343 { "AIF1TX", NULL, "IF1 ADC3 Mux" },
2344 { "AIF1TX", NULL, "IF1 ADC4 Mux" },
2345
2346 { "IF2 ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2347 { "IF2 ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2348 { "IF2 ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2349
2350 { "IF2 ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2351 { "IF2 ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2352
2353 { "IF2 ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2354 { "IF2 ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2355 { "IF2 ADC3 Mux", "OB45", "OB45" },
2356
2357 { "IF2 ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2358 { "IF2 ADC4 Mux", "OB67", "OB67" },
2359 { "IF2 ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2360
2361 { "AIF2TX", NULL, "I2S2" },
2362 { "AIF2TX", NULL, "IF2 ADC1 Mux" },
2363 { "AIF2TX", NULL, "IF2 ADC2 Mux" },
2364 { "AIF2TX", NULL, "IF2 ADC3 Mux" },
2365 { "AIF2TX", NULL, "IF2 ADC4 Mux" },
2366
2367 { "IF3 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2368 { "IF3 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2369 { "IF3 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2370 { "IF3 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2371 { "IF3 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2372 { "IF3 ADC Mux", "OB01", "OB01 Bypass Mux" },
2373 { "IF3 ADC Mux", "OB23", "OB23 Bypass Mux" },
2374 { "IF3 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2375
2376 { "AIF3TX", NULL, "I2S3" },
2377 { "AIF3TX", NULL, "IF3 ADC Mux" },
2378
2379 { "IF4 ADC Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2380 { "IF4 ADC Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2381 { "IF4 ADC Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2382 { "IF4 ADC Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2383 { "IF4 ADC Mux", "MONO ADC MIX", "Mono ADC MIX" },
2384 { "IF4 ADC Mux", "OB01", "OB01 Bypass Mux" },
2385 { "IF4 ADC Mux", "OB23", "OB23 Bypass Mux" },
2386 { "IF4 ADC Mux", "VAD ADC", "VAD ADC Mux" },
2387
2388 { "AIF4TX", NULL, "I2S4" },
2389 { "AIF4TX", NULL, "IF4 ADC Mux" },
2390
2391 { "SLB ADC1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2392 { "SLB ADC1 Mux", "OB01", "OB01 Bypass Mux" },
2393 { "SLB ADC1 Mux", "VAD ADC", "VAD ADC Mux" },
2394
2395 { "SLB ADC2 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2396 { "SLB ADC2 Mux", "OB23", "OB23 Bypass Mux" },
2397
2398 { "SLB ADC3 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2399 { "SLB ADC3 Mux", "MONO ADC MIX", "Mono ADC MIX" },
2400 { "SLB ADC3 Mux", "OB45", "OB45" },
2401
2402 { "SLB ADC4 Mux", "STO4 ADC MIX", "Stereo4 ADC MIX" },
2403 { "SLB ADC4 Mux", "OB67", "OB67" },
2404 { "SLB ADC4 Mux", "OB01", "OB01 Bypass Mux" },
2405
2406 { "SLBTX", NULL, "SLB" },
2407 { "SLBTX", NULL, "SLB ADC1 Mux" },
2408 { "SLBTX", NULL, "SLB ADC2 Mux" },
2409 { "SLBTX", NULL, "SLB ADC3 Mux" },
2410 { "SLBTX", NULL, "SLB ADC4 Mux" },
2411
2412 { "IB01 Mux", "IF1 DAC 01", "IF1 DAC01" },
2413 { "IB01 Mux", "IF2 DAC 01", "IF2 DAC01" },
2414 { "IB01 Mux", "SLB DAC 01", "SLB DAC01" },
2415 { "IB01 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2416 { "IB01 Mux", "VAD ADC/DAC1 FS", "DAC1 FS" },
2417
2418 { "IB01 Bypass Mux", "Bypass", "IB01 Mux" },
2419 { "IB01 Bypass Mux", "Pass SRC", "IB01 Mux" },
2420
2421 { "IB23 Mux", "IF1 DAC 23", "IF1 DAC23" },
2422 { "IB23 Mux", "IF2 DAC 23", "IF2 DAC23" },
2423 { "IB23 Mux", "SLB DAC 23", "SLB DAC23" },
2424 { "IB23 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2425 { "IB23 Mux", "DAC1 FS", "DAC1 FS" },
2426 { "IB23 Mux", "IF4 DAC", "IF4 DAC" },
2427
2428 { "IB23 Bypass Mux", "Bypass", "IB23 Mux" },
2429 { "IB23 Bypass Mux", "Pass SRC", "IB23 Mux" },
2430
2431 { "IB45 Mux", "IF1 DAC 45", "IF1 DAC45" },
2432 { "IB45 Mux", "IF2 DAC 45", "IF2 DAC45" },
2433 { "IB45 Mux", "SLB DAC 45", "SLB DAC45" },
2434 { "IB45 Mux", "STO3 ADC MIX", "Stereo3 ADC MIX" },
2435 { "IB45 Mux", "IF3 DAC", "IF3 DAC" },
2436
2437 { "IB45 Bypass Mux", "Bypass", "IB45 Mux" },
2438 { "IB45 Bypass Mux", "Pass SRC", "IB45 Mux" },
2439
2440 { "IB6 Mux", "IF1 DAC 6", "IF1 DAC6" },
2441 { "IB6 Mux", "IF2 DAC 6", "IF2 DAC6" },
2442 { "IB6 Mux", "SLB DAC 6", "SLB DAC6" },
2443 { "IB6 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2444 { "IB6 Mux", "IF4 DAC L", "IF4 DAC L" },
2445 { "IB6 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2446 { "IB6 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2447 { "IB6 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2448
2449 { "IB7 Mux", "IF1 DAC 7", "IF1 DAC7" },
2450 { "IB7 Mux", "IF2 DAC 7", "IF2 DAC7" },
2451 { "IB7 Mux", "SLB DAC 7", "SLB DAC7" },
2452 { "IB7 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2453 { "IB7 Mux", "IF4 DAC R", "IF4 DAC R" },
2454 { "IB7 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2455 { "IB7 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2456 { "IB7 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2457
2458 { "IB8 Mux", "STO1 ADC MIX L", "Stereo1 ADC MIXL" },
2459 { "IB8 Mux", "STO2 ADC MIX L", "Stereo2 ADC MIXL" },
2460 { "IB8 Mux", "STO3 ADC MIX L", "Stereo3 ADC MIXL" },
2461 { "IB8 Mux", "STO4 ADC MIX L", "Stereo4 ADC MIXL" },
2462 { "IB8 Mux", "MONO ADC MIX L", "Mono ADC MIXL" },
2463 { "IB8 Mux", "DACL1 FS", "DAC1 MIXL" },
2464
2465 { "IB9 Mux", "STO1 ADC MIX R", "Stereo1 ADC MIXR" },
2466 { "IB9 Mux", "STO2 ADC MIX R", "Stereo2 ADC MIXR" },
2467 { "IB9 Mux", "STO3 ADC MIX R", "Stereo3 ADC MIXR" },
2468 { "IB9 Mux", "STO4 ADC MIX R", "Stereo4 ADC MIXR" },
2469 { "IB9 Mux", "MONO ADC MIX R", "Mono ADC MIXR" },
2470 { "IB9 Mux", "DACR1 FS", "DAC1 MIXR" },
2471 { "IB9 Mux", "DAC1 FS", "DAC1 FS" },
2472
2473 { "OB01 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2474 { "OB01 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2475 { "OB01 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2476 { "OB01 MIX", "IB6 Switch", "IB6 Mux" },
2477 { "OB01 MIX", "IB7 Switch", "IB7 Mux" },
2478 { "OB01 MIX", "IB8 Switch", "IB8 Mux" },
2479 { "OB01 MIX", "IB9 Switch", "IB9 Mux" },
2480
2481 { "OB23 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2482 { "OB23 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2483 { "OB23 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2484 { "OB23 MIX", "IB6 Switch", "IB6 Mux" },
2485 { "OB23 MIX", "IB7 Switch", "IB7 Mux" },
2486 { "OB23 MIX", "IB8 Switch", "IB8 Mux" },
2487 { "OB23 MIX", "IB9 Switch", "IB9 Mux" },
2488
2489 { "OB4 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2490 { "OB4 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2491 { "OB4 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2492 { "OB4 MIX", "IB6 Switch", "IB6 Mux" },
2493 { "OB4 MIX", "IB7 Switch", "IB7 Mux" },
2494 { "OB4 MIX", "IB8 Switch", "IB8 Mux" },
2495 { "OB4 MIX", "IB9 Switch", "IB9 Mux" },
2496
2497 { "OB5 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2498 { "OB5 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2499 { "OB5 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2500 { "OB5 MIX", "IB6 Switch", "IB6 Mux" },
2501 { "OB5 MIX", "IB7 Switch", "IB7 Mux" },
2502 { "OB5 MIX", "IB8 Switch", "IB8 Mux" },
2503 { "OB5 MIX", "IB9 Switch", "IB9 Mux" },
2504
2505 { "OB6 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2506 { "OB6 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2507 { "OB6 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2508 { "OB6 MIX", "IB6 Switch", "IB6 Mux" },
2509 { "OB6 MIX", "IB7 Switch", "IB7 Mux" },
2510 { "OB6 MIX", "IB8 Switch", "IB8 Mux" },
2511 { "OB6 MIX", "IB9 Switch", "IB9 Mux" },
2512
2513 { "OB7 MIX", "IB01 Switch", "IB01 Bypass Mux" },
2514 { "OB7 MIX", "IB23 Switch", "IB23 Bypass Mux" },
2515 { "OB7 MIX", "IB45 Switch", "IB45 Bypass Mux" },
2516 { "OB7 MIX", "IB6 Switch", "IB6 Mux" },
2517 { "OB7 MIX", "IB7 Switch", "IB7 Mux" },
2518 { "OB7 MIX", "IB8 Switch", "IB8 Mux" },
2519 { "OB7 MIX", "IB9 Switch", "IB9 Mux" },
2520
2521 { "OB01 Bypass Mux", "Bypass", "OB01 MIX" },
2522 { "OB01 Bypass Mux", "Pass SRC", "OB01 MIX" },
2523 { "OB23 Bypass Mux", "Bypass", "OB23 MIX" },
2524 { "OB23 Bypass Mux", "Pass SRC", "OB23 MIX" },
2525
2526 { "OutBound2", NULL, "OB23 Bypass Mux" },
2527 { "OutBound3", NULL, "OB23 Bypass Mux" },
2528 { "OutBound4", NULL, "OB4 MIX" },
2529 { "OutBound5", NULL, "OB5 MIX" },
2530 { "OutBound6", NULL, "OB6 MIX" },
2531 { "OutBound7", NULL, "OB7 MIX" },
2532
2533 { "OB45", NULL, "OutBound4" },
2534 { "OB45", NULL, "OutBound5" },
2535 { "OB67", NULL, "OutBound6" },
2536 { "OB67", NULL, "OutBound7" },
2537
2538 { "IF1 DAC0", NULL, "AIF1RX" },
2539 { "IF1 DAC1", NULL, "AIF1RX" },
2540 { "IF1 DAC2", NULL, "AIF1RX" },
2541 { "IF1 DAC3", NULL, "AIF1RX" },
2542 { "IF1 DAC4", NULL, "AIF1RX" },
2543 { "IF1 DAC5", NULL, "AIF1RX" },
2544 { "IF1 DAC6", NULL, "AIF1RX" },
2545 { "IF1 DAC7", NULL, "AIF1RX" },
2546 { "IF1 DAC0", NULL, "I2S1" },
2547 { "IF1 DAC1", NULL, "I2S1" },
2548 { "IF1 DAC2", NULL, "I2S1" },
2549 { "IF1 DAC3", NULL, "I2S1" },
2550 { "IF1 DAC4", NULL, "I2S1" },
2551 { "IF1 DAC5", NULL, "I2S1" },
2552 { "IF1 DAC6", NULL, "I2S1" },
2553 { "IF1 DAC7", NULL, "I2S1" },
2554
2555 { "IF1 DAC01", NULL, "IF1 DAC0" },
2556 { "IF1 DAC01", NULL, "IF1 DAC1" },
2557 { "IF1 DAC23", NULL, "IF1 DAC2" },
2558 { "IF1 DAC23", NULL, "IF1 DAC3" },
2559 { "IF1 DAC45", NULL, "IF1 DAC4" },
2560 { "IF1 DAC45", NULL, "IF1 DAC5" },
2561 { "IF1 DAC67", NULL, "IF1 DAC6" },
2562 { "IF1 DAC67", NULL, "IF1 DAC7" },
2563
2564 { "IF2 DAC0", NULL, "AIF2RX" },
2565 { "IF2 DAC1", NULL, "AIF2RX" },
2566 { "IF2 DAC2", NULL, "AIF2RX" },
2567 { "IF2 DAC3", NULL, "AIF2RX" },
2568 { "IF2 DAC4", NULL, "AIF2RX" },
2569 { "IF2 DAC5", NULL, "AIF2RX" },
2570 { "IF2 DAC6", NULL, "AIF2RX" },
2571 { "IF2 DAC7", NULL, "AIF2RX" },
2572 { "IF2 DAC0", NULL, "I2S2" },
2573 { "IF2 DAC1", NULL, "I2S2" },
2574 { "IF2 DAC2", NULL, "I2S2" },
2575 { "IF2 DAC3", NULL, "I2S2" },
2576 { "IF2 DAC4", NULL, "I2S2" },
2577 { "IF2 DAC5", NULL, "I2S2" },
2578 { "IF2 DAC6", NULL, "I2S2" },
2579 { "IF2 DAC7", NULL, "I2S2" },
2580
2581 { "IF2 DAC01", NULL, "IF2 DAC0" },
2582 { "IF2 DAC01", NULL, "IF2 DAC1" },
2583 { "IF2 DAC23", NULL, "IF2 DAC2" },
2584 { "IF2 DAC23", NULL, "IF2 DAC3" },
2585 { "IF2 DAC45", NULL, "IF2 DAC4" },
2586 { "IF2 DAC45", NULL, "IF2 DAC5" },
2587 { "IF2 DAC67", NULL, "IF2 DAC6" },
2588 { "IF2 DAC67", NULL, "IF2 DAC7" },
2589
2590 { "IF3 DAC", NULL, "AIF3RX" },
2591 { "IF3 DAC", NULL, "I2S3" },
2592
2593 { "IF4 DAC", NULL, "AIF4RX" },
2594 { "IF4 DAC", NULL, "I2S4" },
2595
2596 { "IF3 DAC L", NULL, "IF3 DAC" },
2597 { "IF3 DAC R", NULL, "IF3 DAC" },
2598
2599 { "IF4 DAC L", NULL, "IF4 DAC" },
2600 { "IF4 DAC R", NULL, "IF4 DAC" },
2601
2602 { "SLB DAC0", NULL, "SLBRX" },
2603 { "SLB DAC1", NULL, "SLBRX" },
2604 { "SLB DAC2", NULL, "SLBRX" },
2605 { "SLB DAC3", NULL, "SLBRX" },
2606 { "SLB DAC4", NULL, "SLBRX" },
2607 { "SLB DAC5", NULL, "SLBRX" },
2608 { "SLB DAC6", NULL, "SLBRX" },
2609 { "SLB DAC7", NULL, "SLBRX" },
2610 { "SLB DAC0", NULL, "SLB" },
2611 { "SLB DAC1", NULL, "SLB" },
2612 { "SLB DAC2", NULL, "SLB" },
2613 { "SLB DAC3", NULL, "SLB" },
2614 { "SLB DAC4", NULL, "SLB" },
2615 { "SLB DAC5", NULL, "SLB" },
2616 { "SLB DAC6", NULL, "SLB" },
2617 { "SLB DAC7", NULL, "SLB" },
2618
2619 { "SLB DAC01", NULL, "SLB DAC0" },
2620 { "SLB DAC01", NULL, "SLB DAC1" },
2621 { "SLB DAC23", NULL, "SLB DAC2" },
2622 { "SLB DAC23", NULL, "SLB DAC3" },
2623 { "SLB DAC45", NULL, "SLB DAC4" },
2624 { "SLB DAC45", NULL, "SLB DAC5" },
2625 { "SLB DAC67", NULL, "SLB DAC6" },
2626 { "SLB DAC67", NULL, "SLB DAC7" },
2627
2628 { "ADDA1 Mux", "STO1 ADC MIX", "Stereo1 ADC MIX" },
2629 { "ADDA1 Mux", "STO2 ADC MIX", "Stereo2 ADC MIX" },
2630 { "ADDA1 Mux", "OB 67", "OB67" },
2631
2632 { "DAC1 Mux", "IF1 DAC 01", "IF1 DAC01" },
2633 { "DAC1 Mux", "IF2 DAC 01", "IF2 DAC01" },
2634 { "DAC1 Mux", "IF3 DAC LR", "IF3 DAC" },
2635 { "DAC1 Mux", "IF4 DAC LR", "IF4 DAC" },
2636 { "DAC1 Mux", "SLB DAC 01", "SLB DAC01" },
2637 { "DAC1 Mux", "OB 01", "OB01 Bypass Mux" },
2638
2639 { "DAC1 MIXL", "Stereo ADC Switch", "ADDA1 Mux" },
2640 { "DAC1 MIXL", "DAC1 Switch", "DAC1 Mux" },
2641 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2642 { "DAC1 MIXR", "Stereo ADC Switch", "ADDA1 Mux" },
2643 { "DAC1 MIXR", "DAC1 Switch", "DAC1 Mux" },
2644 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2645
2646 { "DAC1 FS", NULL, "DAC1 MIXL" },
2647 { "DAC1 FS", NULL, "DAC1 MIXR" },
2648
2649 { "DAC2 L Mux", "IF1 DAC 2", "IF1 DAC2" },
2650 { "DAC2 L Mux", "IF2 DAC 2", "IF2 DAC2" },
2651 { "DAC2 L Mux", "IF3 DAC L", "IF3 DAC L" },
2652 { "DAC2 L Mux", "IF4 DAC L", "IF4 DAC L" },
2653 { "DAC2 L Mux", "SLB DAC 2", "SLB DAC2" },
2654 { "DAC2 L Mux", "OB 2", "OutBound2" },
2655
2656 { "DAC2 R Mux", "IF1 DAC 3", "IF1 DAC3" },
2657 { "DAC2 R Mux", "IF2 DAC 3", "IF2 DAC3" },
2658 { "DAC2 R Mux", "IF3 DAC R", "IF3 DAC R" },
2659 { "DAC2 R Mux", "IF4 DAC R", "IF4 DAC R" },
2660 { "DAC2 R Mux", "SLB DAC 3", "SLB DAC3" },
2661 { "DAC2 R Mux", "OB 3", "OutBound3" },
2662 { "DAC2 R Mux", "Haptic Generator", "Haptic Generator" },
2663 { "DAC2 R Mux", "VAD ADC", "VAD ADC Mux" },
2664
2665 { "DAC3 L Mux", "IF1 DAC 4", "IF1 DAC4" },
2666 { "DAC3 L Mux", "IF2 DAC 4", "IF2 DAC4" },
2667 { "DAC3 L Mux", "IF3 DAC L", "IF3 DAC L" },
2668 { "DAC3 L Mux", "IF4 DAC L", "IF4 DAC L" },
2669 { "DAC3 L Mux", "SLB DAC 4", "SLB DAC4" },
2670 { "DAC3 L Mux", "OB 4", "OutBound4" },
2671
2672 { "DAC3 R Mux", "IF1 DAC 5", "IF1 DAC4" },
2673 { "DAC3 R Mux", "IF2 DAC 5", "IF2 DAC4" },
2674 { "DAC3 R Mux", "IF3 DAC R", "IF3 DAC R" },
2675 { "DAC3 R Mux", "IF4 DAC R", "IF4 DAC R" },
2676 { "DAC3 R Mux", "SLB DAC 5", "SLB DAC5" },
2677 { "DAC3 R Mux", "OB 5", "OutBound5" },
2678
2679 { "DAC4 L Mux", "IF1 DAC 6", "IF1 DAC6" },
2680 { "DAC4 L Mux", "IF2 DAC 6", "IF2 DAC6" },
2681 { "DAC4 L Mux", "IF3 DAC L", "IF3 DAC L" },
2682 { "DAC4 L Mux", "IF4 DAC L", "IF4 DAC L" },
2683 { "DAC4 L Mux", "SLB DAC 6", "SLB DAC6" },
2684 { "DAC4 L Mux", "OB 6", "OutBound6" },
2685
2686 { "DAC4 R Mux", "IF1 DAC 7", "IF1 DAC7" },
2687 { "DAC4 R Mux", "IF2 DAC 7", "IF2 DAC7" },
2688 { "DAC4 R Mux", "IF3 DAC R", "IF3 DAC R" },
2689 { "DAC4 R Mux", "IF4 DAC R", "IF4 DAC R" },
2690 { "DAC4 R Mux", "SLB DAC 7", "SLB DAC7" },
2691 { "DAC4 R Mux", "OB 7", "OutBound7" },
2692
2693 { "Sidetone Mux", "DMIC1 L", "DMIC L1" },
2694 { "Sidetone Mux", "DMIC2 L", "DMIC L2" },
2695 { "Sidetone Mux", "DMIC3 L", "DMIC L3" },
2696 { "Sidetone Mux", "DMIC4 L", "DMIC L4" },
2697 { "Sidetone Mux", "ADC1", "ADC 1" },
2698 { "Sidetone Mux", "ADC2", "ADC 2" },
2699
2700 { "Stereo DAC MIXL", "ST L Switch", "Sidetone Mux" },
2701 { "Stereo DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2702 { "Stereo DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2703 { "Stereo DAC MIXL", "DAC1 R Switch", "DAC1 MIXR" },
2704 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2705 { "Stereo DAC MIXR", "ST R Switch", "Sidetone Mux" },
2706 { "Stereo DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2707 { "Stereo DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2708 { "Stereo DAC MIXR", "DAC1 L Switch", "DAC1 MIXL" },
2709 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2710
2711 { "Mono DAC MIXL", "ST L Switch", "Sidetone Mux" },
2712 { "Mono DAC MIXL", "DAC1 L Switch", "DAC1 MIXL" },
2713 { "Mono DAC MIXL", "DAC2 L Switch", "DAC2 L Mux" },
2714 { "Mono DAC MIXL", "DAC2 R Switch", "DAC2 R Mux" },
2715 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2716 { "Mono DAC MIXR", "ST R Switch", "Sidetone Mux" },
2717 { "Mono DAC MIXR", "DAC1 R Switch", "DAC1 MIXR" },
2718 { "Mono DAC MIXR", "DAC2 R Switch", "DAC2 R Mux" },
2719 { "Mono DAC MIXR", "DAC2 L Switch", "DAC2 L Mux" },
2720 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2721
2722 { "DD1 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2723 { "DD1 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2724 { "DD1 MIXL", "DAC3 L Switch", "DAC3 L Mux" },
2725 { "DD1 MIXL", "DAC3 R Switch", "DAC3 R Mux" },
2726 { "DD1 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2727 { "DD1 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2728 { "DD1 MIXR", "DAC3 L Switch", "DAC3 L Mux" },
2729 { "DD1 MIXR", "DAC3 R Switch", "DAC3 R Mux" },
2730
2731 { "DD2 MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2732 { "DD2 MIXL", "Mono DAC Mix L Switch", "Mono DAC MIXL" },
2733 { "DD2 MIXL", "DAC4 L Switch", "DAC4 L Mux" },
2734 { "DD2 MIXL", "DAC4 R Switch", "DAC4 R Mux" },
2735 { "DD2 MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2736 { "DD2 MIXR", "Mono DAC Mix R Switch", "Mono DAC MIXR" },
2737 { "DD2 MIXR", "DAC4 L Switch", "DAC4 L Mux" },
2738 { "DD2 MIXR", "DAC4 R Switch", "DAC4 R Mux" },
2739
2740 { "Stereo DAC MIX", NULL, "Stereo DAC MIXL" },
2741 { "Stereo DAC MIX", NULL, "Stereo DAC MIXR" },
2742 { "Mono DAC MIX", NULL, "Mono DAC MIXL" },
2743 { "Mono DAC MIX", NULL, "Mono DAC MIXR" },
2744 { "DD1 MIX", NULL, "DD1 MIXL" },
2745 { "DD1 MIX", NULL, "DD1 MIXR" },
2746 { "DD2 MIX", NULL, "DD2 MIXL" },
2747 { "DD2 MIX", NULL, "DD2 MIXR" },
2748
2749 { "DAC12 SRC Mux", "STO1 DAC MIX", "Stereo DAC MIX" },
2750 { "DAC12 SRC Mux", "MONO DAC MIX", "Mono DAC MIX" },
2751 { "DAC12 SRC Mux", "DD MIX1", "DD1 MIX" },
2752 { "DAC12 SRC Mux", "DD MIX2", "DD2 MIX" },
2753
2754 { "DAC3 SRC Mux", "MONO DAC MIXL", "Mono DAC MIXL" },
2755 { "DAC3 SRC Mux", "MONO DAC MIXR", "Mono DAC MIXR" },
2756 { "DAC3 SRC Mux", "DD MIX1L", "DD1 MIXL" },
2757 { "DAC3 SRC Mux", "DD MIX2L", "DD2 MIXL" },
2758
2759 { "DAC 1", NULL, "DAC12 SRC Mux" },
2760 { "DAC 1", NULL, "PLL1", is_sys_clk_from_pll },
2761 { "DAC 2", NULL, "DAC12 SRC Mux" },
2762 { "DAC 2", NULL, "PLL1", is_sys_clk_from_pll },
2763 { "DAC 3", NULL, "DAC3 SRC Mux" },
2764 { "DAC 3", NULL, "PLL1", is_sys_clk_from_pll },
2765
2766 { "PDM1 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2767 { "PDM1 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2768 { "PDM1 L Mux", "DD MIX1", "DD1 MIXL" },
2769 { "PDM1 L Mux", "DD MIX2", "DD2 MIXL" },
2770 { "PDM1 L Mux", NULL, "PDM1 Power" },
2771 { "PDM1 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2772 { "PDM1 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2773 { "PDM1 R Mux", "DD MIX1", "DD1 MIXR" },
2774 { "PDM1 R Mux", "DD MIX2", "DD2 MIXR" },
2775 { "PDM1 R Mux", NULL, "PDM1 Power" },
2776 { "PDM2 L Mux", "STO1 DAC MIX", "Stereo DAC MIXL" },
2777 { "PDM2 L Mux", "MONO DAC MIX", "Mono DAC MIXL" },
2778 { "PDM2 L Mux", "DD MIX1", "DD1 MIXL" },
2779 { "PDM2 L Mux", "DD MIX2", "DD2 MIXL" },
2780 { "PDM2 L Mux", NULL, "PDM2 Power" },
2781 { "PDM2 R Mux", "STO1 DAC MIX", "Stereo DAC MIXR" },
2782 { "PDM2 R Mux", "MONO DAC MIX", "Mono DAC MIXR" },
2783 { "PDM2 R Mux", "DD MIX1", "DD1 MIXR" },
2784 { "PDM2 R Mux", "DD MIX1", "DD2 MIXR" },
2785 { "PDM2 R Mux", NULL, "PDM2 Power" },
2786
2787 { "LOUT1 amp", NULL, "DAC 1" },
2788 { "LOUT2 amp", NULL, "DAC 2" },
2789 { "LOUT3 amp", NULL, "DAC 3" },
2790
2791 { "LOUT1", NULL, "LOUT1 amp" },
2792 { "LOUT2", NULL, "LOUT2 amp" },
2793 { "LOUT3", NULL, "LOUT3 amp" },
2794
2795 { "PDM1L", NULL, "PDM1 L Mux" },
2796 { "PDM1R", NULL, "PDM1 R Mux" },
2797 { "PDM2L", NULL, "PDM2 L Mux" },
2798 { "PDM2R", NULL, "PDM2 R Mux" },
2799};
2800
2801static int get_clk_info(int sclk, int rate)
2802{
2803 int i, pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
2804
2805 if (sclk <= 0 || rate <= 0)
2806 return -EINVAL;
2807
2808 rate = rate << 8;
2809 for (i = 0; i < ARRAY_SIZE(pd); i++)
2810 if (sclk == rate * pd[i])
2811 return i;
2812
2813 return -EINVAL;
2814}
2815
2816static int rt5677_hw_params(struct snd_pcm_substream *substream,
2817 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2818{
2819 struct snd_soc_codec *codec = dai->codec;
2820 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2821 unsigned int val_len = 0, val_clk, mask_clk;
2822 int pre_div, bclk_ms, frame_size;
2823
2824 rt5677->lrck[dai->id] = params_rate(params);
2825 pre_div = get_clk_info(rt5677->sysclk, rt5677->lrck[dai->id]);
2826 if (pre_div < 0) {
2827 dev_err(codec->dev, "Unsupported clock setting\n");
2828 return -EINVAL;
2829 }
2830 frame_size = snd_soc_params_to_frame_size(params);
2831 if (frame_size < 0) {
2832 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
2833 return -EINVAL;
2834 }
2835 bclk_ms = frame_size > 32;
2836 rt5677->bclk[dai->id] = rt5677->lrck[dai->id] * (32 << bclk_ms);
2837
2838 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2839 rt5677->bclk[dai->id], rt5677->lrck[dai->id]);
2840 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2841 bclk_ms, pre_div, dai->id);
2842
2843 switch (params_width(params)) {
2844 case 16:
2845 break;
2846 case 20:
2847 val_len |= RT5677_I2S_DL_20;
2848 break;
2849 case 24:
2850 val_len |= RT5677_I2S_DL_24;
2851 break;
2852 case 8:
2853 val_len |= RT5677_I2S_DL_8;
2854 break;
2855 default:
2856 return -EINVAL;
2857 }
2858
2859 switch (dai->id) {
2860 case RT5677_AIF1:
2861 mask_clk = RT5677_I2S_PD1_MASK;
2862 val_clk = pre_div << RT5677_I2S_PD1_SFT;
2863 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2864 RT5677_I2S_DL_MASK, val_len);
2865 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2866 mask_clk, val_clk);
2867 break;
2868 case RT5677_AIF2:
2869 mask_clk = RT5677_I2S_PD2_MASK;
2870 val_clk = pre_div << RT5677_I2S_PD2_SFT;
2871 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2872 RT5677_I2S_DL_MASK, val_len);
2873 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2874 mask_clk, val_clk);
2875 break;
2876 case RT5677_AIF3:
2877 mask_clk = RT5677_I2S_BCLK_MS3_MASK | RT5677_I2S_PD3_MASK;
2878 val_clk = bclk_ms << RT5677_I2S_BCLK_MS3_SFT |
2879 pre_div << RT5677_I2S_PD3_SFT;
2880 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2881 RT5677_I2S_DL_MASK, val_len);
2882 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2883 mask_clk, val_clk);
2884 break;
2885 case RT5677_AIF4:
2886 mask_clk = RT5677_I2S_BCLK_MS4_MASK | RT5677_I2S_PD4_MASK;
2887 val_clk = bclk_ms << RT5677_I2S_BCLK_MS4_SFT |
2888 pre_div << RT5677_I2S_PD4_SFT;
2889 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2890 RT5677_I2S_DL_MASK, val_len);
2891 regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
2892 mask_clk, val_clk);
2893 break;
2894 default:
2895 break;
2896 }
2897
2898 return 0;
2899}
2900
2901static int rt5677_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2902{
2903 struct snd_soc_codec *codec = dai->codec;
2904 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2905 unsigned int reg_val = 0;
2906
2907 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2908 case SND_SOC_DAIFMT_CBM_CFM:
2909 rt5677->master[dai->id] = 1;
2910 break;
2911 case SND_SOC_DAIFMT_CBS_CFS:
2912 reg_val |= RT5677_I2S_MS_S;
2913 rt5677->master[dai->id] = 0;
2914 break;
2915 default:
2916 return -EINVAL;
2917 }
2918
2919 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2920 case SND_SOC_DAIFMT_NB_NF:
2921 break;
2922 case SND_SOC_DAIFMT_IB_NF:
2923 reg_val |= RT5677_I2S_BP_INV;
2924 break;
2925 default:
2926 return -EINVAL;
2927 }
2928
2929 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2930 case SND_SOC_DAIFMT_I2S:
2931 break;
2932 case SND_SOC_DAIFMT_LEFT_J:
2933 reg_val |= RT5677_I2S_DF_LEFT;
2934 break;
2935 case SND_SOC_DAIFMT_DSP_A:
2936 reg_val |= RT5677_I2S_DF_PCM_A;
2937 break;
2938 case SND_SOC_DAIFMT_DSP_B:
2939 reg_val |= RT5677_I2S_DF_PCM_B;
2940 break;
2941 default:
2942 return -EINVAL;
2943 }
2944
2945 switch (dai->id) {
2946 case RT5677_AIF1:
2947 regmap_update_bits(rt5677->regmap, RT5677_I2S1_SDP,
2948 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2949 RT5677_I2S_DF_MASK, reg_val);
2950 break;
2951 case RT5677_AIF2:
2952 regmap_update_bits(rt5677->regmap, RT5677_I2S2_SDP,
2953 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2954 RT5677_I2S_DF_MASK, reg_val);
2955 break;
2956 case RT5677_AIF3:
2957 regmap_update_bits(rt5677->regmap, RT5677_I2S3_SDP,
2958 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2959 RT5677_I2S_DF_MASK, reg_val);
2960 break;
2961 case RT5677_AIF4:
2962 regmap_update_bits(rt5677->regmap, RT5677_I2S4_SDP,
2963 RT5677_I2S_MS_MASK | RT5677_I2S_BP_MASK |
2964 RT5677_I2S_DF_MASK, reg_val);
2965 break;
2966 default:
2967 break;
2968 }
2969
2970
2971 return 0;
2972}
2973
2974static int rt5677_set_dai_sysclk(struct snd_soc_dai *dai,
2975 int clk_id, unsigned int freq, int dir)
2976{
2977 struct snd_soc_codec *codec = dai->codec;
2978 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
2979 unsigned int reg_val = 0;
2980
2981 if (freq == rt5677->sysclk && clk_id == rt5677->sysclk_src)
2982 return 0;
2983
2984 switch (clk_id) {
2985 case RT5677_SCLK_S_MCLK:
2986 reg_val |= RT5677_SCLK_SRC_MCLK;
2987 break;
2988 case RT5677_SCLK_S_PLL1:
2989 reg_val |= RT5677_SCLK_SRC_PLL1;
2990 break;
2991 case RT5677_SCLK_S_RCCLK:
2992 reg_val |= RT5677_SCLK_SRC_RCCLK;
2993 break;
2994 default:
2995 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2996 return -EINVAL;
2997 }
2998 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
2999 RT5677_SCLK_SRC_MASK, reg_val);
3000 rt5677->sysclk = freq;
3001 rt5677->sysclk_src = clk_id;
3002
3003 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
3004
3005 return 0;
3006}
3007
3008/**
3009 * rt5677_pll_calc - Calcualte PLL M/N/K code.
3010 * @freq_in: external clock provided to codec.
3011 * @freq_out: target clock which codec works on.
3012 * @pll_code: Pointer to structure with M, N, K, bypass K and bypass M flag.
3013 *
3014 * Calcualte M/N/K code and bypass K/M flag to configure PLL for codec.
3015 *
3016 * Returns 0 for success or negative error code.
3017 */
3018static int rt5677_pll_calc(const unsigned int freq_in,
3019 const unsigned int freq_out, struct rt5677_pll_code *pll_code)
3020{
3021 int max_n = RT5677_PLL_N_MAX, max_m = RT5677_PLL_M_MAX;
3022 int k, red, n_t, pll_out, in_t;
3023 int n = 0, m = 0, m_t = 0;
3024 int out_t, red_t = abs(freq_out - freq_in);
3025 bool m_bp = false, k_bp = false;
3026
3027 if (RT5677_PLL_INP_MAX < freq_in || RT5677_PLL_INP_MIN > freq_in)
3028 return -EINVAL;
3029
3030 k = 100000000 / freq_out - 2;
3031 if (k > RT5677_PLL_K_MAX)
3032 k = RT5677_PLL_K_MAX;
3033 for (n_t = 0; n_t <= max_n; n_t++) {
3034 in_t = freq_in / (k + 2);
3035 pll_out = freq_out / (n_t + 2);
3036 if (in_t < 0)
3037 continue;
3038 if (in_t == pll_out) {
3039 m_bp = true;
3040 n = n_t;
3041 goto code_find;
3042 }
3043 red = abs(in_t - pll_out);
3044 if (red < red_t) {
3045 m_bp = true;
3046 n = n_t;
3047 m = m_t;
3048 if (red == 0)
3049 goto code_find;
3050 red_t = red;
3051 }
3052 for (m_t = 0; m_t <= max_m; m_t++) {
3053 out_t = in_t / (m_t + 2);
3054 red = abs(out_t - pll_out);
3055 if (red < red_t) {
3056 m_bp = false;
3057 n = n_t;
3058 m = m_t;
3059 if (red == 0)
3060 goto code_find;
3061 red_t = red;
3062 }
3063 }
3064 }
3065 pr_debug("Only get approximation about PLL\n");
3066
3067code_find:
3068
3069 pll_code->m_bp = m_bp;
3070 pll_code->k_bp = k_bp;
3071 pll_code->m_code = m;
3072 pll_code->n_code = n;
3073 pll_code->k_code = k;
3074 return 0;
3075}
3076
3077static int rt5677_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
3078 unsigned int freq_in, unsigned int freq_out)
3079{
3080 struct snd_soc_codec *codec = dai->codec;
3081 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3082 struct rt5677_pll_code pll_code;
3083 int ret;
3084
3085 if (source == rt5677->pll_src && freq_in == rt5677->pll_in &&
3086 freq_out == rt5677->pll_out)
3087 return 0;
3088
3089 if (!freq_in || !freq_out) {
3090 dev_dbg(codec->dev, "PLL disabled\n");
3091
3092 rt5677->pll_in = 0;
3093 rt5677->pll_out = 0;
3094 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3095 RT5677_SCLK_SRC_MASK, RT5677_SCLK_SRC_MCLK);
3096 return 0;
3097 }
3098
3099 switch (source) {
3100 case RT5677_PLL1_S_MCLK:
3101 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3102 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_MCLK);
3103 break;
3104 case RT5677_PLL1_S_BCLK1:
3105 case RT5677_PLL1_S_BCLK2:
3106 case RT5677_PLL1_S_BCLK3:
3107 case RT5677_PLL1_S_BCLK4:
3108 switch (dai->id) {
3109 case RT5677_AIF1:
3110 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3111 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK1);
3112 break;
3113 case RT5677_AIF2:
3114 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3115 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK2);
3116 break;
3117 case RT5677_AIF3:
3118 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3119 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK3);
3120 break;
3121 case RT5677_AIF4:
3122 regmap_update_bits(rt5677->regmap, RT5677_GLB_CLK1,
3123 RT5677_PLL1_SRC_MASK, RT5677_PLL1_SRC_BCLK4);
3124 break;
3125 default:
3126 break;
3127 }
3128 break;
3129 default:
3130 dev_err(codec->dev, "Unknown PLL source %d\n", source);
3131 return -EINVAL;
3132 }
3133
3134 ret = rt5677_pll_calc(freq_in, freq_out, &pll_code);
3135 if (ret < 0) {
3136 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
3137 return ret;
3138 }
3139
3140 dev_dbg(codec->dev, "m_bypass=%d k_bypass=%d m=%d n=%d k=%d\n",
3141 pll_code.m_bp, pll_code.k_bp,
3142 (pll_code.m_bp ? 0 : pll_code.m_code), pll_code.n_code,
3143 (pll_code.k_bp ? 0 : pll_code.k_code));
3144
3145 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL1,
3146 pll_code.n_code << RT5677_PLL_N_SFT |
3147 pll_code.k_bp << RT5677_PLL_K_BP_SFT |
3148 (pll_code.k_bp ? 0 : pll_code.k_code));
3149 regmap_write(rt5677->regmap, RT5677_PLL1_CTRL2,
3150 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5677_PLL_M_SFT |
3151 pll_code.m_bp << RT5677_PLL_M_BP_SFT);
3152
3153 rt5677->pll_in = freq_in;
3154 rt5677->pll_out = freq_out;
3155 rt5677->pll_src = source;
3156
3157 return 0;
3158}
3159
3160static int rt5677_set_bias_level(struct snd_soc_codec *codec,
3161 enum snd_soc_bias_level level)
3162{
3163 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3164
3165 switch (level) {
3166 case SND_SOC_BIAS_ON:
3167 break;
3168
3169 case SND_SOC_BIAS_PREPARE:
3170 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
3171 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3172 RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
3173 0x0055);
3174 regmap_update_bits(rt5677->regmap,
3175 RT5677_PR_BASE + RT5677_BIAS_CUR4,
3176 0x0f00, 0x0f00);
3177 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3178 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3179 RT5677_PWR_BG | RT5677_PWR_VREF2,
3180 RT5677_PWR_VREF1 | RT5677_PWR_MB |
3181 RT5677_PWR_BG | RT5677_PWR_VREF2);
3182 mdelay(20);
3183 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
3184 RT5677_PWR_FV1 | RT5677_PWR_FV2,
3185 RT5677_PWR_FV1 | RT5677_PWR_FV2);
3186 regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
3187 RT5677_PWR_CORE, RT5677_PWR_CORE);
3188 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC,
3189 0x1, 0x1);
3190 }
3191 break;
3192
3193 case SND_SOC_BIAS_STANDBY:
3194 break;
3195
3196 case SND_SOC_BIAS_OFF:
3197 regmap_update_bits(rt5677->regmap, RT5677_DIG_MISC, 0x1, 0x0);
3198 regmap_write(rt5677->regmap, RT5677_PWR_DIG1, 0x0000);
3199 regmap_write(rt5677->regmap, RT5677_PWR_DIG2, 0x0000);
3200 regmap_write(rt5677->regmap, RT5677_PWR_ANLG1, 0x0000);
3201 regmap_write(rt5677->regmap, RT5677_PWR_ANLG2, 0x0000);
3202 regmap_update_bits(rt5677->regmap,
3203 RT5677_PR_BASE + RT5677_BIAS_CUR4, 0x0f00, 0x0000);
3204 break;
3205
3206 default:
3207 break;
3208 }
3209 codec->dapm.bias_level = level;
3210
3211 return 0;
3212}
3213
3214static int rt5677_probe(struct snd_soc_codec *codec)
3215{
3216 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3217
3218 rt5677->codec = codec;
3219
3220 rt5677_set_bias_level(codec, SND_SOC_BIAS_OFF);
3221
3222 regmap_write(rt5677->regmap, RT5677_DIG_MISC, 0x0020);
3223 regmap_write(rt5677->regmap, RT5677_PWR_DSP2, 0x0c00);
3224
3225 return 0;
3226}
3227
3228static int rt5677_remove(struct snd_soc_codec *codec)
3229{
3230 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3231
3232 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3233
3234 return 0;
3235}
3236
3237#ifdef CONFIG_PM
3238static int rt5677_suspend(struct snd_soc_codec *codec)
3239{
3240 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3241
3242 regcache_cache_only(rt5677->regmap, true);
3243 regcache_mark_dirty(rt5677->regmap);
3244
3245 return 0;
3246}
3247
3248static int rt5677_resume(struct snd_soc_codec *codec)
3249{
3250 struct rt5677_priv *rt5677 = snd_soc_codec_get_drvdata(codec);
3251
3252 regcache_cache_only(rt5677->regmap, false);
3253 regcache_sync(rt5677->regmap);
3254
3255 return 0;
3256}
3257#else
3258#define rt5677_suspend NULL
3259#define rt5677_resume NULL
3260#endif
3261
3262#define RT5677_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3263#define RT5677_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3264 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3265
3266static struct snd_soc_dai_ops rt5677_aif_dai_ops = {
3267 .hw_params = rt5677_hw_params,
3268 .set_fmt = rt5677_set_dai_fmt,
3269 .set_sysclk = rt5677_set_dai_sysclk,
3270 .set_pll = rt5677_set_dai_pll,
3271};
3272
3273static struct snd_soc_dai_driver rt5677_dai[] = {
3274 {
3275 .name = "rt5677-aif1",
3276 .id = RT5677_AIF1,
3277 .playback = {
3278 .stream_name = "AIF1 Playback",
3279 .channels_min = 1,
3280 .channels_max = 2,
3281 .rates = RT5677_STEREO_RATES,
3282 .formats = RT5677_FORMATS,
3283 },
3284 .capture = {
3285 .stream_name = "AIF1 Capture",
3286 .channels_min = 1,
3287 .channels_max = 2,
3288 .rates = RT5677_STEREO_RATES,
3289 .formats = RT5677_FORMATS,
3290 },
3291 .ops = &rt5677_aif_dai_ops,
3292 },
3293 {
3294 .name = "rt5677-aif2",
3295 .id = RT5677_AIF2,
3296 .playback = {
3297 .stream_name = "AIF2 Playback",
3298 .channels_min = 1,
3299 .channels_max = 2,
3300 .rates = RT5677_STEREO_RATES,
3301 .formats = RT5677_FORMATS,
3302 },
3303 .capture = {
3304 .stream_name = "AIF2 Capture",
3305 .channels_min = 1,
3306 .channels_max = 2,
3307 .rates = RT5677_STEREO_RATES,
3308 .formats = RT5677_FORMATS,
3309 },
3310 .ops = &rt5677_aif_dai_ops,
3311 },
3312 {
3313 .name = "rt5677-aif3",
3314 .id = RT5677_AIF3,
3315 .playback = {
3316 .stream_name = "AIF3 Playback",
3317 .channels_min = 1,
3318 .channels_max = 2,
3319 .rates = RT5677_STEREO_RATES,
3320 .formats = RT5677_FORMATS,
3321 },
3322 .capture = {
3323 .stream_name = "AIF3 Capture",
3324 .channels_min = 1,
3325 .channels_max = 2,
3326 .rates = RT5677_STEREO_RATES,
3327 .formats = RT5677_FORMATS,
3328 },
3329 .ops = &rt5677_aif_dai_ops,
3330 },
3331 {
3332 .name = "rt5677-aif4",
3333 .id = RT5677_AIF4,
3334 .playback = {
3335 .stream_name = "AIF4 Playback",
3336 .channels_min = 1,
3337 .channels_max = 2,
3338 .rates = RT5677_STEREO_RATES,
3339 .formats = RT5677_FORMATS,
3340 },
3341 .capture = {
3342 .stream_name = "AIF4 Capture",
3343 .channels_min = 1,
3344 .channels_max = 2,
3345 .rates = RT5677_STEREO_RATES,
3346 .formats = RT5677_FORMATS,
3347 },
3348 .ops = &rt5677_aif_dai_ops,
3349 },
3350 {
3351 .name = "rt5677-slimbus",
3352 .id = RT5677_AIF5,
3353 .playback = {
3354 .stream_name = "SLIMBus Playback",
3355 .channels_min = 1,
3356 .channels_max = 2,
3357 .rates = RT5677_STEREO_RATES,
3358 .formats = RT5677_FORMATS,
3359 },
3360 .capture = {
3361 .stream_name = "SLIMBus Capture",
3362 .channels_min = 1,
3363 .channels_max = 2,
3364 .rates = RT5677_STEREO_RATES,
3365 .formats = RT5677_FORMATS,
3366 },
3367 .ops = &rt5677_aif_dai_ops,
3368 },
3369};
3370
3371static struct snd_soc_codec_driver soc_codec_dev_rt5677 = {
3372 .probe = rt5677_probe,
3373 .remove = rt5677_remove,
3374 .suspend = rt5677_suspend,
3375 .resume = rt5677_resume,
3376 .set_bias_level = rt5677_set_bias_level,
3377 .idle_bias_off = true,
3378 .controls = rt5677_snd_controls,
3379 .num_controls = ARRAY_SIZE(rt5677_snd_controls),
3380 .dapm_widgets = rt5677_dapm_widgets,
3381 .num_dapm_widgets = ARRAY_SIZE(rt5677_dapm_widgets),
3382 .dapm_routes = rt5677_dapm_routes,
3383 .num_dapm_routes = ARRAY_SIZE(rt5677_dapm_routes),
3384};
3385
3386static const struct regmap_config rt5677_regmap = {
3387 .reg_bits = 8,
3388 .val_bits = 16,
3389
3390 .max_register = RT5677_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5677_ranges) *
3391 RT5677_PR_SPACING),
3392
3393 .volatile_reg = rt5677_volatile_register,
3394 .readable_reg = rt5677_readable_register,
3395
3396 .cache_type = REGCACHE_RBTREE,
3397 .reg_defaults = rt5677_reg,
3398 .num_reg_defaults = ARRAY_SIZE(rt5677_reg),
3399 .ranges = rt5677_ranges,
3400 .num_ranges = ARRAY_SIZE(rt5677_ranges),
3401};
3402
3403static const struct i2c_device_id rt5677_i2c_id[] = {
3404 { "rt5677", 0 },
3405 { }
3406};
3407MODULE_DEVICE_TABLE(i2c, rt5677_i2c_id);
3408
3409static int rt5677_i2c_probe(struct i2c_client *i2c,
3410 const struct i2c_device_id *id)
3411{
3412 struct rt5677_platform_data *pdata = dev_get_platdata(&i2c->dev);
3413 struct rt5677_priv *rt5677;
3414 int ret;
3415 unsigned int val;
3416
3417 rt5677 = devm_kzalloc(&i2c->dev, sizeof(struct rt5677_priv),
3418 GFP_KERNEL);
3419 if (rt5677 == NULL)
3420 return -ENOMEM;
3421
3422 i2c_set_clientdata(i2c, rt5677);
3423
3424 if (pdata)
3425 rt5677->pdata = *pdata;
3426
3427 rt5677->regmap = devm_regmap_init_i2c(i2c, &rt5677_regmap);
3428 if (IS_ERR(rt5677->regmap)) {
3429 ret = PTR_ERR(rt5677->regmap);
3430 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3431 ret);
3432 return ret;
3433 }
3434
3435 regmap_read(rt5677->regmap, RT5677_VENDOR_ID2, &val);
3436 if (val != RT5677_DEVICE_ID) {
3437 dev_err(&i2c->dev,
3438 "Device with ID register %x is not rt5677\n", val);
3439 return -ENODEV;
3440 }
3441
3442 regmap_write(rt5677->regmap, RT5677_RESET, 0x10ec);
3443
3444 ret = regmap_register_patch(rt5677->regmap, init_list,
3445 ARRAY_SIZE(init_list));
3446 if (ret != 0)
3447 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3448
3449 if (rt5677->pdata.in1_diff)
3450 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3451 RT5677_IN_DF1, RT5677_IN_DF1);
3452
3453 if (rt5677->pdata.in2_diff)
3454 regmap_update_bits(rt5677->regmap, RT5677_IN1,
3455 RT5677_IN_DF2, RT5677_IN_DF2);
3456
3457 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5677,
3458 rt5677_dai, ARRAY_SIZE(rt5677_dai));
3459 if (ret < 0)
3460 goto err;
3461
3462 return 0;
3463err:
3464 return ret;
3465}
3466
3467static int rt5677_i2c_remove(struct i2c_client *i2c)
3468{
3469 snd_soc_unregister_codec(&i2c->dev);
3470
3471 return 0;
3472}
3473
3474static struct i2c_driver rt5677_i2c_driver = {
3475 .driver = {
3476 .name = "rt5677",
3477 .owner = THIS_MODULE,
3478 },
3479 .probe = rt5677_i2c_probe,
3480 .remove = rt5677_i2c_remove,
3481 .id_table = rt5677_i2c_id,
3482};
3483
3484static int __init rt5677_modinit(void)
3485{
3486 return i2c_add_driver(&rt5677_i2c_driver);
3487}
3488module_init(rt5677_modinit);
3489
3490static void __exit rt5677_modexit(void)
3491{
3492 i2c_del_driver(&rt5677_i2c_driver);
3493}
3494module_exit(rt5677_modexit);
3495
3496MODULE_DESCRIPTION("ASoC RT5677 driver");
3497MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
3498MODULE_LICENSE("GPL v2");
diff --git a/sound/soc/codecs/rt5677.h b/sound/soc/codecs/rt5677.h
new file mode 100644
index 000000000000..af4e9c797408
--- /dev/null
+++ b/sound/soc/codecs/rt5677.h
@@ -0,0 +1,1451 @@
1/*
2 * rt5677.h -- RT5677 ALSA SoC audio driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Oder Chiou <oder_chiou@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __RT5677_H__
13#define __RT5677_H__
14
15#include <sound/rt5677.h>
16
17/* Info */
18#define RT5677_RESET 0x00
19#define RT5677_VENDOR_ID 0xfd
20#define RT5677_VENDOR_ID1 0xfe
21#define RT5677_VENDOR_ID2 0xff
22/* I/O - Output */
23#define RT5677_LOUT1 0x01
24/* I/O - Input */
25#define RT5677_IN1 0x03
26#define RT5677_MICBIAS 0x04
27/* I/O - SLIMBus */
28#define RT5677_SLIMBUS_PARAM 0x07
29#define RT5677_SLIMBUS_RX 0x08
30#define RT5677_SLIMBUS_CTRL 0x09
31/* I/O */
32#define RT5677_SIDETONE_CTRL 0x13
33/* I/O - ADC/DAC */
34#define RT5677_ANA_DAC1_2_3_SRC 0x15
35#define RT5677_IF_DSP_DAC3_4_MIXER 0x16
36#define RT5677_DAC4_DIG_VOL 0x17
37#define RT5677_DAC3_DIG_VOL 0x18
38#define RT5677_DAC1_DIG_VOL 0x19
39#define RT5677_DAC2_DIG_VOL 0x1a
40#define RT5677_IF_DSP_DAC2_MIXER 0x1b
41#define RT5677_STO1_ADC_DIG_VOL 0x1c
42#define RT5677_MONO_ADC_DIG_VOL 0x1d
43#define RT5677_STO1_2_ADC_BST 0x1e
44#define RT5677_STO2_ADC_DIG_VOL 0x1f
45/* Mixer - D-D */
46#define RT5677_ADC_BST_CTRL2 0x20
47#define RT5677_STO3_4_ADC_BST 0x21
48#define RT5677_STO3_ADC_DIG_VOL 0x22
49#define RT5677_STO4_ADC_DIG_VOL 0x23
50#define RT5677_STO4_ADC_MIXER 0x24
51#define RT5677_STO3_ADC_MIXER 0x25
52#define RT5677_STO2_ADC_MIXER 0x26
53#define RT5677_STO1_ADC_MIXER 0x27
54#define RT5677_MONO_ADC_MIXER 0x28
55#define RT5677_ADC_IF_DSP_DAC1_MIXER 0x29
56#define RT5677_STO1_DAC_MIXER 0x2a
57#define RT5677_MONO_DAC_MIXER 0x2b
58#define RT5677_DD1_MIXER 0x2c
59#define RT5677_DD2_MIXER 0x2d
60#define RT5677_IF3_DATA 0x2f
61#define RT5677_IF4_DATA 0x30
62/* Mixer - PDM */
63#define RT5677_PDM_OUT_CTRL 0x31
64#define RT5677_PDM_DATA_CTRL1 0x32
65#define RT5677_PDM_DATA_CTRL2 0x33
66#define RT5677_PDM1_DATA_CTRL2 0x34
67#define RT5677_PDM1_DATA_CTRL3 0x35
68#define RT5677_PDM1_DATA_CTRL4 0x36
69#define RT5677_PDM2_DATA_CTRL2 0x37
70#define RT5677_PDM2_DATA_CTRL3 0x38
71#define RT5677_PDM2_DATA_CTRL4 0x39
72/* TDM */
73#define RT5677_TDM1_CTRL1 0x3b
74#define RT5677_TDM1_CTRL2 0x3c
75#define RT5677_TDM1_CTRL3 0x3d
76#define RT5677_TDM1_CTRL4 0x3e
77#define RT5677_TDM1_CTRL5 0x3f
78#define RT5677_TDM2_CTRL1 0x40
79#define RT5677_TDM2_CTRL2 0x41
80#define RT5677_TDM2_CTRL3 0x42
81#define RT5677_TDM2_CTRL4 0x43
82#define RT5677_TDM2_CTRL5 0x44
83/* I2C_MASTER_CTRL */
84#define RT5677_I2C_MASTER_CTRL1 0x47
85#define RT5677_I2C_MASTER_CTRL2 0x48
86#define RT5677_I2C_MASTER_CTRL3 0x49
87#define RT5677_I2C_MASTER_CTRL4 0x4a
88#define RT5677_I2C_MASTER_CTRL5 0x4b
89#define RT5677_I2C_MASTER_CTRL6 0x4c
90#define RT5677_I2C_MASTER_CTRL7 0x4d
91#define RT5677_I2C_MASTER_CTRL8 0x4e
92/* DMIC */
93#define RT5677_DMIC_CTRL1 0x50
94#define RT5677_DMIC_CTRL2 0x51
95/* Haptic Generator */
96#define RT5677_HAP_GENE_CTRL1 0x56
97#define RT5677_HAP_GENE_CTRL2 0x57
98#define RT5677_HAP_GENE_CTRL3 0x58
99#define RT5677_HAP_GENE_CTRL4 0x59
100#define RT5677_HAP_GENE_CTRL5 0x5a
101#define RT5677_HAP_GENE_CTRL6 0x5b
102#define RT5677_HAP_GENE_CTRL7 0x5c
103#define RT5677_HAP_GENE_CTRL8 0x5d
104#define RT5677_HAP_GENE_CTRL9 0x5e
105#define RT5677_HAP_GENE_CTRL10 0x5f
106/* Power */
107#define RT5677_PWR_DIG1 0x61
108#define RT5677_PWR_DIG2 0x62
109#define RT5677_PWR_ANLG1 0x63
110#define RT5677_PWR_ANLG2 0x64
111#define RT5677_PWR_DSP1 0x65
112#define RT5677_PWR_DSP_ST 0x66
113#define RT5677_PWR_DSP2 0x67
114#define RT5677_ADC_DAC_HPF_CTRL1 0x68
115/* Private Register Control */
116#define RT5677_PRIV_INDEX 0x6a
117#define RT5677_PRIV_DATA 0x6c
118/* Format - ADC/DAC */
119#define RT5677_I2S4_SDP 0x6f
120#define RT5677_I2S1_SDP 0x70
121#define RT5677_I2S2_SDP 0x71
122#define RT5677_I2S3_SDP 0x72
123#define RT5677_CLK_TREE_CTRL1 0x73
124#define RT5677_CLK_TREE_CTRL2 0x74
125#define RT5677_CLK_TREE_CTRL3 0x75
126/* Function - Analog */
127#define RT5677_PLL1_CTRL1 0x7a
128#define RT5677_PLL1_CTRL2 0x7b
129#define RT5677_PLL2_CTRL1 0x7c
130#define RT5677_PLL2_CTRL2 0x7d
131#define RT5677_GLB_CLK1 0x80
132#define RT5677_GLB_CLK2 0x81
133#define RT5677_ASRC_1 0x83
134#define RT5677_ASRC_2 0x84
135#define RT5677_ASRC_3 0x85
136#define RT5677_ASRC_4 0x86
137#define RT5677_ASRC_5 0x87
138#define RT5677_ASRC_6 0x88
139#define RT5677_ASRC_7 0x89
140#define RT5677_ASRC_8 0x8a
141#define RT5677_ASRC_9 0x8b
142#define RT5677_ASRC_10 0x8c
143#define RT5677_ASRC_11 0x8d
144#define RT5677_ASRC_12 0x8e
145#define RT5677_ASRC_13 0x8f
146#define RT5677_ASRC_14 0x90
147#define RT5677_ASRC_15 0x91
148#define RT5677_ASRC_16 0x92
149#define RT5677_ASRC_17 0x93
150#define RT5677_ASRC_18 0x94
151#define RT5677_ASRC_19 0x95
152#define RT5677_ASRC_20 0x97
153#define RT5677_ASRC_21 0x98
154#define RT5677_ASRC_22 0x99
155#define RT5677_ASRC_23 0x9a
156#define RT5677_VAD_CTRL1 0x9c
157#define RT5677_VAD_CTRL2 0x9d
158#define RT5677_VAD_CTRL3 0x9e
159#define RT5677_VAD_CTRL4 0x9f
160#define RT5677_VAD_CTRL5 0xa0
161/* Function - Digital */
162#define RT5677_DSP_INB_CTRL1 0xa3
163#define RT5677_DSP_INB_CTRL2 0xa4
164#define RT5677_DSP_IN_OUTB_CTRL 0xa5
165#define RT5677_DSP_OUTB0_1_DIG_VOL 0xa6
166#define RT5677_DSP_OUTB2_3_DIG_VOL 0xa7
167#define RT5677_DSP_OUTB4_5_DIG_VOL 0xa8
168#define RT5677_DSP_OUTB6_7_DIG_VOL 0xa9
169#define RT5677_ADC_EQ_CTRL1 0xae
170#define RT5677_ADC_EQ_CTRL2 0xaf
171#define RT5677_EQ_CTRL1 0xb0
172#define RT5677_EQ_CTRL2 0xb1
173#define RT5677_EQ_CTRL3 0xb2
174#define RT5677_SOFT_VOL_ZERO_CROSS1 0xb3
175#define RT5677_JD_CTRL1 0xb5
176#define RT5677_JD_CTRL2 0xb6
177#define RT5677_JD_CTRL3 0xb8
178#define RT5677_IRQ_CTRL1 0xbd
179#define RT5677_IRQ_CTRL2 0xbe
180#define RT5677_GPIO_ST 0xbf
181#define RT5677_GPIO_CTRL1 0xc0
182#define RT5677_GPIO_CTRL2 0xc1
183#define RT5677_GPIO_CTRL3 0xc2
184#define RT5677_STO1_ADC_HI_FILTER1 0xc5
185#define RT5677_STO1_ADC_HI_FILTER2 0xc6
186#define RT5677_MONO_ADC_HI_FILTER1 0xc7
187#define RT5677_MONO_ADC_HI_FILTER2 0xc8
188#define RT5677_STO2_ADC_HI_FILTER1 0xc9
189#define RT5677_STO2_ADC_HI_FILTER2 0xca
190#define RT5677_STO3_ADC_HI_FILTER1 0xcb
191#define RT5677_STO3_ADC_HI_FILTER2 0xcc
192#define RT5677_STO4_ADC_HI_FILTER1 0xcd
193#define RT5677_STO4_ADC_HI_FILTER2 0xce
194#define RT5677_MB_DRC_CTRL1 0xd0
195#define RT5677_DRC1_CTRL1 0xd2
196#define RT5677_DRC1_CTRL2 0xd3
197#define RT5677_DRC1_CTRL3 0xd4
198#define RT5677_DRC1_CTRL4 0xd5
199#define RT5677_DRC1_CTRL5 0xd6
200#define RT5677_DRC1_CTRL6 0xd7
201#define RT5677_DRC2_CTRL1 0xd8
202#define RT5677_DRC2_CTRL2 0xd9
203#define RT5677_DRC2_CTRL3 0xda
204#define RT5677_DRC2_CTRL4 0xdb
205#define RT5677_DRC2_CTRL5 0xdc
206#define RT5677_DRC2_CTRL6 0xdd
207#define RT5677_DRC1_HL_CTRL1 0xde
208#define RT5677_DRC1_HL_CTRL2 0xdf
209#define RT5677_DRC2_HL_CTRL1 0xe0
210#define RT5677_DRC2_HL_CTRL2 0xe1
211#define RT5677_DSP_INB1_SRC_CTRL1 0xe3
212#define RT5677_DSP_INB1_SRC_CTRL2 0xe4
213#define RT5677_DSP_INB1_SRC_CTRL3 0xe5
214#define RT5677_DSP_INB1_SRC_CTRL4 0xe6
215#define RT5677_DSP_INB2_SRC_CTRL1 0xe7
216#define RT5677_DSP_INB2_SRC_CTRL2 0xe8
217#define RT5677_DSP_INB2_SRC_CTRL3 0xe9
218#define RT5677_DSP_INB2_SRC_CTRL4 0xea
219#define RT5677_DSP_INB3_SRC_CTRL1 0xeb
220#define RT5677_DSP_INB3_SRC_CTRL2 0xec
221#define RT5677_DSP_INB3_SRC_CTRL3 0xed
222#define RT5677_DSP_INB3_SRC_CTRL4 0xee
223#define RT5677_DSP_OUTB1_SRC_CTRL1 0xef
224#define RT5677_DSP_OUTB1_SRC_CTRL2 0xf0
225#define RT5677_DSP_OUTB1_SRC_CTRL3 0xf1
226#define RT5677_DSP_OUTB1_SRC_CTRL4 0xf2
227#define RT5677_DSP_OUTB2_SRC_CTRL1 0xf3
228#define RT5677_DSP_OUTB2_SRC_CTRL2 0xf4
229#define RT5677_DSP_OUTB2_SRC_CTRL3 0xf5
230#define RT5677_DSP_OUTB2_SRC_CTRL4 0xf6
231
232/* Virtual DSP Mixer Control */
233#define RT5677_DSP_OUTB_0123_MIXER_CTRL 0xf7
234#define RT5677_DSP_OUTB_45_MIXER_CTRL 0xf8
235#define RT5677_DSP_OUTB_67_MIXER_CTRL 0xf9
236
237/* General Control */
238#define RT5677_DIG_MISC 0xfa
239#define RT5677_GEN_CTRL1 0xfb
240#define RT5677_GEN_CTRL2 0xfc
241
242/* DSP Mode I2C Control*/
243#define RT5677_DSP_I2C_OP_CODE 0x00
244#define RT5677_DSP_I2C_ADDR_LSB 0x01
245#define RT5677_DSP_I2C_ADDR_MSB 0x02
246#define RT5677_DSP_I2C_DATA_LSB 0x03
247#define RT5677_DSP_I2C_DATA_MSB 0x04
248
249/* Index of Codec Private Register definition */
250#define RT5677_PR_DRC1_CTRL_1 0x01
251#define RT5677_PR_DRC1_CTRL_2 0x02
252#define RT5677_PR_DRC1_CTRL_3 0x03
253#define RT5677_PR_DRC1_CTRL_4 0x04
254#define RT5677_PR_DRC1_CTRL_5 0x05
255#define RT5677_PR_DRC1_CTRL_6 0x06
256#define RT5677_PR_DRC1_CTRL_7 0x07
257#define RT5677_PR_DRC2_CTRL_1 0x08
258#define RT5677_PR_DRC2_CTRL_2 0x09
259#define RT5677_PR_DRC2_CTRL_3 0x0a
260#define RT5677_PR_DRC2_CTRL_4 0x0b
261#define RT5677_PR_DRC2_CTRL_5 0x0c
262#define RT5677_PR_DRC2_CTRL_6 0x0d
263#define RT5677_PR_DRC2_CTRL_7 0x0e
264#define RT5677_BIAS_CUR1 0x10
265#define RT5677_BIAS_CUR2 0x12
266#define RT5677_BIAS_CUR3 0x13
267#define RT5677_BIAS_CUR4 0x14
268#define RT5677_BIAS_CUR5 0x15
269#define RT5677_VREF_LOUT_CTRL 0x17
270#define RT5677_DIG_VOL_CTRL1 0x1a
271#define RT5677_DIG_VOL_CTRL2 0x1b
272#define RT5677_ANA_ADC_GAIN_CTRL 0x1e
273#define RT5677_VAD_SRAM_TEST1 0x20
274#define RT5677_VAD_SRAM_TEST2 0x21
275#define RT5677_VAD_SRAM_TEST3 0x22
276#define RT5677_VAD_SRAM_TEST4 0x23
277#define RT5677_PAD_DRV_CTRL 0x26
278#define RT5677_DIG_IN_PIN_ST_CTRL1 0x29
279#define RT5677_DIG_IN_PIN_ST_CTRL2 0x2a
280#define RT5677_DIG_IN_PIN_ST_CTRL3 0x2b
281#define RT5677_PLL1_INT 0x38
282#define RT5677_PLL2_INT 0x39
283#define RT5677_TEST_CTRL1 0x3a
284#define RT5677_TEST_CTRL2 0x3b
285#define RT5677_TEST_CTRL3 0x3c
286#define RT5677_CHOP_DAC_ADC 0x3d
287#define RT5677_SOFT_DEPOP_DAC_CLK_CTRL 0x3e
288#define RT5677_CROSS_OVER_FILTER1 0x90
289#define RT5677_CROSS_OVER_FILTER2 0x91
290#define RT5677_CROSS_OVER_FILTER3 0x92
291#define RT5677_CROSS_OVER_FILTER4 0x93
292#define RT5677_CROSS_OVER_FILTER5 0x94
293#define RT5677_CROSS_OVER_FILTER6 0x95
294#define RT5677_CROSS_OVER_FILTER7 0x96
295#define RT5677_CROSS_OVER_FILTER8 0x97
296#define RT5677_CROSS_OVER_FILTER9 0x98
297#define RT5677_CROSS_OVER_FILTER10 0x99
298
299/* global definition */
300#define RT5677_L_MUTE (0x1 << 15)
301#define RT5677_L_MUTE_SFT 15
302#define RT5677_VOL_L_MUTE (0x1 << 14)
303#define RT5677_VOL_L_SFT 14
304#define RT5677_R_MUTE (0x1 << 7)
305#define RT5677_R_MUTE_SFT 7
306#define RT5677_VOL_R_MUTE (0x1 << 6)
307#define RT5677_VOL_R_SFT 6
308#define RT5677_L_VOL_MASK (0x3f << 8)
309#define RT5677_L_VOL_SFT 8
310#define RT5677_R_VOL_MASK (0x3f)
311#define RT5677_R_VOL_SFT 0
312
313/* LOUT1 Control (0x01) */
314#define RT5677_LOUT1_L_MUTE (0x1 << 15)
315#define RT5677_LOUT1_L_MUTE_SFT (15)
316#define RT5677_LOUT1_L_DF (0x1 << 14)
317#define RT5677_LOUT1_L_DF_SFT (14)
318#define RT5677_LOUT2_L_MUTE (0x1 << 13)
319#define RT5677_LOUT2_L_MUTE_SFT (13)
320#define RT5677_LOUT2_L_DF (0x1 << 12)
321#define RT5677_LOUT2_L_DF_SFT (12)
322#define RT5677_LOUT3_L_MUTE (0x1 << 11)
323#define RT5677_LOUT3_L_MUTE_SFT (11)
324#define RT5677_LOUT3_L_DF (0x1 << 10)
325#define RT5677_LOUT3_L_DF_SFT (10)
326#define RT5677_LOUT1_ENH_DRV (0x1 << 9)
327#define RT5677_LOUT1_ENH_DRV_SFT (9)
328#define RT5677_LOUT2_ENH_DRV (0x1 << 8)
329#define RT5677_LOUT2_ENH_DRV_SFT (8)
330#define RT5677_LOUT3_ENH_DRV (0x1 << 7)
331#define RT5677_LOUT3_ENH_DRV_SFT (7)
332
333/* IN1 Control (0x03) */
334#define RT5677_BST_MASK1 (0xf << 12)
335#define RT5677_BST_SFT1 12
336#define RT5677_BST_MASK2 (0xf << 8)
337#define RT5677_BST_SFT2 8
338#define RT5677_IN_DF1 (0x1 << 7)
339#define RT5677_IN_DF1_SFT 7
340#define RT5677_IN_DF2 (0x1 << 6)
341#define RT5677_IN_DF2_SFT 6
342
343/* Micbias Control (0x04) */
344#define RT5677_MICBIAS1_OUTVOLT_MASK (0x1 << 15)
345#define RT5677_MICBIAS1_OUTVOLT_SFT (15)
346#define RT5677_MICBIAS1_OUTVOLT_2_7V (0x0 << 15)
347#define RT5677_MICBIAS1_OUTVOLT_2_25V (0x1 << 15)
348#define RT5677_MICBIAS1_CTRL_VDD_MASK (0x1 << 14)
349#define RT5677_MICBIAS1_CTRL_VDD_SFT (14)
350#define RT5677_MICBIAS1_CTRL_VDD_1_8V (0x0 << 14)
351#define RT5677_MICBIAS1_CTRL_VDD_3_3V (0x1 << 14)
352#define RT5677_MICBIAS1_OVCD_MASK (0x1 << 11)
353#define RT5677_MICBIAS1_OVCD_SHIFT (11)
354#define RT5677_MICBIAS1_OVCD_DIS (0x0 << 11)
355#define RT5677_MICBIAS1_OVCD_EN (0x1 << 11)
356#define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
357#define RT5677_MICBIAS1_OVTH_SFT 9
358#define RT5677_MICBIAS1_OVTH_640UA (0x0 << 9)
359#define RT5677_MICBIAS1_OVTH_1280UA (0x1 << 9)
360#define RT5677_MICBIAS1_OVTH_1920UA (0x2 << 9)
361
362/* SLIMbus Parameter (0x07) */
363
364/* SLIMbus Rx (0x08) */
365#define RT5677_SLB_ADC4_MASK (0x3 << 6)
366#define RT5677_SLB_ADC4_SFT 6
367#define RT5677_SLB_ADC3_MASK (0x3 << 4)
368#define RT5677_SLB_ADC3_SFT 4
369#define RT5677_SLB_ADC2_MASK (0x3 << 2)
370#define RT5677_SLB_ADC2_SFT 2
371#define RT5677_SLB_ADC1_MASK (0x3 << 0)
372#define RT5677_SLB_ADC1_SFT 0
373
374/* SLIMBus control (0x09) */
375
376/* Sidetone Control (0x13) */
377#define RT5677_ST_HPF_SEL_MASK (0x7 << 13)
378#define RT5677_ST_HPF_SEL_SFT 13
379#define RT5677_ST_HPF_PATH (0x1 << 12)
380#define RT5677_ST_HPF_PATH_SFT 12
381#define RT5677_ST_SEL_MASK (0x7 << 9)
382#define RT5677_ST_SEL_SFT 9
383#define RT5677_ST_EN (0x1 << 6)
384#define RT5677_ST_EN_SFT 6
385
386/* Analog DAC1/2/3 Source Control (0x15) */
387#define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
388#define RT5677_ANA_DAC3_SRC_SEL_SFT 4
389#define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
390#define RT5677_ANA_DAC1_2_SRC_SEL_SFT 0
391
392/* IF/DSP to DAC3/4 Mixer Control (0x16) */
393#define RT5677_M_DAC4_L_VOL (0x1 << 15)
394#define RT5677_M_DAC4_L_VOL_SFT 15
395#define RT5677_SEL_DAC4_L_SRC_MASK (0x7 << 12)
396#define RT5677_SEL_DAC4_L_SRC_SFT 12
397#define RT5677_M_DAC4_R_VOL (0x1 << 11)
398#define RT5677_M_DAC4_R_VOL_SFT 11
399#define RT5677_SEL_DAC4_R_SRC_MASK (0x7 << 8)
400#define RT5677_SEL_DAC4_R_SRC_SFT 8
401#define RT5677_M_DAC3_L_VOL (0x1 << 7)
402#define RT5677_M_DAC3_L_VOL_SFT 7
403#define RT5677_SEL_DAC3_L_SRC_MASK (0x7 << 4)
404#define RT5677_SEL_DAC3_L_SRC_SFT 4
405#define RT5677_M_DAC3_R_VOL (0x1 << 3)
406#define RT5677_M_DAC3_R_VOL_SFT 3
407#define RT5677_SEL_DAC3_R_SRC_MASK (0x7 << 0)
408#define RT5677_SEL_DAC3_R_SRC_SFT 0
409
410/* DAC4 Digital Volume (0x17) */
411#define RT5677_DAC4_L_VOL_MASK (0xff << 8)
412#define RT5677_DAC4_L_VOL_SFT 8
413#define RT5677_DAC4_R_VOL_MASK (0xff)
414#define RT5677_DAC4_R_VOL_SFT 0
415
416/* DAC3 Digital Volume (0x18) */
417#define RT5677_DAC3_L_VOL_MASK (0xff << 8)
418#define RT5677_DAC3_L_VOL_SFT 8
419#define RT5677_DAC3_R_VOL_MASK (0xff)
420#define RT5677_DAC3_R_VOL_SFT 0
421
422/* DAC3 Digital Volume (0x19) */
423#define RT5677_DAC1_L_VOL_MASK (0xff << 8)
424#define RT5677_DAC1_L_VOL_SFT 8
425#define RT5677_DAC1_R_VOL_MASK (0xff)
426#define RT5677_DAC1_R_VOL_SFT 0
427
428/* DAC2 Digital Volume (0x1a) */
429#define RT5677_DAC2_L_VOL_MASK (0xff << 8)
430#define RT5677_DAC2_L_VOL_SFT 8
431#define RT5677_DAC2_R_VOL_MASK (0xff)
432#define RT5677_DAC2_R_VOL_SFT 0
433
434/* IF/DSP to DAC2 Mixer Control (0x1b) */
435#define RT5677_M_DAC2_L_VOL (0x1 << 7)
436#define RT5677_M_DAC2_L_VOL_SFT 7
437#define RT5677_SEL_DAC2_L_SRC_MASK (0x7 << 4)
438#define RT5677_SEL_DAC2_L_SRC_SFT 4
439#define RT5677_M_DAC2_R_VOL (0x1 << 3)
440#define RT5677_M_DAC2_R_VOL_SFT 3
441#define RT5677_SEL_DAC2_R_SRC_MASK (0x7 << 0)
442#define RT5677_SEL_DAC2_R_SRC_SFT 0
443
444/* Stereo1 ADC Digital Volume Control (0x1c) */
445#define RT5677_STO1_ADC_L_VOL_MASK (0x7f << 8)
446#define RT5677_STO1_ADC_L_VOL_SFT 8
447#define RT5677_STO1_ADC_R_VOL_MASK (0x7f)
448#define RT5677_STO1_ADC_R_VOL_SFT 0
449
450/* Mono ADC Digital Volume Control (0x1d) */
451#define RT5677_MONO_ADC_L_VOL_MASK (0x7f << 8)
452#define RT5677_MONO_ADC_L_VOL_SFT 8
453#define RT5677_MONO_ADC_R_VOL_MASK (0x7f)
454#define RT5677_MONO_ADC_R_VOL_SFT 0
455
456/* Stereo 1/2 ADC Boost Gain Control (0x1e) */
457#define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)
458#define RT5677_STO1_ADC_L_BST_SFT 14
459#define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
460#define RT5677_STO1_ADC_R_BST_SFT 12
461#define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)
462#define RT5677_STO1_ADC_COMP_SFT 10
463#define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
464#define RT5677_STO2_ADC_L_BST_SFT 8
465#define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)
466#define RT5677_STO2_ADC_R_BST_SFT 6
467#define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)
468#define RT5677_STO2_ADC_COMP_SFT 4
469
470/* Stereo2 ADC Digital Volume Control (0x1f) */
471#define RT5677_STO2_ADC_L_VOL_MASK (0x7f << 8)
472#define RT5677_STO2_ADC_L_VOL_SFT 8
473#define RT5677_STO2_ADC_R_VOL_MASK (0x7f)
474#define RT5677_STO2_ADC_R_VOL_SFT 0
475
476/* ADC Boost Gain Control 2 (0x20) */
477#define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)
478#define RT5677_MONO_ADC_L_BST_SFT 14
479#define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
480#define RT5677_MONO_ADC_R_BST_SFT 12
481#define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)
482#define RT5677_MONO_ADC_COMP_SFT 10
483
484/* Stereo 3/4 ADC Boost Gain Control (0x21) */
485#define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)
486#define RT5677_STO3_ADC_L_BST_SFT 14
487#define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
488#define RT5677_STO3_ADC_R_BST_SFT 12
489#define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)
490#define RT5677_STO3_ADC_COMP_SFT 10
491#define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
492#define RT5677_STO4_ADC_L_BST_SFT 8
493#define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)
494#define RT5677_STO4_ADC_R_BST_SFT 6
495#define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)
496#define RT5677_STO4_ADC_COMP_SFT 4
497
498/* Stereo3 ADC Digital Volume Control (0x22) */
499#define RT5677_STO3_ADC_L_VOL_MASK (0x7f << 8)
500#define RT5677_STO3_ADC_L_VOL_SFT 8
501#define RT5677_STO3_ADC_R_VOL_MASK (0x7f)
502#define RT5677_STO3_ADC_R_VOL_SFT 0
503
504/* Stereo4 ADC Digital Volume Control (0x23) */
505#define RT5677_STO4_ADC_L_VOL_MASK (0x7f << 8)
506#define RT5677_STO4_ADC_L_VOL_SFT 8
507#define RT5677_STO4_ADC_R_VOL_MASK (0x7f)
508#define RT5677_STO4_ADC_R_VOL_SFT 0
509
510/* Stereo4 ADC Mixer control (0x24) */
511#define RT5677_M_STO4_ADC_L2 (0x1 << 15)
512#define RT5677_M_STO4_ADC_L2_SFT 15
513#define RT5677_M_STO4_ADC_L1 (0x1 << 14)
514#define RT5677_M_STO4_ADC_L1_SFT 14
515#define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
516#define RT5677_SEL_STO4_ADC1_SFT 12
517#define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)
518#define RT5677_SEL_STO4_ADC2_SFT 10
519#define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
520#define RT5677_SEL_STO4_DMIC_SFT 8
521#define RT5677_M_STO4_ADC_R1 (0x1 << 7)
522#define RT5677_M_STO4_ADC_R1_SFT 7
523#define RT5677_M_STO4_ADC_R2 (0x1 << 6)
524#define RT5677_M_STO4_ADC_R2_SFT 6
525
526/* Stereo3 ADC Mixer control (0x25) */
527#define RT5677_M_STO3_ADC_L2 (0x1 << 15)
528#define RT5677_M_STO3_ADC_L2_SFT 15
529#define RT5677_M_STO3_ADC_L1 (0x1 << 14)
530#define RT5677_M_STO3_ADC_L1_SFT 14
531#define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
532#define RT5677_SEL_STO3_ADC1_SFT 12
533#define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)
534#define RT5677_SEL_STO3_ADC2_SFT 10
535#define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
536#define RT5677_SEL_STO3_DMIC_SFT 8
537#define RT5677_M_STO3_ADC_R1 (0x1 << 7)
538#define RT5677_M_STO3_ADC_R1_SFT 7
539#define RT5677_M_STO3_ADC_R2 (0x1 << 6)
540#define RT5677_M_STO3_ADC_R2_SFT 6
541
542/* Stereo2 ADC Mixer Control (0x26) */
543#define RT5677_M_STO2_ADC_L2 (0x1 << 15)
544#define RT5677_M_STO2_ADC_L2_SFT 15
545#define RT5677_M_STO2_ADC_L1 (0x1 << 14)
546#define RT5677_M_STO2_ADC_L1_SFT 14
547#define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
548#define RT5677_SEL_STO2_ADC1_SFT 12
549#define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)
550#define RT5677_SEL_STO2_ADC2_SFT 10
551#define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
552#define RT5677_SEL_STO2_DMIC_SFT 8
553#define RT5677_M_STO2_ADC_R1 (0x1 << 7)
554#define RT5677_M_STO2_ADC_R1_SFT 7
555#define RT5677_M_STO2_ADC_R2 (0x1 << 6)
556#define RT5677_M_STO2_ADC_R2_SFT 6
557#define RT5677_SEL_STO2_LR_MIX_MASK (0x1 << 0)
558#define RT5677_SEL_STO2_LR_MIX_SFT 0
559#define RT5677_SEL_STO2_LR_MIX_L (0x0 << 0)
560#define RT5677_SEL_STO2_LR_MIX_LR (0x1 << 0)
561
562/* Stereo1 ADC Mixer control (0x27) */
563#define RT5677_M_STO1_ADC_L2 (0x1 << 15)
564#define RT5677_M_STO1_ADC_L2_SFT 15
565#define RT5677_M_STO1_ADC_L1 (0x1 << 14)
566#define RT5677_M_STO1_ADC_L1_SFT 14
567#define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
568#define RT5677_SEL_STO1_ADC1_SFT 12
569#define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)
570#define RT5677_SEL_STO1_ADC2_SFT 10
571#define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
572#define RT5677_SEL_STO1_DMIC_SFT 8
573#define RT5677_M_STO1_ADC_R1 (0x1 << 7)
574#define RT5677_M_STO1_ADC_R1_SFT 7
575#define RT5677_M_STO1_ADC_R2 (0x1 << 6)
576#define RT5677_M_STO1_ADC_R2_SFT 6
577
578/* Mono ADC Mixer control (0x28) */
579#define RT5677_M_MONO_ADC_L2 (0x1 << 15)
580#define RT5677_M_MONO_ADC_L2_SFT 15
581#define RT5677_M_MONO_ADC_L1 (0x1 << 14)
582#define RT5677_M_MONO_ADC_L1_SFT 14
583#define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
584#define RT5677_SEL_MONO_ADC_L1_SFT 12
585#define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)
586#define RT5677_SEL_MONO_ADC_L2_SFT 10
587#define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
588#define RT5677_SEL_MONO_DMIC_L_SFT 8
589#define RT5677_M_MONO_ADC_R1 (0x1 << 7)
590#define RT5677_M_MONO_ADC_R1_SFT 7
591#define RT5677_M_MONO_ADC_R2 (0x1 << 6)
592#define RT5677_M_MONO_ADC_R2_SFT 6
593#define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)
594#define RT5677_SEL_MONO_ADC_R1_SFT 4
595#define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)
596#define RT5677_SEL_MONO_ADC_R2_SFT 2
597#define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)
598#define RT5677_SEL_MONO_DMIC_R_SFT 0
599
600/* ADC/IF/DSP to DAC1 Mixer control (0x29) */
601#define RT5677_M_ADDA_MIXER1_L (0x1 << 15)
602#define RT5677_M_ADDA_MIXER1_L_SFT 15
603#define RT5677_M_DAC1_L (0x1 << 14)
604#define RT5677_M_DAC1_L_SFT 14
605#define RT5677_DAC1_L_SEL_MASK (0x7 << 8)
606#define RT5677_DAC1_L_SEL_SFT 8
607#define RT5677_M_ADDA_MIXER1_R (0x1 << 7)
608#define RT5677_M_ADDA_MIXER1_R_SFT 7
609#define RT5677_M_DAC1_R (0x1 << 6)
610#define RT5677_M_DAC1_R_SFT 6
611#define RT5677_ADDA1_SEL_MASK (0x3 << 0)
612#define RT5677_ADDA1_SEL_SFT 0
613
614/* Stereo1 DAC Mixer L/R Control (0x2a) */
615#define RT5677_M_ST_DAC1_L (0x1 << 15)
616#define RT5677_M_ST_DAC1_L_SFT 15
617#define RT5677_M_DAC1_L_STO_L (0x1 << 13)
618#define RT5677_M_DAC1_L_STO_L_SFT 13
619#define RT5677_DAC1_L_STO_L_VOL_MASK (0x1 << 12)
620#define RT5677_DAC1_L_STO_L_VOL_SFT 12
621#define RT5677_M_DAC2_L_STO_L (0x1 << 11)
622#define RT5677_M_DAC2_L_STO_L_SFT 11
623#define RT5677_DAC2_L_STO_L_VOL_MASK (0x1 << 10)
624#define RT5677_DAC2_L_STO_L_VOL_SFT 10
625#define RT5677_M_DAC1_R_STO_L (0x1 << 9)
626#define RT5677_M_DAC1_R_STO_L_SFT 9
627#define RT5677_DAC1_R_STO_L_VOL_MASK (0x1 << 8)
628#define RT5677_DAC1_R_STO_L_VOL_SFT 8
629#define RT5677_M_ST_DAC1_R (0x1 << 7)
630#define RT5677_M_ST_DAC1_R_SFT 7
631#define RT5677_M_DAC1_R_STO_R (0x1 << 5)
632#define RT5677_M_DAC1_R_STO_R_SFT 5
633#define RT5677_DAC1_R_STO_R_VOL_MASK (0x1 << 4)
634#define RT5677_DAC1_R_STO_R_VOL_SFT 4
635#define RT5677_M_DAC2_R_STO_R (0x1 << 3)
636#define RT5677_M_DAC2_R_STO_R_SFT 3
637#define RT5677_DAC2_R_STO_R_VOL_MASK (0x1 << 2)
638#define RT5677_DAC2_R_STO_R_VOL_SFT 2
639#define RT5677_M_DAC1_L_STO_R (0x1 << 1)
640#define RT5677_M_DAC1_L_STO_R_SFT 1
641#define RT5677_DAC1_L_STO_R_VOL_MASK (0x1 << 0)
642#define RT5677_DAC1_L_STO_R_VOL_SFT 0
643
644/* Mono DAC Mixer L/R Control (0x2b) */
645#define RT5677_M_ST_DAC2_L (0x1 << 15)
646#define RT5677_M_ST_DAC2_L_SFT 15
647#define RT5677_M_DAC2_L_MONO_L (0x1 << 13)
648#define RT5677_M_DAC2_L_MONO_L_SFT 13
649#define RT5677_DAC2_L_MONO_L_VOL_MASK (0x1 << 12)
650#define RT5677_DAC2_L_MONO_L_VOL_SFT 12
651#define RT5677_M_DAC2_R_MONO_L (0x1 << 11)
652#define RT5677_M_DAC2_R_MONO_L_SFT 11
653#define RT5677_DAC2_R_MONO_L_VOL_MASK (0x1 << 10)
654#define RT5677_DAC2_R_MONO_L_VOL_SFT 10
655#define RT5677_M_DAC1_L_MONO_L (0x1 << 9)
656#define RT5677_M_DAC1_L_MONO_L_SFT 9
657#define RT5677_DAC1_L_MONO_L_VOL_MASK (0x1 << 8)
658#define RT5677_DAC1_L_MONO_L_VOL_SFT 8
659#define RT5677_M_ST_DAC2_R (0x1 << 7)
660#define RT5677_M_ST_DAC2_R_SFT 7
661#define RT5677_M_DAC2_R_MONO_R (0x1 << 5)
662#define RT5677_M_DAC2_R_MONO_R_SFT 5
663#define RT5677_DAC2_R_MONO_R_VOL_MASK (0x1 << 4)
664#define RT5677_DAC2_R_MONO_R_VOL_SFT 4
665#define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
666#define RT5677_M_DAC1_R_MONO_R_SFT 3
667#define RT5677_DAC1_R_MONO_R_VOL_MASK (0x1 << 2)
668#define RT5677_DAC1_R_MONO_R_VOL_SFT 2
669#define RT5677_M_DAC2_L_MONO_R (0x1 << 1)
670#define RT5677_M_DAC2_L_MONO_R_SFT 1
671#define RT5677_DAC2_L_MONO_R_VOL_MASK (0x1 << 0)
672#define RT5677_DAC2_L_MONO_R_VOL_SFT 0
673
674/* DD Mixer 1 Control (0x2c) */
675#define RT5677_M_STO_L_DD1_L (0x1 << 15)
676#define RT5677_M_STO_L_DD1_L_SFT 15
677#define RT5677_STO_L_DD1_L_VOL_MASK (0x1 << 14)
678#define RT5677_STO_L_DD1_L_VOL_SFT 14
679#define RT5677_M_MONO_L_DD1_L (0x1 << 13)
680#define RT5677_M_MONO_L_DD1_L_SFT 13
681#define RT5677_MONO_L_DD1_L_VOL_MASK (0x1 << 12)
682#define RT5677_MONO_L_DD1_L_VOL_SFT 12
683#define RT5677_M_DAC3_L_DD1_L (0x1 << 11)
684#define RT5677_M_DAC3_L_DD1_L_SFT 11
685#define RT5677_DAC3_L_DD1_L_VOL_MASK (0x1 << 10)
686#define RT5677_DAC3_L_DD1_L_VOL_SFT 10
687#define RT5677_M_DAC3_R_DD1_L (0x1 << 9)
688#define RT5677_M_DAC3_R_DD1_L_SFT 9
689#define RT5677_DAC3_R_DD1_L_VOL_MASK (0x1 << 8)
690#define RT5677_DAC3_R_DD1_L_VOL_SFT 8
691#define RT5677_M_STO_R_DD1_R (0x1 << 7)
692#define RT5677_M_STO_R_DD1_R_SFT 7
693#define RT5677_STO_R_DD1_R_VOL_MASK (0x1 << 6)
694#define RT5677_STO_R_DD1_R_VOL_SFT 6
695#define RT5677_M_MONO_R_DD1_R (0x1 << 5)
696#define RT5677_M_MONO_R_DD1_R_SFT 5
697#define RT5677_MONO_R_DD1_R_VOL_MASK (0x1 << 4)
698#define RT5677_MONO_R_DD1_R_VOL_SFT 4
699#define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
700#define RT5677_M_DAC3_R_DD1_R_SFT 3
701#define RT5677_DAC3_R_DD1_R_VOL_MASK (0x1 << 2)
702#define RT5677_DAC3_R_DD1_R_VOL_SFT 2
703#define RT5677_M_DAC3_L_DD1_R (0x1 << 1)
704#define RT5677_M_DAC3_L_DD1_R_SFT 1
705#define RT5677_DAC3_L_DD1_R_VOL_MASK (0x1 << 0)
706#define RT5677_DAC3_L_DD1_R_VOL_SFT 0
707
708/* DD Mixer 2 Control (0x2d) */
709#define RT5677_M_STO_L_DD2_L (0x1 << 15)
710#define RT5677_M_STO_L_DD2_L_SFT 15
711#define RT5677_STO_L_DD2_L_VOL_MASK (0x1 << 14)
712#define RT5677_STO_L_DD2_L_VOL_SFT 14
713#define RT5677_M_MONO_L_DD2_L (0x1 << 13)
714#define RT5677_M_MONO_L_DD2_L_SFT 13
715#define RT5677_MONO_L_DD2_L_VOL_MASK (0x1 << 12)
716#define RT5677_MONO_L_DD2_L_VOL_SFT 12
717#define RT5677_M_DAC4_L_DD2_L (0x1 << 11)
718#define RT5677_M_DAC4_L_DD2_L_SFT 11
719#define RT5677_DAC4_L_DD2_L_VOL_MASK (0x1 << 10)
720#define RT5677_DAC4_L_DD2_L_VOL_SFT 10
721#define RT5677_M_DAC4_R_DD2_L (0x1 << 9)
722#define RT5677_M_DAC4_R_DD2_L_SFT 9
723#define RT5677_DAC4_R_DD2_L_VOL_MASK (0x1 << 8)
724#define RT5677_DAC4_R_DD2_L_VOL_SFT 8
725#define RT5677_M_STO_R_DD2_R (0x1 << 7)
726#define RT5677_M_STO_R_DD2_R_SFT 7
727#define RT5677_STO_R_DD2_R_VOL_MASK (0x1 << 6)
728#define RT5677_STO_R_DD2_R_VOL_SFT 6
729#define RT5677_M_MONO_R_DD2_R (0x1 << 5)
730#define RT5677_M_MONO_R_DD2_R_SFT 5
731#define RT5677_MONO_R_DD2_R_VOL_MASK (0x1 << 4)
732#define RT5677_MONO_R_DD2_R_VOL_SFT 4
733#define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
734#define RT5677_M_DAC4_R_DD2_R_SFT 3
735#define RT5677_DAC4_R_DD2_R_VOL_MASK (0x1 << 2)
736#define RT5677_DAC4_R_DD2_R_VOL_SFT 2
737#define RT5677_M_DAC4_L_DD2_R (0x1 << 1)
738#define RT5677_M_DAC4_L_DD2_R_SFT 1
739#define RT5677_DAC4_L_DD2_R_VOL_MASK (0x1 << 0)
740#define RT5677_DAC4_L_DD2_R_VOL_SFT 0
741
742/* IF3 data control (0x2f) */
743#define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)
744#define RT5677_IF3_DAC_SEL_SFT 6
745#define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)
746#define RT5677_IF3_ADC_SEL_SFT 4
747#define RT5677_IF3_ADC_IN_MASK (0xf << 0)
748#define RT5677_IF3_ADC_IN_SFT 0
749
750/* IF4 data control (0x30) */
751#define RT5677_IF4_ADC_IN_MASK (0xf << 4)
752#define RT5677_IF4_ADC_IN_SFT 4
753#define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)
754#define RT5677_IF4_DAC_SEL_SFT 2
755#define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)
756#define RT5677_IF4_ADC_SEL_SFT 0
757
758/* PDM Output Control (0x31) */
759#define RT5677_M_PDM1_L (0x1 << 15)
760#define RT5677_M_PDM1_L_SFT 15
761#define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
762#define RT5677_SEL_PDM1_L_SFT 12
763#define RT5677_M_PDM1_R (0x1 << 11)
764#define RT5677_M_PDM1_R_SFT 11
765#define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
766#define RT5677_SEL_PDM1_R_SFT 8
767#define RT5677_M_PDM2_L (0x1 << 7)
768#define RT5677_M_PDM2_L_SFT 7
769#define RT5677_SEL_PDM2_L_MASK (0x3 << 4)
770#define RT5677_SEL_PDM2_L_SFT 4
771#define RT5677_M_PDM2_R (0x1 << 3)
772#define RT5677_M_PDM2_R_SFT 3
773#define RT5677_SEL_PDM2_R_MASK (0x3 << 0)
774#define RT5677_SEL_PDM2_R_SFT 0
775
776/* PDM I2C / Data Control 1 (0x32) */
777#define RT5677_PDM2_PW_DOWN (0x1 << 7)
778#define RT5677_PDM1_PW_DOWN (0x1 << 6)
779#define RT5677_PDM2_BUSY (0x1 << 5)
780#define RT5677_PDM1_BUSY (0x1 << 4)
781#define RT5677_PDM_PATTERN (0x1 << 3)
782#define RT5677_PDM_GAIN (0x1 << 2)
783#define RT5677_PDM_DIV_MASK (0x3 << 0)
784
785/* PDM I2C / Data Control 2 (0x33) */
786#define RT5677_PDM1_I2C_ID (0xf << 12)
787#define RT5677_PDM1_EXE (0x1 << 11)
788#define RT5677_PDM1_I2C_CMD (0x1 << 10)
789#define RT5677_PDM1_I2C_EXE (0x1 << 9)
790#define RT5677_PDM1_I2C_BUSY (0x1 << 8)
791#define RT5677_PDM2_I2C_ID (0xf << 4)
792#define RT5677_PDM2_EXE (0x1 << 3)
793#define RT5677_PDM2_I2C_CMD (0x1 << 2)
794#define RT5677_PDM2_I2C_EXE (0x1 << 1)
795#define RT5677_PDM2_I2C_BUSY (0x1 << 0)
796
797/* MX3C TDM1 control 1 (0x3c) */
798#define RT5677_IF1_ADC4_MASK (0x3 << 10)
799#define RT5677_IF1_ADC4_SFT 10
800#define RT5677_IF1_ADC3_MASK (0x3 << 8)
801#define RT5677_IF1_ADC3_SFT 8
802#define RT5677_IF1_ADC2_MASK (0x3 << 6)
803#define RT5677_IF1_ADC2_SFT 6
804#define RT5677_IF1_ADC1_MASK (0x3 << 4)
805#define RT5677_IF1_ADC1_SFT 4
806
807/* MX41 TDM2 control 1 (0x41) */
808#define RT5677_IF2_ADC4_MASK (0x3 << 10)
809#define RT5677_IF2_ADC4_SFT 10
810#define RT5677_IF2_ADC3_MASK (0x3 << 8)
811#define RT5677_IF2_ADC3_SFT 8
812#define RT5677_IF2_ADC2_MASK (0x3 << 6)
813#define RT5677_IF2_ADC2_SFT 6
814#define RT5677_IF2_ADC1_MASK (0x3 << 4)
815#define RT5677_IF2_ADC1_SFT 4
816
817/* Digital Microphone Control 1 (0x50) */
818#define RT5677_DMIC_1_EN_MASK (0x1 << 15)
819#define RT5677_DMIC_1_EN_SFT 15
820#define RT5677_DMIC_1_DIS (0x0 << 15)
821#define RT5677_DMIC_1_EN (0x1 << 15)
822#define RT5677_DMIC_2_EN_MASK (0x1 << 14)
823#define RT5677_DMIC_2_EN_SFT 14
824#define RT5677_DMIC_2_DIS (0x0 << 14)
825#define RT5677_DMIC_2_EN (0x1 << 14)
826#define RT5677_DMIC_L_STO1_LH_MASK (0x1 << 13)
827#define RT5677_DMIC_L_STO1_LH_SFT 13
828#define RT5677_DMIC_L_STO1_LH_FALLING (0x0 << 13)
829#define RT5677_DMIC_L_STO1_LH_RISING (0x1 << 13)
830#define RT5677_DMIC_R_STO1_LH_MASK (0x1 << 12)
831#define RT5677_DMIC_R_STO1_LH_SFT 12
832#define RT5677_DMIC_R_STO1_LH_FALLING (0x0 << 12)
833#define RT5677_DMIC_R_STO1_LH_RISING (0x1 << 12)
834#define RT5677_DMIC_L_STO3_LH_MASK (0x1 << 11)
835#define RT5677_DMIC_L_STO3_LH_SFT 11
836#define RT5677_DMIC_L_STO3_LH_FALLING (0x0 << 11)
837#define RT5677_DMIC_L_STO3_LH_RISING (0x1 << 11)
838#define RT5677_DMIC_R_STO3_LH_MASK (0x1 << 10)
839#define RT5677_DMIC_R_STO3_LH_SFT 10
840#define RT5677_DMIC_R_STO3_LH_FALLING (0x0 << 10)
841#define RT5677_DMIC_R_STO3_LH_RISING (0x1 << 10)
842#define RT5677_DMIC_L_STO2_LH_MASK (0x1 << 9)
843#define RT5677_DMIC_L_STO2_LH_SFT 9
844#define RT5677_DMIC_L_STO2_LH_FALLING (0x0 << 9)
845#define RT5677_DMIC_L_STO2_LH_RISING (0x1 << 9)
846#define RT5677_DMIC_R_STO2_LH_MASK (0x1 << 8)
847#define RT5677_DMIC_R_STO2_LH_SFT 8
848#define RT5677_DMIC_R_STO2_LH_FALLING (0x0 << 8)
849#define RT5677_DMIC_R_STO2_LH_RISING (0x1 << 8)
850#define RT5677_DMIC_CLK_MASK (0x7 << 5)
851#define RT5677_DMIC_CLK_SFT 5
852#define RT5677_DMIC_3_EN_MASK (0x1 << 4)
853#define RT5677_DMIC_3_EN_SFT 4
854#define RT5677_DMIC_3_DIS (0x0 << 4)
855#define RT5677_DMIC_3_EN (0x1 << 4)
856#define RT5677_DMIC_R_MONO_LH_MASK (0x1 << 2)
857#define RT5677_DMIC_R_MONO_LH_SFT 2
858#define RT5677_DMIC_R_MONO_LH_FALLING (0x0 << 2)
859#define RT5677_DMIC_R_MONO_LH_RISING (0x1 << 2)
860#define RT5677_DMIC_L_STO4_LH_MASK (0x1 << 1)
861#define RT5677_DMIC_L_STO4_LH_SFT 1
862#define RT5677_DMIC_L_STO4_LH_FALLING (0x0 << 1)
863#define RT5677_DMIC_L_STO4_LH_RISING (0x1 << 1)
864#define RT5677_DMIC_R_STO4_LH_MASK (0x1 << 0)
865#define RT5677_DMIC_R_STO4_LH_SFT 0
866#define RT5677_DMIC_R_STO4_LH_FALLING (0x0 << 0)
867#define RT5677_DMIC_R_STO4_LH_RISING (0x1 << 0)
868
869/* Digital Microphone Control 2 (0x51) */
870#define RT5677_DMIC_4_EN_MASK (0x1 << 15)
871#define RT5677_DMIC_4_EN_SFT 15
872#define RT5677_DMIC_4_DIS (0x0 << 15)
873#define RT5677_DMIC_4_EN (0x1 << 15)
874#define RT5677_DMIC_4L_LH_MASK (0x1 << 7)
875#define RT5677_DMIC_4L_LH_SFT 7
876#define RT5677_DMIC_4L_LH_FALLING (0x0 << 7)
877#define RT5677_DMIC_4L_LH_RISING (0x1 << 7)
878#define RT5677_DMIC_4R_LH_MASK (0x1 << 6)
879#define RT5677_DMIC_4R_LH_SFT 6
880#define RT5677_DMIC_4R_LH_FALLING (0x0 << 6)
881#define RT5677_DMIC_4R_LH_RISING (0x1 << 6)
882#define RT5677_DMIC_3L_LH_MASK (0x1 << 5)
883#define RT5677_DMIC_3L_LH_SFT 5
884#define RT5677_DMIC_3L_LH_FALLING (0x0 << 5)
885#define RT5677_DMIC_3L_LH_RISING (0x1 << 5)
886#define RT5677_DMIC_3R_LH_MASK (0x1 << 4)
887#define RT5677_DMIC_3R_LH_SFT 4
888#define RT5677_DMIC_3R_LH_FALLING (0x0 << 4)
889#define RT5677_DMIC_3R_LH_RISING (0x1 << 4)
890#define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
891#define RT5677_DMIC_2L_LH_SFT 3
892#define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)
893#define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
894#define RT5677_DMIC_2R_LH_MASK (0x1 << 2)
895#define RT5677_DMIC_2R_LH_SFT 2
896#define RT5677_DMIC_2R_LH_FALLING (0x0 << 2)
897#define RT5677_DMIC_2R_LH_RISING (0x1 << 2)
898#define RT5677_DMIC_1L_LH_MASK (0x1 << 1)
899#define RT5677_DMIC_1L_LH_SFT 1
900#define RT5677_DMIC_1L_LH_FALLING (0x0 << 1)
901#define RT5677_DMIC_1L_LH_RISING (0x1 << 1)
902#define RT5677_DMIC_1R_LH_MASK (0x1 << 0)
903#define RT5677_DMIC_1R_LH_SFT 0
904#define RT5677_DMIC_1R_LH_FALLING (0x0 << 0)
905#define RT5677_DMIC_1R_LH_RISING (0x1 << 0)
906
907/* Power Management for Digital 1 (0x61) */
908#define RT5677_PWR_I2S1 (0x1 << 15)
909#define RT5677_PWR_I2S1_BIT 15
910#define RT5677_PWR_I2S2 (0x1 << 14)
911#define RT5677_PWR_I2S2_BIT 14
912#define RT5677_PWR_I2S3 (0x1 << 13)
913#define RT5677_PWR_I2S3_BIT 13
914#define RT5677_PWR_DAC1 (0x1 << 12)
915#define RT5677_PWR_DAC1_BIT 12
916#define RT5677_PWR_DAC2 (0x1 << 11)
917#define RT5677_PWR_DAC2_BIT 11
918#define RT5677_PWR_I2S4 (0x1 << 10)
919#define RT5677_PWR_I2S4_BIT 10
920#define RT5677_PWR_SLB (0x1 << 9)
921#define RT5677_PWR_SLB_BIT 9
922#define RT5677_PWR_DAC3 (0x1 << 7)
923#define RT5677_PWR_DAC3_BIT 7
924#define RT5677_PWR_ADCFED2 (0x1 << 4)
925#define RT5677_PWR_ADCFED2_BIT 4
926#define RT5677_PWR_ADCFED1 (0x1 << 3)
927#define RT5677_PWR_ADCFED1_BIT 3
928#define RT5677_PWR_ADC_L (0x1 << 2)
929#define RT5677_PWR_ADC_L_BIT 2
930#define RT5677_PWR_ADC_R (0x1 << 1)
931#define RT5677_PWR_ADC_R_BIT 1
932#define RT5677_PWR_I2C_MASTER (0x1 << 0)
933#define RT5677_PWR_I2C_MASTER_BIT 0
934
935/* Power Management for Digital 2 (0x62) */
936#define RT5677_PWR_ADC_S1F (0x1 << 15)
937#define RT5677_PWR_ADC_S1F_BIT 15
938#define RT5677_PWR_ADC_MF_L (0x1 << 14)
939#define RT5677_PWR_ADC_MF_L_BIT 14
940#define RT5677_PWR_ADC_MF_R (0x1 << 13)
941#define RT5677_PWR_ADC_MF_R_BIT 13
942#define RT5677_PWR_DAC_S1F (0x1 << 12)
943#define RT5677_PWR_DAC_S1F_BIT 12
944#define RT5677_PWR_DAC_M2F_L (0x1 << 11)
945#define RT5677_PWR_DAC_M2F_L_BIT 11
946#define RT5677_PWR_DAC_M2F_R (0x1 << 10)
947#define RT5677_PWR_DAC_M2F_R_BIT 10
948#define RT5677_PWR_DAC_M3F_L (0x1 << 9)
949#define RT5677_PWR_DAC_M3F_L_BIT 9
950#define RT5677_PWR_DAC_M3F_R (0x1 << 8)
951#define RT5677_PWR_DAC_M3F_R_BIT 8
952#define RT5677_PWR_DAC_M4F_L (0x1 << 7)
953#define RT5677_PWR_DAC_M4F_L_BIT 7
954#define RT5677_PWR_DAC_M4F_R (0x1 << 6)
955#define RT5677_PWR_DAC_M4F_R_BIT 6
956#define RT5677_PWR_ADC_S2F (0x1 << 5)
957#define RT5677_PWR_ADC_S2F_BIT 5
958#define RT5677_PWR_ADC_S3F (0x1 << 4)
959#define RT5677_PWR_ADC_S3F_BIT 4
960#define RT5677_PWR_ADC_S4F (0x1 << 3)
961#define RT5677_PWR_ADC_S4F_BIT 3
962#define RT5677_PWR_PDM1 (0x1 << 2)
963#define RT5677_PWR_PDM1_BIT 2
964#define RT5677_PWR_PDM2 (0x1 << 1)
965#define RT5677_PWR_PDM2_BIT 1
966
967/* Power Management for Analog 1 (0x63) */
968#define RT5677_PWR_VREF1 (0x1 << 15)
969#define RT5677_PWR_VREF1_BIT 15
970#define RT5677_PWR_FV1 (0x1 << 14)
971#define RT5677_PWR_FV1_BIT 14
972#define RT5677_PWR_MB (0x1 << 13)
973#define RT5677_PWR_MB_BIT 13
974#define RT5677_PWR_LO1 (0x1 << 12)
975#define RT5677_PWR_LO1_BIT 12
976#define RT5677_PWR_BG (0x1 << 11)
977#define RT5677_PWR_BG_BIT 11
978#define RT5677_PWR_LO2 (0x1 << 10)
979#define RT5677_PWR_LO2_BIT 10
980#define RT5677_PWR_LO3 (0x1 << 9)
981#define RT5677_PWR_LO3_BIT 9
982#define RT5677_PWR_VREF2 (0x1 << 8)
983#define RT5677_PWR_VREF2_BIT 8
984#define RT5677_PWR_FV2 (0x1 << 7)
985#define RT5677_PWR_FV2_BIT 7
986#define RT5677_LDO2_SEL_MASK (0x7 << 4)
987#define RT5677_LDO2_SEL_SFT 4
988#define RT5677_LDO1_SEL_MASK (0x7 << 0)
989#define RT5677_LDO1_SEL_SFT 0
990
991/* Power Management for Analog 2 (0x64) */
992#define RT5677_PWR_BST1 (0x1 << 15)
993#define RT5677_PWR_BST1_BIT 15
994#define RT5677_PWR_BST2 (0x1 << 14)
995#define RT5677_PWR_BST2_BIT 14
996#define RT5677_PWR_CLK_MB1 (0x1 << 13)
997#define RT5677_PWR_CLK_MB1_BIT 13
998#define RT5677_PWR_SLIM (0x1 << 12)
999#define RT5677_PWR_SLIM_BIT 12
1000#define RT5677_PWR_MB1 (0x1 << 11)
1001#define RT5677_PWR_MB1_BIT 11
1002#define RT5677_PWR_PP_MB1 (0x1 << 10)
1003#define RT5677_PWR_PP_MB1_BIT 10
1004#define RT5677_PWR_PLL1 (0x1 << 9)
1005#define RT5677_PWR_PLL1_BIT 9
1006#define RT5677_PWR_PLL2 (0x1 << 8)
1007#define RT5677_PWR_PLL2_BIT 8
1008#define RT5677_PWR_CORE (0x1 << 7)
1009#define RT5677_PWR_CORE_BIT 7
1010#define RT5677_PWR_CLK_MB (0x1 << 6)
1011#define RT5677_PWR_CLK_MB_BIT 6
1012#define RT5677_PWR_BST1_P (0x1 << 5)
1013#define RT5677_PWR_BST1_P_BIT 5
1014#define RT5677_PWR_BST2_P (0x1 << 4)
1015#define RT5677_PWR_BST2_P_BIT 4
1016#define RT5677_PWR_IPTV (0x1 << 3)
1017#define RT5677_PWR_IPTV_BIT 3
1018#define RT5677_PWR_25M_CLK (0x1 << 1)
1019#define RT5677_PWR_25M_CLK_BIT 1
1020#define RT5677_PWR_LDO1 (0x1 << 0)
1021#define RT5677_PWR_LDO1_BIT 0
1022
1023/* Power Management for DSP (0x65) */
1024#define RT5677_PWR_SR7 (0x1 << 10)
1025#define RT5677_PWR_SR7_BIT 10
1026#define RT5677_PWR_SR6 (0x1 << 9)
1027#define RT5677_PWR_SR6_BIT 9
1028#define RT5677_PWR_SR5 (0x1 << 8)
1029#define RT5677_PWR_SR5_BIT 8
1030#define RT5677_PWR_SR4 (0x1 << 7)
1031#define RT5677_PWR_SR4_BIT 7
1032#define RT5677_PWR_SR3 (0x1 << 6)
1033#define RT5677_PWR_SR3_BIT 6
1034#define RT5677_PWR_SR2 (0x1 << 5)
1035#define RT5677_PWR_SR2_BIT 5
1036#define RT5677_PWR_SR1 (0x1 << 4)
1037#define RT5677_PWR_SR1_BIT 4
1038#define RT5677_PWR_SR0 (0x1 << 3)
1039#define RT5677_PWR_SR0_BIT 3
1040#define RT5677_PWR_MLT (0x1 << 2)
1041#define RT5677_PWR_MLT_BIT 2
1042#define RT5677_PWR_DSP (0x1 << 1)
1043#define RT5677_PWR_DSP_BIT 1
1044#define RT5677_PWR_DSP_CPU (0x1 << 0)
1045#define RT5677_PWR_DSP_CPU_BIT 0
1046
1047/* Power Status for DSP (0x66) */
1048#define RT5677_PWR_SR7_RDY (0x1 << 9)
1049#define RT5677_PWR_SR7_RDY_BIT 9
1050#define RT5677_PWR_SR6_RDY (0x1 << 8)
1051#define RT5677_PWR_SR6_RDY_BIT 8
1052#define RT5677_PWR_SR5_RDY (0x1 << 7)
1053#define RT5677_PWR_SR5_RDY_BIT 7
1054#define RT5677_PWR_SR4_RDY (0x1 << 6)
1055#define RT5677_PWR_SR4_RDY_BIT 6
1056#define RT5677_PWR_SR3_RDY (0x1 << 5)
1057#define RT5677_PWR_SR3_RDY_BIT 5
1058#define RT5677_PWR_SR2_RDY (0x1 << 4)
1059#define RT5677_PWR_SR2_RDY_BIT 4
1060#define RT5677_PWR_SR1_RDY (0x1 << 3)
1061#define RT5677_PWR_SR1_RDY_BIT 3
1062#define RT5677_PWR_SR0_RDY (0x1 << 2)
1063#define RT5677_PWR_SR0_RDY_BIT 2
1064#define RT5677_PWR_MLT_RDY (0x1 << 1)
1065#define RT5677_PWR_MLT_RDY_BIT 1
1066#define RT5677_PWR_DSP_RDY (0x1 << 0)
1067#define RT5677_PWR_DSP_RDY_BIT 0
1068
1069/* Power Management for DSP (0x67) */
1070#define RT5677_PWR_SLIM_ISO (0x1 << 11)
1071#define RT5677_PWR_SLIM_ISO_BIT 11
1072#define RT5677_PWR_CORE_ISO (0x1 << 10)
1073#define RT5677_PWR_CORE_ISO_BIT 10
1074#define RT5677_PWR_DSP_ISO (0x1 << 9)
1075#define RT5677_PWR_DSP_ISO_BIT 9
1076#define RT5677_PWR_SR7_ISO (0x1 << 8)
1077#define RT5677_PWR_SR7_ISO_BIT 8
1078#define RT5677_PWR_SR6_ISO (0x1 << 7)
1079#define RT5677_PWR_SR6_ISO_BIT 7
1080#define RT5677_PWR_SR5_ISO (0x1 << 6)
1081#define RT5677_PWR_SR5_ISO_BIT 6
1082#define RT5677_PWR_SR4_ISO (0x1 << 5)
1083#define RT5677_PWR_SR4_ISO_BIT 5
1084#define RT5677_PWR_SR3_ISO (0x1 << 4)
1085#define RT5677_PWR_SR3_ISO_BIT 4
1086#define RT5677_PWR_SR2_ISO (0x1 << 3)
1087#define RT5677_PWR_SR2_ISO_BIT 3
1088#define RT5677_PWR_SR1_ISO (0x1 << 2)
1089#define RT5677_PWR_SR1_ISO_BIT 2
1090#define RT5677_PWR_SR0_ISO (0x1 << 1)
1091#define RT5677_PWR_SR0_ISO_BIT 1
1092#define RT5677_PWR_MLT_ISO (0x1 << 0)
1093#define RT5677_PWR_MLT_ISO_BIT 0
1094
1095/* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
1096#define RT5677_I2S_MS_MASK (0x1 << 15)
1097#define RT5677_I2S_MS_SFT 15
1098#define RT5677_I2S_MS_M (0x0 << 15)
1099#define RT5677_I2S_MS_S (0x1 << 15)
1100#define RT5677_I2S_O_CP_MASK (0x3 << 10)
1101#define RT5677_I2S_O_CP_SFT 10
1102#define RT5677_I2S_O_CP_OFF (0x0 << 10)
1103#define RT5677_I2S_O_CP_U_LAW (0x1 << 10)
1104#define RT5677_I2S_O_CP_A_LAW (0x2 << 10)
1105#define RT5677_I2S_I_CP_MASK (0x3 << 8)
1106#define RT5677_I2S_I_CP_SFT 8
1107#define RT5677_I2S_I_CP_OFF (0x0 << 8)
1108#define RT5677_I2S_I_CP_U_LAW (0x1 << 8)
1109#define RT5677_I2S_I_CP_A_LAW (0x2 << 8)
1110#define RT5677_I2S_BP_MASK (0x1 << 7)
1111#define RT5677_I2S_BP_SFT 7
1112#define RT5677_I2S_BP_NOR (0x0 << 7)
1113#define RT5677_I2S_BP_INV (0x1 << 7)
1114#define RT5677_I2S_DL_MASK (0x3 << 2)
1115#define RT5677_I2S_DL_SFT 2
1116#define RT5677_I2S_DL_16 (0x0 << 2)
1117#define RT5677_I2S_DL_20 (0x1 << 2)
1118#define RT5677_I2S_DL_24 (0x2 << 2)
1119#define RT5677_I2S_DL_8 (0x3 << 2)
1120#define RT5677_I2S_DF_MASK (0x3 << 0)
1121#define RT5677_I2S_DF_SFT 0
1122#define RT5677_I2S_DF_I2S (0x0 << 0)
1123#define RT5677_I2S_DF_LEFT (0x1 << 0)
1124#define RT5677_I2S_DF_PCM_A (0x2 << 0)
1125#define RT5677_I2S_DF_PCM_B (0x3 << 0)
1126
1127/* Clock Tree Control 1 (0x73) */
1128#define RT5677_I2S_PD1_MASK (0x7 << 12)
1129#define RT5677_I2S_PD1_SFT 12
1130#define RT5677_I2S_PD1_1 (0x0 << 12)
1131#define RT5677_I2S_PD1_2 (0x1 << 12)
1132#define RT5677_I2S_PD1_3 (0x2 << 12)
1133#define RT5677_I2S_PD1_4 (0x3 << 12)
1134#define RT5677_I2S_PD1_6 (0x4 << 12)
1135#define RT5677_I2S_PD1_8 (0x5 << 12)
1136#define RT5677_I2S_PD1_12 (0x6 << 12)
1137#define RT5677_I2S_PD1_16 (0x7 << 12)
1138#define RT5677_I2S_BCLK_MS2_MASK (0x1 << 11)
1139#define RT5677_I2S_BCLK_MS2_SFT 11
1140#define RT5677_I2S_BCLK_MS2_32 (0x0 << 11)
1141#define RT5677_I2S_BCLK_MS2_64 (0x1 << 11)
1142#define RT5677_I2S_PD2_MASK (0x7 << 8)
1143#define RT5677_I2S_PD2_SFT 8
1144#define RT5677_I2S_PD2_1 (0x0 << 8)
1145#define RT5677_I2S_PD2_2 (0x1 << 8)
1146#define RT5677_I2S_PD2_3 (0x2 << 8)
1147#define RT5677_I2S_PD2_4 (0x3 << 8)
1148#define RT5677_I2S_PD2_6 (0x4 << 8)
1149#define RT5677_I2S_PD2_8 (0x5 << 8)
1150#define RT5677_I2S_PD2_12 (0x6 << 8)
1151#define RT5677_I2S_PD2_16 (0x7 << 8)
1152#define RT5677_I2S_BCLK_MS3_MASK (0x1 << 7)
1153#define RT5677_I2S_BCLK_MS3_SFT 7
1154#define RT5677_I2S_BCLK_MS3_32 (0x0 << 7)
1155#define RT5677_I2S_BCLK_MS3_64 (0x1 << 7)
1156#define RT5677_I2S_PD3_MASK (0x7 << 4)
1157#define RT5677_I2S_PD3_SFT 4
1158#define RT5677_I2S_PD3_1 (0x0 << 4)
1159#define RT5677_I2S_PD3_2 (0x1 << 4)
1160#define RT5677_I2S_PD3_3 (0x2 << 4)
1161#define RT5677_I2S_PD3_4 (0x3 << 4)
1162#define RT5677_I2S_PD3_6 (0x4 << 4)
1163#define RT5677_I2S_PD3_8 (0x5 << 4)
1164#define RT5677_I2S_PD3_12 (0x6 << 4)
1165#define RT5677_I2S_PD3_16 (0x7 << 4)
1166#define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
1167#define RT5677_I2S_BCLK_MS4_SFT 3
1168#define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)
1169#define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
1170#define RT5677_I2S_PD4_MASK (0x7 << 0)
1171#define RT5677_I2S_PD4_SFT 0
1172#define RT5677_I2S_PD4_1 (0x0 << 0)
1173#define RT5677_I2S_PD4_2 (0x1 << 0)
1174#define RT5677_I2S_PD4_3 (0x2 << 0)
1175#define RT5677_I2S_PD4_4 (0x3 << 0)
1176#define RT5677_I2S_PD4_6 (0x4 << 0)
1177#define RT5677_I2S_PD4_8 (0x5 << 0)
1178#define RT5677_I2S_PD4_12 (0x6 << 0)
1179#define RT5677_I2S_PD4_16 (0x7 << 0)
1180
1181/* Clock Tree Control 2 (0x74) */
1182#define RT5677_I2S_PD5_MASK (0x7 << 12)
1183#define RT5677_I2S_PD5_SFT 12
1184#define RT5677_I2S_PD5_1 (0x0 << 12)
1185#define RT5677_I2S_PD5_2 (0x1 << 12)
1186#define RT5677_I2S_PD5_3 (0x2 << 12)
1187#define RT5677_I2S_PD5_4 (0x3 << 12)
1188#define RT5677_I2S_PD5_6 (0x4 << 12)
1189#define RT5677_I2S_PD5_8 (0x5 << 12)
1190#define RT5677_I2S_PD5_12 (0x6 << 12)
1191#define RT5677_I2S_PD5_16 (0x7 << 12)
1192#define RT5677_I2S_PD6_MASK (0x7 << 8)
1193#define RT5677_I2S_PD6_SFT 8
1194#define RT5677_I2S_PD6_1 (0x0 << 8)
1195#define RT5677_I2S_PD6_2 (0x1 << 8)
1196#define RT5677_I2S_PD6_3 (0x2 << 8)
1197#define RT5677_I2S_PD6_4 (0x3 << 8)
1198#define RT5677_I2S_PD6_6 (0x4 << 8)
1199#define RT5677_I2S_PD6_8 (0x5 << 8)
1200#define RT5677_I2S_PD6_12 (0x6 << 8)
1201#define RT5677_I2S_PD6_16 (0x7 << 8)
1202#define RT5677_I2S_PD7_MASK (0x7 << 4)
1203#define RT5677_I2S_PD7_SFT 4
1204#define RT5677_I2S_PD7_1 (0x0 << 4)
1205#define RT5677_I2S_PD7_2 (0x1 << 4)
1206#define RT5677_I2S_PD7_3 (0x2 << 4)
1207#define RT5677_I2S_PD7_4 (0x3 << 4)
1208#define RT5677_I2S_PD7_6 (0x4 << 4)
1209#define RT5677_I2S_PD7_8 (0x5 << 4)
1210#define RT5677_I2S_PD7_12 (0x6 << 4)
1211#define RT5677_I2S_PD7_16 (0x7 << 4)
1212#define RT5677_I2S_PD8_MASK (0x7 << 0)
1213#define RT5677_I2S_PD8_SFT 0
1214#define RT5677_I2S_PD8_1 (0x0 << 0)
1215#define RT5677_I2S_PD8_2 (0x1 << 0)
1216#define RT5677_I2S_PD8_3 (0x2 << 0)
1217#define RT5677_I2S_PD8_4 (0x3 << 0)
1218#define RT5677_I2S_PD8_6 (0x4 << 0)
1219#define RT5677_I2S_PD8_8 (0x5 << 0)
1220#define RT5677_I2S_PD8_12 (0x6 << 0)
1221#define RT5677_I2S_PD8_16 (0x7 << 0)
1222
1223/* Clock Tree Control 3 (0x75) */
1224#define RT5677_DSP_ASRC_O_MASK (0x3 << 6)
1225#define RT5677_DSP_ASRC_O_SFT 6
1226#define RT5677_DSP_ASRC_O_1_0 (0x0 << 6)
1227#define RT5677_DSP_ASRC_O_1_5 (0x1 << 6)
1228#define RT5677_DSP_ASRC_O_2_0 (0x2 << 6)
1229#define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)
1230#define RT5677_DSP_ASRC_I_MASK (0x3 << 4)
1231#define RT5677_DSP_ASRC_I_SFT 4
1232#define RT5677_DSP_ASRC_I_1_0 (0x0 << 4)
1233#define RT5677_DSP_ASRC_I_1_5 (0x1 << 4)
1234#define RT5677_DSP_ASRC_I_2_0 (0x2 << 4)
1235#define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)
1236#define RT5677_DSP_BUS_PD_MASK (0x7 << 0)
1237#define RT5677_DSP_BUS_PD_SFT 0
1238#define RT5677_DSP_BUS_PD_1 (0x0 << 0)
1239#define RT5677_DSP_BUS_PD_2 (0x1 << 0)
1240#define RT5677_DSP_BUS_PD_3 (0x2 << 0)
1241#define RT5677_DSP_BUS_PD_4 (0x3 << 0)
1242#define RT5677_DSP_BUS_PD_6 (0x4 << 0)
1243#define RT5677_DSP_BUS_PD_8 (0x5 << 0)
1244#define RT5677_DSP_BUS_PD_12 (0x6 << 0)
1245#define RT5677_DSP_BUS_PD_16 (0x7 << 0)
1246
1247#define RT5677_PLL_INP_MAX 40000000
1248#define RT5677_PLL_INP_MIN 2048000
1249/* PLL M/N/K Code Control 1 (0x7a 0x7c) */
1250#define RT5677_PLL_N_MAX 0x1ff
1251#define RT5677_PLL_N_MASK (RT5677_PLL_N_MAX << 7)
1252#define RT5677_PLL_N_SFT 7
1253#define RT5677_PLL_K_BP (0x1 << 5)
1254#define RT5677_PLL_K_BP_SFT 5
1255#define RT5677_PLL_K_MAX 0x1f
1256#define RT5677_PLL_K_MASK (RT5677_PLL_K_MAX)
1257#define RT5677_PLL_K_SFT 0
1258
1259/* PLL M/N/K Code Control 2 (0x7b 0x7d) */
1260#define RT5677_PLL_M_MAX 0xf
1261#define RT5677_PLL_M_MASK (RT5677_PLL_M_MAX << 12)
1262#define RT5677_PLL_M_SFT 12
1263#define RT5677_PLL_M_BP (0x1 << 11)
1264#define RT5677_PLL_M_BP_SFT 11
1265
1266/* Global Clock Control 1 (0x80) */
1267#define RT5677_SCLK_SRC_MASK (0x3 << 14)
1268#define RT5677_SCLK_SRC_SFT 14
1269#define RT5677_SCLK_SRC_MCLK (0x0 << 14)
1270#define RT5677_SCLK_SRC_PLL1 (0x1 << 14)
1271#define RT5677_SCLK_SRC_RCCLK (0x2 << 14) /* 25MHz */
1272#define RT5677_SCLK_SRC_SLIM (0x3 << 14)
1273#define RT5677_PLL1_SRC_MASK (0x7 << 11)
1274#define RT5677_PLL1_SRC_SFT 11
1275#define RT5677_PLL1_SRC_MCLK (0x0 << 11)
1276#define RT5677_PLL1_SRC_BCLK1 (0x1 << 11)
1277#define RT5677_PLL1_SRC_BCLK2 (0x2 << 11)
1278#define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)
1279#define RT5677_PLL1_SRC_BCLK4 (0x4 << 11)
1280#define RT5677_PLL1_SRC_RCCLK (0x5 << 11)
1281#define RT5677_PLL1_SRC_SLIM (0x6 << 11)
1282#define RT5677_MCLK_SRC_MASK (0x1 << 10)
1283#define RT5677_MCLK_SRC_SFT 10
1284#define RT5677_MCLK1_SRC (0x0 << 10)
1285#define RT5677_MCLK2_SRC (0x1 << 10)
1286#define RT5677_PLL1_PD_MASK (0x1 << 8)
1287#define RT5677_PLL1_PD_SFT 8
1288#define RT5677_PLL1_PD_1 (0x0 << 8)
1289#define RT5677_PLL1_PD_2 (0x1 << 8)
1290#define RT5671_DAC_OSR_MASK (0x3 << 6)
1291#define RT5671_DAC_OSR_SFT 6
1292#define RT5671_DAC_OSR_128 (0x0 << 6)
1293#define RT5671_DAC_OSR_64 (0x1 << 6)
1294#define RT5671_DAC_OSR_32 (0x2 << 6)
1295#define RT5671_ADC_OSR_MASK (0x3 << 4)
1296#define RT5671_ADC_OSR_SFT 4
1297#define RT5671_ADC_OSR_128 (0x0 << 4)
1298#define RT5671_ADC_OSR_64 (0x1 << 4)
1299#define RT5671_ADC_OSR_32 (0x2 << 4)
1300
1301/* Global Clock Control 2 (0x81) */
1302#define RT5677_PLL2_PR_SRC_MASK (0x1 << 15)
1303#define RT5677_PLL2_PR_SRC_SFT 15
1304#define RT5677_PLL2_PR_SRC_MCLK1 (0x0 << 15)
1305#define RT5677_PLL2_PR_SRC_MCLK2 (0x1 << 15)
1306#define RT5677_PLL2_SRC_MASK (0x7 << 12)
1307#define RT5677_PLL2_SRC_SFT 12
1308#define RT5677_PLL2_SRC_MCLK (0x0 << 12)
1309#define RT5677_PLL2_SRC_BCLK1 (0x1 << 12)
1310#define RT5677_PLL2_SRC_BCLK2 (0x2 << 12)
1311#define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
1312#define RT5677_PLL2_SRC_BCLK4 (0x4 << 12)
1313#define RT5677_PLL2_SRC_RCCLK (0x5 << 12)
1314#define RT5677_PLL2_SRC_SLIM (0x6 << 12)
1315#define RT5671_DSP_ASRC_O_SRC (0x3 << 10)
1316#define RT5671_DSP_ASRC_O_SRC_SFT 10
1317#define RT5671_DSP_ASRC_O_MCLK (0x0 << 10)
1318#define RT5671_DSP_ASRC_O_PLL1 (0x1 << 10)
1319#define RT5671_DSP_ASRC_O_SLIM (0x2 << 10)
1320#define RT5671_DSP_ASRC_O_RCCLK (0x3 << 10)
1321#define RT5671_DSP_ASRC_I_SRC (0x3 << 8)
1322#define RT5671_DSP_ASRC_I_SRC_SFT 8
1323#define RT5671_DSP_ASRC_I_MCLK (0x0 << 8)
1324#define RT5671_DSP_ASRC_I_PLL1 (0x1 << 8)
1325#define RT5671_DSP_ASRC_I_SLIM (0x2 << 8)
1326#define RT5671_DSP_ASRC_I_RCCLK (0x3 << 8)
1327#define RT5677_DSP_CLK_SRC_MASK (0x1 << 7)
1328#define RT5677_DSP_CLK_SRC_SFT 7
1329#define RT5677_DSP_CLK_SRC_PLL2 (0x0 << 7)
1330#define RT5677_DSP_CLK_SRC_BYPASS (0x1 << 7)
1331
1332/* VAD Function Control 4 (0x9f) */
1333#define RT5677_VAD_SRC_MASK (0x7 << 8)
1334#define RT5677_VAD_SRC_SFT 8
1335
1336/* DSP InBound Control (0xa3) */
1337#define RT5677_IB01_SRC_MASK (0x7 << 12)
1338#define RT5677_IB01_SRC_SFT 12
1339#define RT5677_IB23_SRC_MASK (0x7 << 8)
1340#define RT5677_IB23_SRC_SFT 8
1341#define RT5677_IB45_SRC_MASK (0x7 << 4)
1342#define RT5677_IB45_SRC_SFT 4
1343#define RT5677_IB6_SRC_MASK (0x7 << 0)
1344#define RT5677_IB6_SRC_SFT 0
1345
1346/* DSP InBound Control (0xa4) */
1347#define RT5677_IB7_SRC_MASK (0x7 << 12)
1348#define RT5677_IB7_SRC_SFT 12
1349#define RT5677_IB8_SRC_MASK (0x7 << 8)
1350#define RT5677_IB8_SRC_SFT 8
1351#define RT5677_IB9_SRC_MASK (0x7 << 4)
1352#define RT5677_IB9_SRC_SFT 4
1353
1354/* DSP In/OutBound Control (0xa5) */
1355#define RT5677_SEL_SRC_OB23 (0x1 << 4)
1356#define RT5677_SEL_SRC_OB23_SFT 4
1357#define RT5677_SEL_SRC_OB01 (0x1 << 3)
1358#define RT5677_SEL_SRC_OB01_SFT 3
1359#define RT5677_SEL_SRC_IB45 (0x1 << 2)
1360#define RT5677_SEL_SRC_IB45_SFT 2
1361#define RT5677_SEL_SRC_IB23 (0x1 << 1)
1362#define RT5677_SEL_SRC_IB23_SFT 1
1363#define RT5677_SEL_SRC_IB01 (0x1 << 0)
1364#define RT5677_SEL_SRC_IB01_SFT 0
1365
1366/* Virtual DSP Mixer Control (0xf7 0xf8 0xf9) */
1367#define RT5677_DSP_IB_01_H (0x1 << 15)
1368#define RT5677_DSP_IB_01_H_SFT 15
1369#define RT5677_DSP_IB_23_H (0x1 << 14)
1370#define RT5677_DSP_IB_23_H_SFT 14
1371#define RT5677_DSP_IB_45_H (0x1 << 13)
1372#define RT5677_DSP_IB_45_H_SFT 13
1373#define RT5677_DSP_IB_6_H (0x1 << 12)
1374#define RT5677_DSP_IB_6_H_SFT 12
1375#define RT5677_DSP_IB_7_H (0x1 << 11)
1376#define RT5677_DSP_IB_7_H_SFT 11
1377#define RT5677_DSP_IB_8_H (0x1 << 10)
1378#define RT5677_DSP_IB_8_H_SFT 10
1379#define RT5677_DSP_IB_9_H (0x1 << 9)
1380#define RT5677_DSP_IB_9_H_SFT 9
1381#define RT5677_DSP_IB_01_L (0x1 << 7)
1382#define RT5677_DSP_IB_01_L_SFT 7
1383#define RT5677_DSP_IB_23_L (0x1 << 6)
1384#define RT5677_DSP_IB_23_L_SFT 6
1385#define RT5677_DSP_IB_45_L (0x1 << 5)
1386#define RT5677_DSP_IB_45_L_SFT 5
1387#define RT5677_DSP_IB_6_L (0x1 << 4)
1388#define RT5677_DSP_IB_6_L_SFT 4
1389#define RT5677_DSP_IB_7_L (0x1 << 3)
1390#define RT5677_DSP_IB_7_L_SFT 3
1391#define RT5677_DSP_IB_8_L (0x1 << 2)
1392#define RT5677_DSP_IB_8_L_SFT 2
1393#define RT5677_DSP_IB_9_L (0x1 << 1)
1394#define RT5677_DSP_IB_9_L_SFT 1
1395
1396/* Debug String Length */
1397#define RT5677_REG_DISP_LEN 23
1398
1399#define RT5677_NO_JACK BIT(0)
1400#define RT5677_HEADSET_DET BIT(1)
1401#define RT5677_HEADPHO_DET BIT(2)
1402
1403/* System Clock Source */
1404enum {
1405 RT5677_SCLK_S_MCLK,
1406 RT5677_SCLK_S_PLL1,
1407 RT5677_SCLK_S_RCCLK,
1408};
1409
1410/* PLL1 Source */
1411enum {
1412 RT5677_PLL1_S_MCLK,
1413 RT5677_PLL1_S_BCLK1,
1414 RT5677_PLL1_S_BCLK2,
1415 RT5677_PLL1_S_BCLK3,
1416 RT5677_PLL1_S_BCLK4,
1417};
1418
1419enum {
1420 RT5677_AIF1,
1421 RT5677_AIF2,
1422 RT5677_AIF3,
1423 RT5677_AIF4,
1424 RT5677_AIF5,
1425 RT5677_AIFS,
1426};
1427
1428struct rt5677_pll_code {
1429 bool m_bp; /* Indicates bypass m code or not. */
1430 bool k_bp; /* Indicates bypass k code or not. */
1431 int m_code;
1432 int n_code;
1433 int k_code;
1434};
1435
1436struct rt5677_priv {
1437 struct snd_soc_codec *codec;
1438 struct rt5677_platform_data pdata;
1439 struct regmap *regmap;
1440
1441 int sysclk;
1442 int sysclk_src;
1443 int lrck[RT5677_AIFS];
1444 int bclk[RT5677_AIFS];
1445 int master[RT5677_AIFS];
1446 int pll_src;
1447 int pll_in;
1448 int pll_out;
1449};
1450
1451#endif /* __RT5677_H__ */
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