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-rw-r--r--arch/arm/include/asm/hardware/entry-macro-gic.S7
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/entry-macro.S5
-rw-r--r--arch/arm/mach-omap2/include/mach/entry-macro.S1
-rw-r--r--arch/arm/mach-realview/include/mach/entry-macro.S5
-rw-r--r--arch/arm/mach-tegra/include/mach/entry-macro.S2
-rw-r--r--arch/arm/mach-ux500/include/mach/entry-macro.S1
-rw-r--r--arch/arm/mach-vexpress/include/mach/entry-macro.S5
7 files changed, 10 insertions, 16 deletions
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
index 05587f125a13..c115b82fe80a 100644
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -10,6 +10,13 @@
10 10
11#include <asm/hardware/gic.h> 11#include <asm/hardware/gic.h>
12 12
13#ifndef HAVE_GET_IRQNR_PREAMBLE
14 .macro get_irqnr_preamble, base, tmp
15 ldr \base, =gic_cpu_base_addr
16 ldr \base, [\base]
17 .endm
18#endif
19
13/* 20/*
14 * The interrupt numbering scheme is defined in the 21 * The interrupt numbering scheme is defined in the
15 * interrupt controller spec. To wit: 22 * interrupt controller spec. To wit:
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index e793c3376728..6bd83ed90afe 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -14,10 +14,5 @@
14 .macro disable_fiq 14 .macro disable_fiq
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =gic_cpu_base_addr
19 ldr \base, [\base]
20 .endm
21
22 .macro arch_ret_to_user, tmp1, tmp2 17 .macro arch_ret_to_user, tmp1, tmp2
23 .endm 18 .endm
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index 2e358df3fe19..d54c4f89a8bd 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -170,6 +170,7 @@ omap_irq_base: .word 0
170 170
171 171
172#ifdef CONFIG_ARCH_OMAP4 172#ifdef CONFIG_ARCH_OMAP4
173#define HAVE_GET_IRQNR_PREAMBLE
173#include <asm/hardware/entry-macro-gic.S> 174#include <asm/hardware/entry-macro-gic.S>
174 175
175 .macro get_irqnr_preamble, base, tmp 176 .macro get_irqnr_preamble, base, tmp
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
index 4417b1039615..4071164aebaa 100644
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -13,11 +13,6 @@
13 .macro disable_fiq 13 .macro disable_fiq
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp
17 ldr \base, =gic_cpu_base_addr
18 ldr \base, [\base]
19 .endm
20
21 .macro arch_ret_to_user, tmp1, tmp2 16 .macro arch_ret_to_user, tmp1, tmp2
22 .endm 17 .endm
23 18
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index dc0924915183..dd165c53889d 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -16,7 +16,7 @@
16#include <mach/io.h> 16#include <mach/io.h>
17 17
18#if defined(CONFIG_ARM_GIC) 18#if defined(CONFIG_ARM_GIC)
19 19#define HAVE_GET_IRQNR_PREAMBLE
20#include <asm/hardware/entry-macro-gic.S> 20#include <asm/hardware/entry-macro-gic.S>
21 21
22 /* Uses the GIC interrupt controller built into the cpu */ 22 /* Uses the GIC interrupt controller built into the cpu */
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index 3cc3cdf55180..a37f585a3ecb 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -11,6 +11,7 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14#define HAVE_GET_IRQNR_PREAMBLE
14#include <asm/hardware/entry-macro-gic.S> 15#include <asm/hardware/entry-macro-gic.S>
15 16
16 .macro disable_fiq 17 .macro disable_fiq
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
index 19d5ac8ba071..73c11297509e 100644
--- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S
@@ -3,10 +3,5 @@
3 .macro disable_fiq 3 .macro disable_fiq
4 .endm 4 .endm
5 5
6 .macro get_irqnr_preamble, base, tmp
7 ldr \base, =gic_cpu_base_addr
8 ldr \base, [\base]
9 .endm
10
11 .macro arch_ret_to_user, tmp1, tmp2 6 .macro arch_ret_to_user, tmp1, tmp2
12 .endm 7 .endm