2 files changed, 16 insertions, 0 deletions

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index e90344a17631..42414cd73571 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -316,7 +316,9 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
         int retval;
         struct fsl_usb2_platform_data *pdata;
+        struct device *dev;
 
+        dev = hcd->self.controller;
         pdata = hcd->self.controller->platform_data;
         ehci->big_endian_desc = pdata->big_endian_desc;
         ehci->big_endian_mmio = pdata->big_endian_mmio;
@@ -346,6 +348,16 @@ static int ehci_fsl_setup(struct usb_hcd *hcd)
 
         ehci_reset(ehci);
 
+        if (of_device_is_compatible(dev->parent->of_node,
+                                    "fsl,mpc5121-usb2-dr")) {
+                /*
+                 * set SBUSCFG:AHBBRST so that control msgs don't
+                 * fail when doing heavy PATA writes.
+                 */
+                ehci_writel(ehci, SBUSCFG_INCR8,
+                            hcd->regs + FSL_SOC_USB_SBUSCFG);
+        }
+
         retval = ehci_fsl_reinit(ehci);
         return retval;
 }
@@ -469,6 +481,8 @@ static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
         ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
                     hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
 
+        ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
+
         /* restore EHCI registers */
         ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
         ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 491806221165..0855be8b5b47 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -19,6 +19,8 @@
 #define _EHCI_FSL_H
 
 /* offsets for the non-ehci registers in the FSL SOC USB controller */
+#define FSL_SOC_USB_SBUSCFG     0x90
+#define SBUSCFG_INCR8           0x02    /* INCR8, specified */
 #define FSL_SOC_USB_ULPIVP      0x170
 #define FSL_SOC_USB_PORTSC1     0x184
 #define PORT_PTS_MSK            (3<<30)