diff options
-rw-r--r-- | arch/arm/plat-omap/include/plat/dmtimer.h | 52 |
1 files changed, 25 insertions, 27 deletions
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h index b60e2b66ad18..b3cd91b60a2e 100644 --- a/arch/arm/plat-omap/include/plat/dmtimer.h +++ b/arch/arm/plat-omap/include/plat/dmtimer.h | |||
@@ -79,8 +79,6 @@ struct omap_timer_capability_dev_attr { | |||
79 | u32 timer_capability; | 79 | u32 timer_capability; |
80 | }; | 80 | }; |
81 | 81 | ||
82 | struct omap_dm_timer; | ||
83 | |||
84 | struct timer_regs { | 82 | struct timer_regs { |
85 | u32 tidr; | 83 | u32 tidr; |
86 | u32 tier; | 84 | u32 tier; |
@@ -101,6 +99,31 @@ struct timer_regs { | |||
101 | u32 towr; | 99 | u32 towr; |
102 | }; | 100 | }; |
103 | 101 | ||
102 | struct omap_dm_timer { | ||
103 | int id; | ||
104 | int irq; | ||
105 | struct clk *fclk; | ||
106 | |||
107 | void __iomem *io_base; | ||
108 | void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ | ||
109 | void __iomem *irq_ena; /* irq enable */ | ||
110 | void __iomem *irq_dis; /* irq disable, only on v2 ip */ | ||
111 | void __iomem *pend; /* write pending */ | ||
112 | void __iomem *func_base; /* function register base */ | ||
113 | |||
114 | unsigned long rate; | ||
115 | unsigned reserved:1; | ||
116 | unsigned posted:1; | ||
117 | struct timer_regs context; | ||
118 | int (*get_context_loss_count)(struct device *); | ||
119 | int ctx_loss_count; | ||
120 | int revision; | ||
121 | u32 capability; | ||
122 | u32 errata; | ||
123 | struct platform_device *pdev; | ||
124 | struct list_head node; | ||
125 | }; | ||
126 | |||
104 | struct dmtimer_platform_data { | 127 | struct dmtimer_platform_data { |
105 | /* set_timer_src - Only used for OMAP1 devices */ | 128 | /* set_timer_src - Only used for OMAP1 devices */ |
106 | int (*set_timer_src)(struct platform_device *pdev, int source); | 129 | int (*set_timer_src)(struct platform_device *pdev, int source); |
@@ -260,31 +283,6 @@ int omap_dm_timers_active(void); | |||
260 | #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ | 283 | #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ |
261 | (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) | 284 | (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) |
262 | 285 | ||
263 | struct omap_dm_timer { | ||
264 | int id; | ||
265 | int irq; | ||
266 | struct clk *fclk; | ||
267 | |||
268 | void __iomem *io_base; | ||
269 | void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */ | ||
270 | void __iomem *irq_ena; /* irq enable */ | ||
271 | void __iomem *irq_dis; /* irq disable, only on v2 ip */ | ||
272 | void __iomem *pend; /* write pending */ | ||
273 | void __iomem *func_base; /* function register base */ | ||
274 | |||
275 | unsigned long rate; | ||
276 | unsigned reserved:1; | ||
277 | unsigned posted:1; | ||
278 | struct timer_regs context; | ||
279 | int (*get_context_loss_count)(struct device *); | ||
280 | int ctx_loss_count; | ||
281 | int revision; | ||
282 | u32 capability; | ||
283 | u32 errata; | ||
284 | struct platform_device *pdev; | ||
285 | struct list_head node; | ||
286 | }; | ||
287 | |||
288 | static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, | 286 | static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, |
289 | int posted) | 287 | int posted) |
290 | { | 288 | { |