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-rw-r--r--drivers/gpu/drm/Kconfig1
-rw-r--r--drivers/gpu/drm/radeon/Kconfig33
-rw-r--r--drivers/gpu/drm/radeon/Makefile10
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c6
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c353
-rw-r--r--drivers/gpu/drm/radeon/evergreen_cs.c1149
-rw-r--r--drivers/gpu/drm/radeon/evergreen_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h54
-rw-r--r--drivers/gpu/drm/radeon/ni.c339
-rw-r--r--drivers/gpu/drm/radeon/nid.h27
-rw-r--r--drivers/gpu/drm/radeon/r100.c224
-rw-r--r--drivers/gpu/drm/radeon/r100_track.h4
-rw-r--r--drivers/gpu/drm/radeon/r100d.h11
-rw-r--r--drivers/gpu/drm/radeon/r200.c26
-rw-r--r--drivers/gpu/drm/radeon/r300.c42
-rw-r--r--drivers/gpu/drm/radeon/r300_cmdbuf.c2
-rw-r--r--drivers/gpu/drm/radeon/r300d.h11
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h1
-rw-r--r--drivers/gpu/drm/radeon/r600.c384
-rw-r--r--drivers/gpu/drm/radeon/r600_blit.c33
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c31
-rw-r--r--drivers/gpu/drm/radeon/r600_cp.c2
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c332
-rw-r--r--drivers/gpu/drm/radeon/r600d.h17
-rw-r--r--drivers/gpu/drm/radeon/radeon.h31
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c52
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h17
-rw-r--r--drivers/gpu/drm/radeon/radeon_cp.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c176
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c70
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.h16
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h1
-rw-r--r--drivers/gpu/drm/radeon/radeon_gart.c60
-rw-r--r--drivers/gpu/drm/radeon/radeon_irq.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_mem.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_reg.h15
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c19
-rw-r--r--drivers/gpu/drm/radeon/radeon_state.c2
-rw-r--r--drivers/gpu/drm/radeon/rv515d.h11
-rw-r--r--drivers/gpu/drm/radeon/si.c478
-rw-r--r--drivers/gpu/drm/radeon/sid.h25
-rw-r--r--include/drm/drm_pciids.h13
43 files changed, 2199 insertions, 1887 deletions
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 983201b450f1..3399b209260a 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -96,6 +96,7 @@ config DRM_RADEON
96 select DRM_TTM 96 select DRM_TTM
97 select POWER_SUPPLY 97 select POWER_SUPPLY
98 select HWMON 98 select HWMON
99 select BACKLIGHT_CLASS_DEVICE
99 help 100 help
100 Choose this option if you have an ATI Radeon graphics card. There 101 Choose this option if you have an ATI Radeon graphics card. There
101 are both PCI and AGP versions. You don't need to choose this to 102 are both PCI and AGP versions. You don't need to choose this to
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index ea92bbe3ed37..970f8e92dbb7 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -1,31 +1,8 @@
1config DRM_RADEON_KMS 1config DRM_RADEON_UMS
2 bool "Enable modesetting on radeon by default - NEW DRIVER" 2 bool "Enable userspace modesetting on radeon (DEPRECATED)"
3 depends on DRM_RADEON 3 depends on DRM_RADEON
4 select BACKLIGHT_CLASS_DEVICE
5 help 4 help
6 Choose this option if you want kernel modesetting enabled by default. 5 Choose this option if you still need userspace modesetting.
7 6
8 This is a completely new driver. It's only part of the existing drm 7 Userspace modesetting is deprecated for quite some time now, so
9 for compatibility reasons. It requires an entirely different graphics 8 enable this only if you have ancient versions of the DDX drivers.
10 stack above it and works very differently from the old drm stack.
11 i.e. don't enable this unless you know what you are doing it may
12 cause issues or bugs compared to the previous userspace driver stack.
13
14 When kernel modesetting is enabled the IOCTL of radeon/drm
15 driver are considered as invalid and an error message is printed
16 in the log and they return failure.
17
18 KMS enabled userspace will use new API to talk with the radeon/drm
19 driver. The new API provide functions to create/destroy/share/mmap
20 buffer object which are then managed by the kernel memory manager
21 (here TTM). In order to submit command to the GPU the userspace
22 provide a buffer holding the command stream, along this buffer
23 userspace have to provide a list of buffer object used by the
24 command stream. The kernel radeon driver will then place buffer
25 in GPU accessible memory and will update command stream to reflect
26 the position of the different buffers.
27
28 The kernel will also perform security check on command stream
29 provided by the user, we want to catch and forbid any illegal use
30 of the GPU such as DMA into random system memory or into memory
31 not owned by the process supplying the command stream.
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
index a6598fd66423..bf172522ea68 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -56,8 +56,12 @@ $(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
56 56
57$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h 57$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h
58 58
59radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \ 59radeon-y := radeon_drv.o
60 radeon_irq.o r300_cmdbuf.o r600_cp.o 60
61# add UMS driver
62radeon-$(CONFIG_DRM_RADEON_UMS)+= radeon_cp.o radeon_state.o radeon_mem.o \
63 radeon_irq.o r300_cmdbuf.o r600_cp.o r600_blit.o
64
61# add KMS driver 65# add KMS driver
62radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ 66radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
63 radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \ 67 radeon_atombios.o radeon_agp.o atombios_crtc.o radeon_combios.o \
@@ -67,7 +71,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
67 radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \ 71 radeon_clocks.o radeon_fb.o radeon_gem.o radeon_ring.o radeon_irq_kms.o \
68 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \ 72 radeon_cs.o radeon_bios.o radeon_benchmark.o r100.o r300.o r420.o \
69 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \ 73 rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
70 r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ 74 r200.o radeon_legacy_tv.o r600_cs.o r600_blit_shaders.o \
71 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ 75 r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \
72 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ 76 evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \
73 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \ 77 evergreen_hdmi.o radeon_trace_points.o ni.o cayman_blit_shaders.o \
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 9175615bbd8a..21a892c6ab9c 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -252,8 +252,6 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
252 radeon_crtc->enabled = true; 252 radeon_crtc->enabled = true;
253 /* adjust pm to dpms changes BEFORE enabling crtcs */ 253 /* adjust pm to dpms changes BEFORE enabling crtcs */
254 radeon_pm_compute_clocks(rdev); 254 radeon_pm_compute_clocks(rdev);
255 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
256 atombios_powergate_crtc(crtc, ATOM_DISABLE);
257 atombios_enable_crtc(crtc, ATOM_ENABLE); 255 atombios_enable_crtc(crtc, ATOM_ENABLE);
258 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 256 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
259 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 257 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
@@ -271,8 +269,6 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
271 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 269 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
272 atombios_enable_crtc(crtc, ATOM_DISABLE); 270 atombios_enable_crtc(crtc, ATOM_DISABLE);
273 radeon_crtc->enabled = false; 271 radeon_crtc->enabled = false;
274 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
275 atombios_powergate_crtc(crtc, ATOM_ENABLE);
276 /* adjust pm to dpms changes AFTER disabling crtcs */ 272 /* adjust pm to dpms changes AFTER disabling crtcs */
277 radeon_pm_compute_clocks(rdev); 273 radeon_pm_compute_clocks(rdev);
278 break; 274 break;
@@ -1844,6 +1840,8 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
1844 int i; 1840 int i;
1845 1841
1846 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 1842 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1843 if (ASIC_IS_DCE6(rdev))
1844 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1847 1845
1848 for (i = 0; i < rdev->num_crtc; i++) { 1846 for (i = 0; i < rdev->num_crtc; i++) {
1849 if (rdev->mode_info.crtcs[i] && 1847 if (rdev->mode_info.crtcs[i] &&
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a2d478e8692a..2916de896a60 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2308,32 +2308,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
2308 return 0; 2308 return 0;
2309} 2309}
2310 2310
2311bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2311void evergreen_print_gpu_status_regs(struct radeon_device *rdev)
2312{ 2312{
2313 u32 srbm_status;
2314 u32 grbm_status;
2315 u32 grbm_status_se0, grbm_status_se1;
2316
2317 srbm_status = RREG32(SRBM_STATUS);
2318 grbm_status = RREG32(GRBM_STATUS);
2319 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2320 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2321 if (!(grbm_status & GUI_ACTIVE)) {
2322 radeon_ring_lockup_update(ring);
2323 return false;
2324 }
2325 /* force CP activities */
2326 radeon_ring_force_activity(rdev, ring);
2327 return radeon_ring_test_lockup(rdev, ring);
2328}
2329
2330static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
2331{
2332 u32 grbm_reset = 0;
2333
2334 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2335 return;
2336
2337 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", 2313 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
2338 RREG32(GRBM_STATUS)); 2314 RREG32(GRBM_STATUS));
2339 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", 2315 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
@@ -2342,6 +2318,8 @@ static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
2342 RREG32(GRBM_STATUS_SE1)); 2318 RREG32(GRBM_STATUS_SE1));
2343 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", 2319 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
2344 RREG32(SRBM_STATUS)); 2320 RREG32(SRBM_STATUS));
2321 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n",
2322 RREG32(SRBM_STATUS2));
2345 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 2323 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2346 RREG32(CP_STALLED_STAT1)); 2324 RREG32(CP_STALLED_STAT1));
2347 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 2325 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
@@ -2350,112 +2328,283 @@ static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
2350 RREG32(CP_BUSY_STAT)); 2328 RREG32(CP_BUSY_STAT));
2351 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 2329 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2352 RREG32(CP_STAT)); 2330 RREG32(CP_STAT));
2331 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
2332 RREG32(DMA_STATUS_REG));
2333 if (rdev->family >= CHIP_CAYMAN) {
2334 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n",
2335 RREG32(DMA_STATUS_REG + 0x800));
2336 }
2337}
2353 2338
2354 /* Disable CP parsing/prefetching */ 2339bool evergreen_is_display_hung(struct radeon_device *rdev)
2355 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 2340{
2341 u32 crtc_hung = 0;
2342 u32 crtc_status[6];
2343 u32 i, j, tmp;
2356 2344
2357 /* reset all the gfx blocks */ 2345 for (i = 0; i < rdev->num_crtc; i++) {
2358 grbm_reset = (SOFT_RESET_CP | 2346 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) {
2359 SOFT_RESET_CB | 2347 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2360 SOFT_RESET_DB | 2348 crtc_hung |= (1 << i);
2361 SOFT_RESET_PA | 2349 }
2362 SOFT_RESET_SC | 2350 }
2363 SOFT_RESET_SPI |
2364 SOFT_RESET_SH |
2365 SOFT_RESET_SX |
2366 SOFT_RESET_TC |
2367 SOFT_RESET_TA |
2368 SOFT_RESET_VC |
2369 SOFT_RESET_VGT);
2370
2371 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2372 WREG32(GRBM_SOFT_RESET, grbm_reset);
2373 (void)RREG32(GRBM_SOFT_RESET);
2374 udelay(50);
2375 WREG32(GRBM_SOFT_RESET, 0);
2376 (void)RREG32(GRBM_SOFT_RESET);
2377 2351
2378 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", 2352 for (j = 0; j < 10; j++) {
2379 RREG32(GRBM_STATUS)); 2353 for (i = 0; i < rdev->num_crtc; i++) {
2380 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", 2354 if (crtc_hung & (1 << i)) {
2381 RREG32(GRBM_STATUS_SE0)); 2355 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
2382 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", 2356 if (tmp != crtc_status[i])
2383 RREG32(GRBM_STATUS_SE1)); 2357 crtc_hung &= ~(1 << i);
2384 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", 2358 }
2385 RREG32(SRBM_STATUS)); 2359 }
2386 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 2360 if (crtc_hung == 0)
2387 RREG32(CP_STALLED_STAT1)); 2361 return false;
2388 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 2362 udelay(100);
2389 RREG32(CP_STALLED_STAT2)); 2363 }
2390 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 2364
2391 RREG32(CP_BUSY_STAT)); 2365 return true;
2392 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
2393 RREG32(CP_STAT));
2394} 2366}
2395 2367
2396static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev) 2368static u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev)
2397{ 2369{
2370 u32 reset_mask = 0;
2398 u32 tmp; 2371 u32 tmp;
2399 2372
2400 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2373 /* GRBM_STATUS */
2401 return; 2374 tmp = RREG32(GRBM_STATUS);
2375 if (tmp & (PA_BUSY | SC_BUSY |
2376 SH_BUSY | SX_BUSY |
2377 TA_BUSY | VGT_BUSY |
2378 DB_BUSY | CB_BUSY |
2379 SPI_BUSY | VGT_BUSY_NO_DMA))
2380 reset_mask |= RADEON_RESET_GFX;
2402 2381
2403 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 2382 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2404 RREG32(DMA_STATUS_REG)); 2383 CP_BUSY | CP_COHERENCY_BUSY))
2384 reset_mask |= RADEON_RESET_CP;
2405 2385
2406 /* Disable DMA */ 2386 if (tmp & GRBM_EE_BUSY)
2407 tmp = RREG32(DMA_RB_CNTL); 2387 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2408 tmp &= ~DMA_RB_ENABLE;
2409 WREG32(DMA_RB_CNTL, tmp);
2410 2388
2411 /* Reset dma */ 2389 /* DMA_STATUS_REG */
2412 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA); 2390 tmp = RREG32(DMA_STATUS_REG);
2413 RREG32(SRBM_SOFT_RESET); 2391 if (!(tmp & DMA_IDLE))
2414 udelay(50); 2392 reset_mask |= RADEON_RESET_DMA;
2415 WREG32(SRBM_SOFT_RESET, 0);
2416 2393
2417 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 2394 /* SRBM_STATUS2 */
2418 RREG32(DMA_STATUS_REG)); 2395 tmp = RREG32(SRBM_STATUS2);
2396 if (tmp & DMA_BUSY)
2397 reset_mask |= RADEON_RESET_DMA;
2398
2399 /* SRBM_STATUS */
2400 tmp = RREG32(SRBM_STATUS);
2401 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2402 reset_mask |= RADEON_RESET_RLC;
2403
2404 if (tmp & IH_BUSY)
2405 reset_mask |= RADEON_RESET_IH;
2406
2407 if (tmp & SEM_BUSY)
2408 reset_mask |= RADEON_RESET_SEM;
2409
2410 if (tmp & GRBM_RQ_PENDING)
2411 reset_mask |= RADEON_RESET_GRBM;
2412
2413 if (tmp & VMC_BUSY)
2414 reset_mask |= RADEON_RESET_VMC;
2415
2416 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2417 MCC_BUSY | MCD_BUSY))
2418 reset_mask |= RADEON_RESET_MC;
2419
2420 if (evergreen_is_display_hung(rdev))
2421 reset_mask |= RADEON_RESET_DISPLAY;
2422
2423 /* VM_L2_STATUS */
2424 tmp = RREG32(VM_L2_STATUS);
2425 if (tmp & L2_BUSY)
2426 reset_mask |= RADEON_RESET_VMC;
2427
2428 return reset_mask;
2419} 2429}
2420 2430
2421static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 2431static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2422{ 2432{
2423 struct evergreen_mc_save save; 2433 struct evergreen_mc_save save;
2424 2434 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2425 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2435 u32 tmp;
2426 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
2427
2428 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2429 reset_mask &= ~RADEON_RESET_DMA;
2430 2436
2431 if (reset_mask == 0) 2437 if (reset_mask == 0)
2432 return 0; 2438 return;
2433 2439
2434 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 2440 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2435 2441
2442 evergreen_print_gpu_status_regs(rdev);
2443
2444 /* Disable CP parsing/prefetching */
2445 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2446
2447 if (reset_mask & RADEON_RESET_DMA) {
2448 /* Disable DMA */
2449 tmp = RREG32(DMA_RB_CNTL);
2450 tmp &= ~DMA_RB_ENABLE;
2451 WREG32(DMA_RB_CNTL, tmp);
2452 }
2453
2454 udelay(50);
2455
2436 evergreen_mc_stop(rdev, &save); 2456 evergreen_mc_stop(rdev, &save);
2437 if (evergreen_mc_wait_for_idle(rdev)) { 2457 if (evergreen_mc_wait_for_idle(rdev)) {
2438 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2458 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2439 } 2459 }
2440 2460
2441 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 2461 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
2442 evergreen_gpu_soft_reset_gfx(rdev); 2462 grbm_soft_reset |= SOFT_RESET_DB |
2463 SOFT_RESET_CB |
2464 SOFT_RESET_PA |
2465 SOFT_RESET_SC |
2466 SOFT_RESET_SPI |
2467 SOFT_RESET_SX |
2468 SOFT_RESET_SH |
2469 SOFT_RESET_TC |
2470 SOFT_RESET_TA |
2471 SOFT_RESET_VC |
2472 SOFT_RESET_VGT;
2473 }
2474
2475 if (reset_mask & RADEON_RESET_CP) {
2476 grbm_soft_reset |= SOFT_RESET_CP |
2477 SOFT_RESET_VGT;
2478
2479 srbm_soft_reset |= SOFT_RESET_GRBM;
2480 }
2443 2481
2444 if (reset_mask & RADEON_RESET_DMA) 2482 if (reset_mask & RADEON_RESET_DMA)
2445 evergreen_gpu_soft_reset_dma(rdev); 2483 srbm_soft_reset |= SOFT_RESET_DMA;
2484
2485 if (reset_mask & RADEON_RESET_DISPLAY)
2486 srbm_soft_reset |= SOFT_RESET_DC;
2487
2488 if (reset_mask & RADEON_RESET_RLC)
2489 srbm_soft_reset |= SOFT_RESET_RLC;
2490
2491 if (reset_mask & RADEON_RESET_SEM)
2492 srbm_soft_reset |= SOFT_RESET_SEM;
2493
2494 if (reset_mask & RADEON_RESET_IH)
2495 srbm_soft_reset |= SOFT_RESET_IH;
2496
2497 if (reset_mask & RADEON_RESET_GRBM)
2498 srbm_soft_reset |= SOFT_RESET_GRBM;
2499
2500 if (reset_mask & RADEON_RESET_VMC)
2501 srbm_soft_reset |= SOFT_RESET_VMC;
2502
2503 if (!(rdev->flags & RADEON_IS_IGP)) {
2504 if (reset_mask & RADEON_RESET_MC)
2505 srbm_soft_reset |= SOFT_RESET_MC;
2506 }
2507
2508 if (grbm_soft_reset) {
2509 tmp = RREG32(GRBM_SOFT_RESET);
2510 tmp |= grbm_soft_reset;
2511 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2512 WREG32(GRBM_SOFT_RESET, tmp);
2513 tmp = RREG32(GRBM_SOFT_RESET);
2514
2515 udelay(50);
2516
2517 tmp &= ~grbm_soft_reset;
2518 WREG32(GRBM_SOFT_RESET, tmp);
2519 tmp = RREG32(GRBM_SOFT_RESET);
2520 }
2521
2522 if (srbm_soft_reset) {
2523 tmp = RREG32(SRBM_SOFT_RESET);
2524 tmp |= srbm_soft_reset;
2525 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2526 WREG32(SRBM_SOFT_RESET, tmp);
2527 tmp = RREG32(SRBM_SOFT_RESET);
2528
2529 udelay(50);
2530
2531 tmp &= ~srbm_soft_reset;
2532 WREG32(SRBM_SOFT_RESET, tmp);
2533 tmp = RREG32(SRBM_SOFT_RESET);
2534 }
2446 2535
2447 /* Wait a little for things to settle down */ 2536 /* Wait a little for things to settle down */
2448 udelay(50); 2537 udelay(50);
2449 2538
2450 evergreen_mc_resume(rdev, &save); 2539 evergreen_mc_resume(rdev, &save);
2451 return 0; 2540 udelay(50);
2541
2542 evergreen_print_gpu_status_regs(rdev);
2452} 2543}
2453 2544
2454int evergreen_asic_reset(struct radeon_device *rdev) 2545int evergreen_asic_reset(struct radeon_device *rdev)
2455{ 2546{
2456 return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 2547 u32 reset_mask;
2457 RADEON_RESET_COMPUTE | 2548
2458 RADEON_RESET_DMA)); 2549 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2550
2551 if (reset_mask)
2552 r600_set_bios_scratch_engine_hung(rdev, true);
2553
2554 evergreen_gpu_soft_reset(rdev, reset_mask);
2555
2556 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2557
2558 if (!reset_mask)
2559 r600_set_bios_scratch_engine_hung(rdev, false);
2560
2561 return 0;
2562}
2563
2564/**
2565 * evergreen_gfx_is_lockup - Check if the GFX engine is locked up
2566 *
2567 * @rdev: radeon_device pointer
2568 * @ring: radeon_ring structure holding ring information
2569 *
2570 * Check if the GFX engine is locked up.
2571 * Returns true if the engine appears to be locked up, false if not.
2572 */
2573bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2574{
2575 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2576
2577 if (!(reset_mask & (RADEON_RESET_GFX |
2578 RADEON_RESET_COMPUTE |
2579 RADEON_RESET_CP))) {
2580 radeon_ring_lockup_update(ring);
2581 return false;
2582 }
2583 /* force CP activities */
2584 radeon_ring_force_activity(rdev, ring);
2585 return radeon_ring_test_lockup(rdev, ring);
2586}
2587
2588/**
2589 * evergreen_dma_is_lockup - Check if the DMA engine is locked up
2590 *
2591 * @rdev: radeon_device pointer
2592 * @ring: radeon_ring structure holding ring information
2593 *
2594 * Check if the async DMA engine is locked up.
2595 * Returns true if the engine appears to be locked up, false if not.
2596 */
2597bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2598{
2599 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
2600
2601 if (!(reset_mask & RADEON_RESET_DMA)) {
2602 radeon_ring_lockup_update(ring);
2603 return false;
2604 }
2605 /* force ring activities */
2606 radeon_ring_force_activity(rdev, ring);
2607 return radeon_ring_test_lockup(rdev, ring);
2459} 2608}
2460 2609
2461/* Interrupts */ 2610/* Interrupts */
@@ -3280,14 +3429,14 @@ void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3280 struct radeon_ring *ring = &rdev->ring[fence->ring]; 3429 struct radeon_ring *ring = &rdev->ring[fence->ring];
3281 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; 3430 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3282 /* write the fence */ 3431 /* write the fence */
3283 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0)); 3432 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0));
3284 radeon_ring_write(ring, addr & 0xfffffffc); 3433 radeon_ring_write(ring, addr & 0xfffffffc);
3285 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); 3434 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3286 radeon_ring_write(ring, fence->seq); 3435 radeon_ring_write(ring, fence->seq);
3287 /* generate an interrupt */ 3436 /* generate an interrupt */
3288 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0)); 3437 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0));
3289 /* flush HDP */ 3438 /* flush HDP */
3290 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); 3439 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0));
3291 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); 3440 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3292 radeon_ring_write(ring, 1); 3441 radeon_ring_write(ring, 1);
3293} 3442}
@@ -3310,7 +3459,7 @@ void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3310 while ((next_rptr & 7) != 5) 3459 while ((next_rptr & 7) != 5)
3311 next_rptr++; 3460 next_rptr++;
3312 next_rptr += 3; 3461 next_rptr += 3;
3313 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); 3462 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1));
3314 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 3463 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3315 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); 3464 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3316 radeon_ring_write(ring, next_rptr); 3465 radeon_ring_write(ring, next_rptr);
@@ -3320,8 +3469,8 @@ void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3320 * Pad as necessary with NOPs. 3469 * Pad as necessary with NOPs.
3321 */ 3470 */
3322 while ((ring->wptr & 7) != 5) 3471 while ((ring->wptr & 7) != 5)
3323 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3472 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3324 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0)); 3473 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0));
3325 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); 3474 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3326 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); 3475 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3327 3476
@@ -3380,7 +3529,7 @@ int evergreen_copy_dma(struct radeon_device *rdev,
3380 if (cur_size_in_dw > 0xFFFFF) 3529 if (cur_size_in_dw > 0xFFFFF)
3381 cur_size_in_dw = 0xFFFFF; 3530 cur_size_in_dw = 0xFFFFF;
3382 size_in_dw -= cur_size_in_dw; 3531 size_in_dw -= cur_size_in_dw;
3383 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw)); 3532 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, cur_size_in_dw));
3384 radeon_ring_write(ring, dst_offset & 0xfffffffc); 3533 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3385 radeon_ring_write(ring, src_offset & 0xfffffffc); 3534 radeon_ring_write(ring, src_offset & 0xfffffffc);
3386 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); 3535 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
@@ -3488,7 +3637,7 @@ static int evergreen_startup(struct radeon_device *rdev)
3488 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3637 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3489 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 3638 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3490 DMA_RB_RPTR, DMA_RB_WPTR, 3639 DMA_RB_RPTR, DMA_RB_WPTR,
3491 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3640 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0));
3492 if (r) 3641 if (r)
3493 return r; 3642 return r;
3494 3643
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 7a445666e71f..d8f5d5fcd303 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -36,9 +36,6 @@
36 36
37int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 37int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
38 struct radeon_cs_reloc **cs_reloc); 38 struct radeon_cs_reloc **cs_reloc);
39static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
40 struct radeon_cs_reloc **cs_reloc);
41
42struct evergreen_cs_track { 39struct evergreen_cs_track {
43 u32 group_size; 40 u32 group_size;
44 u32 nbanks; 41 u32 nbanks;
@@ -1009,223 +1006,35 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
1009} 1006}
1010 1007
1011/** 1008/**
1012 * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet 1009 * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet
1013 * @parser: parser structure holding parsing context.
1014 * @pkt: where to store packet informations
1015 *
1016 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1017 * if packet is bigger than remaining ib size. or if packets is unknown.
1018 **/
1019static int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
1020 struct radeon_cs_packet *pkt,
1021 unsigned idx)
1022{
1023 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1024 uint32_t header;
1025
1026 if (idx >= ib_chunk->length_dw) {
1027 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1028 idx, ib_chunk->length_dw);
1029 return -EINVAL;
1030 }
1031 header = radeon_get_ib_value(p, idx);
1032 pkt->idx = idx;
1033 pkt->type = CP_PACKET_GET_TYPE(header);
1034 pkt->count = CP_PACKET_GET_COUNT(header);
1035 pkt->one_reg_wr = 0;
1036 switch (pkt->type) {
1037 case PACKET_TYPE0:
1038 pkt->reg = CP_PACKET0_GET_REG(header);
1039 break;
1040 case PACKET_TYPE3:
1041 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1042 break;
1043 case PACKET_TYPE2:
1044 pkt->count = -1;
1045 break;
1046 default:
1047 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1048 return -EINVAL;
1049 }
1050 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1051 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1052 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1053 return -EINVAL;
1054 }
1055 return 0;
1056}
1057
1058/**
1059 * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1060 * @parser: parser structure holding parsing context. 1010 * @parser: parser structure holding parsing context.
1061 * @data: pointer to relocation data
1062 * @offset_start: starting offset
1063 * @offset_mask: offset mask (to align start offset on)
1064 * @reloc: reloc informations
1065 * 1011 *
1066 * Check next packet is relocation packet3, do bo validation and compute 1012 * This is an Evergreen(+)-specific function for parsing VLINE packets.
1067 * GPU offset using the provided start. 1013 * Real work is done by r600_cs_common_vline_parse function.
1068 **/ 1014 * Here we just set up ASIC-specific register table and call
1069static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 1015 * the common implementation function.
1070 struct radeon_cs_reloc **cs_reloc)
1071{
1072 struct radeon_cs_chunk *relocs_chunk;
1073 struct radeon_cs_packet p3reloc;
1074 unsigned idx;
1075 int r;
1076
1077 if (p->chunk_relocs_idx == -1) {
1078 DRM_ERROR("No relocation chunk !\n");
1079 return -EINVAL;
1080 }
1081 *cs_reloc = NULL;
1082 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1083 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
1084 if (r) {
1085 return r;
1086 }
1087 p->idx += p3reloc.count + 2;
1088 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1089 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1090 p3reloc.idx);
1091 return -EINVAL;
1092 }
1093 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1094 if (idx >= relocs_chunk->length_dw) {
1095 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1096 idx, relocs_chunk->length_dw);
1097 return -EINVAL;
1098 }
1099 /* FIXME: we assume reloc size is 4 dwords */
1100 *cs_reloc = p->relocs_ptr[(idx / 4)];
1101 return 0;
1102}
1103
1104/**
1105 * evergreen_cs_packet_next_is_pkt3_nop() - test if the next packet is NOP
1106 * @p: structure holding the parser context.
1107 *
1108 * Check if the next packet is a relocation packet3.
1109 **/
1110static bool evergreen_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
1111{
1112 struct radeon_cs_packet p3reloc;
1113 int r;
1114
1115 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
1116 if (r) {
1117 return false;
1118 }
1119 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1120 return false;
1121 }
1122 return true;
1123}
1124
1125/**
1126 * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
1127 * @parser: parser structure holding parsing context.
1128 *
1129 * Userspace sends a special sequence for VLINE waits.
1130 * PACKET0 - VLINE_START_END + value
1131 * PACKET3 - WAIT_REG_MEM poll vline status reg
1132 * RELOC (P3) - crtc_id in reloc.
1133 *
1134 * This function parses this and relocates the VLINE START END
1135 * and WAIT_REG_MEM packets to the correct crtc.
1136 * It also detects a switched off crtc and nulls out the
1137 * wait in that case.
1138 */ 1016 */
1139static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p) 1017static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
1140{ 1018{
1141 struct drm_mode_object *obj;
1142 struct drm_crtc *crtc;
1143 struct radeon_crtc *radeon_crtc;
1144 struct radeon_cs_packet p3reloc, wait_reg_mem;
1145 int crtc_id;
1146 int r;
1147 uint32_t header, h_idx, reg, wait_reg_mem_info;
1148 volatile uint32_t *ib;
1149
1150 ib = p->ib.ptr;
1151
1152 /* parse the WAIT_REG_MEM */
1153 r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
1154 if (r)
1155 return r;
1156
1157 /* check its a WAIT_REG_MEM */
1158 if (wait_reg_mem.type != PACKET_TYPE3 ||
1159 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
1160 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
1161 return -EINVAL;
1162 }
1163
1164 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
1165 /* bit 4 is reg (0) or mem (1) */
1166 if (wait_reg_mem_info & 0x10) {
1167 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1168 return -EINVAL;
1169 }
1170 /* waiting for value to be equal */
1171 if ((wait_reg_mem_info & 0x7) != 0x3) {
1172 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1173 return -EINVAL;
1174 }
1175 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
1176 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1177 return -EINVAL;
1178 }
1179
1180 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
1181 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1182 return -EINVAL;
1183 }
1184
1185 /* jump over the NOP */
1186 r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1187 if (r)
1188 return r;
1189
1190 h_idx = p->idx - 2;
1191 p->idx += wait_reg_mem.count + 2;
1192 p->idx += p3reloc.count + 2;
1193 1019
1194 header = radeon_get_ib_value(p, h_idx); 1020 static uint32_t vline_start_end[6] = {
1195 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 1021 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC0_REGISTER_OFFSET,
1196 reg = CP_PACKET0_GET_REG(header); 1022 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC1_REGISTER_OFFSET,
1197 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1023 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC2_REGISTER_OFFSET,
1198 if (!obj) { 1024 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC3_REGISTER_OFFSET,
1199 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1025 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC4_REGISTER_OFFSET,
1200 return -EINVAL; 1026 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET
1201 } 1027 };
1202 crtc = obj_to_crtc(obj); 1028 static uint32_t vline_status[6] = {
1203 radeon_crtc = to_radeon_crtc(crtc); 1029 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1204 crtc_id = radeon_crtc->crtc_id; 1030 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1205 1031 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1206 if (!crtc->enabled) { 1032 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1207 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ 1033 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1208 ib[h_idx + 2] = PACKET2(0); 1034 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET
1209 ib[h_idx + 3] = PACKET2(0); 1035 };
1210 ib[h_idx + 4] = PACKET2(0); 1036
1211 ib[h_idx + 5] = PACKET2(0); 1037 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
1212 ib[h_idx + 6] = PACKET2(0);
1213 ib[h_idx + 7] = PACKET2(0);
1214 ib[h_idx + 8] = PACKET2(0);
1215 } else {
1216 switch (reg) {
1217 case EVERGREEN_VLINE_START_END:
1218 header &= ~R600_CP_PACKET0_REG_MASK;
1219 header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
1220 ib[h_idx] = header;
1221 ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
1222 break;
1223 default:
1224 DRM_ERROR("unknown crtc reloc\n");
1225 return -EINVAL;
1226 }
1227 }
1228 return 0;
1229} 1038}
1230 1039
1231static int evergreen_packet0_check(struct radeon_cs_parser *p, 1040static int evergreen_packet0_check(struct radeon_cs_parser *p,
@@ -1347,7 +1156,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1347 case SQ_LSTMP_RING_BASE: 1156 case SQ_LSTMP_RING_BASE:
1348 case SQ_PSTMP_RING_BASE: 1157 case SQ_PSTMP_RING_BASE:
1349 case SQ_VSTMP_RING_BASE: 1158 case SQ_VSTMP_RING_BASE:
1350 r = evergreen_cs_packet_next_reloc(p, &reloc); 1159 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1351 if (r) { 1160 if (r) {
1352 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1161 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1353 "0x%04X\n", reg); 1162 "0x%04X\n", reg);
@@ -1376,7 +1185,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1376 case DB_Z_INFO: 1185 case DB_Z_INFO:
1377 track->db_z_info = radeon_get_ib_value(p, idx); 1186 track->db_z_info = radeon_get_ib_value(p, idx);
1378 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1187 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1379 r = evergreen_cs_packet_next_reloc(p, &reloc); 1188 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1380 if (r) { 1189 if (r) {
1381 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1190 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1382 "0x%04X\n", reg); 1191 "0x%04X\n", reg);
@@ -1418,7 +1227,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1418 track->db_dirty = true; 1227 track->db_dirty = true;
1419 break; 1228 break;
1420 case DB_Z_READ_BASE: 1229 case DB_Z_READ_BASE:
1421 r = evergreen_cs_packet_next_reloc(p, &reloc); 1230 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1422 if (r) { 1231 if (r) {
1423 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1232 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1424 "0x%04X\n", reg); 1233 "0x%04X\n", reg);
@@ -1430,7 +1239,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1430 track->db_dirty = true; 1239 track->db_dirty = true;
1431 break; 1240 break;
1432 case DB_Z_WRITE_BASE: 1241 case DB_Z_WRITE_BASE:
1433 r = evergreen_cs_packet_next_reloc(p, &reloc); 1242 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1434 if (r) { 1243 if (r) {
1435 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1244 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1436 "0x%04X\n", reg); 1245 "0x%04X\n", reg);
@@ -1442,7 +1251,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1442 track->db_dirty = true; 1251 track->db_dirty = true;
1443 break; 1252 break;
1444 case DB_STENCIL_READ_BASE: 1253 case DB_STENCIL_READ_BASE:
1445 r = evergreen_cs_packet_next_reloc(p, &reloc); 1254 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1446 if (r) { 1255 if (r) {
1447 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1256 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1448 "0x%04X\n", reg); 1257 "0x%04X\n", reg);
@@ -1454,7 +1263,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1454 track->db_dirty = true; 1263 track->db_dirty = true;
1455 break; 1264 break;
1456 case DB_STENCIL_WRITE_BASE: 1265 case DB_STENCIL_WRITE_BASE:
1457 r = evergreen_cs_packet_next_reloc(p, &reloc); 1266 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1458 if (r) { 1267 if (r) {
1459 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1268 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1460 "0x%04X\n", reg); 1269 "0x%04X\n", reg);
@@ -1477,7 +1286,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1477 case VGT_STRMOUT_BUFFER_BASE_1: 1286 case VGT_STRMOUT_BUFFER_BASE_1:
1478 case VGT_STRMOUT_BUFFER_BASE_2: 1287 case VGT_STRMOUT_BUFFER_BASE_2:
1479 case VGT_STRMOUT_BUFFER_BASE_3: 1288 case VGT_STRMOUT_BUFFER_BASE_3:
1480 r = evergreen_cs_packet_next_reloc(p, &reloc); 1289 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1481 if (r) { 1290 if (r) {
1482 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1291 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1483 "0x%04X\n", reg); 1292 "0x%04X\n", reg);
@@ -1499,7 +1308,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1499 track->streamout_dirty = true; 1308 track->streamout_dirty = true;
1500 break; 1309 break;
1501 case CP_COHER_BASE: 1310 case CP_COHER_BASE:
1502 r = evergreen_cs_packet_next_reloc(p, &reloc); 1311 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1503 if (r) { 1312 if (r) {
1504 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1313 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1505 "0x%04X\n", reg); 1314 "0x%04X\n", reg);
@@ -1563,7 +1372,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1563 tmp = (reg - CB_COLOR0_INFO) / 0x3c; 1372 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1564 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1373 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1565 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1374 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1566 r = evergreen_cs_packet_next_reloc(p, &reloc); 1375 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1567 if (r) { 1376 if (r) {
1568 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1377 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1569 "0x%04X\n", reg); 1378 "0x%04X\n", reg);
@@ -1581,7 +1390,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1581 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; 1390 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1582 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1391 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1583 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1392 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1584 r = evergreen_cs_packet_next_reloc(p, &reloc); 1393 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1585 if (r) { 1394 if (r) {
1586 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1395 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1587 "0x%04X\n", reg); 1396 "0x%04X\n", reg);
@@ -1642,7 +1451,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1642 case CB_COLOR5_ATTRIB: 1451 case CB_COLOR5_ATTRIB:
1643 case CB_COLOR6_ATTRIB: 1452 case CB_COLOR6_ATTRIB:
1644 case CB_COLOR7_ATTRIB: 1453 case CB_COLOR7_ATTRIB:
1645 r = evergreen_cs_packet_next_reloc(p, &reloc); 1454 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1646 if (r) { 1455 if (r) {
1647 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1456 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1648 "0x%04X\n", reg); 1457 "0x%04X\n", reg);
@@ -1670,7 +1479,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1670 case CB_COLOR9_ATTRIB: 1479 case CB_COLOR9_ATTRIB:
1671 case CB_COLOR10_ATTRIB: 1480 case CB_COLOR10_ATTRIB:
1672 case CB_COLOR11_ATTRIB: 1481 case CB_COLOR11_ATTRIB:
1673 r = evergreen_cs_packet_next_reloc(p, &reloc); 1482 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1674 if (r) { 1483 if (r) {
1675 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1484 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1676 "0x%04X\n", reg); 1485 "0x%04X\n", reg);
@@ -1703,7 +1512,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1703 case CB_COLOR6_FMASK: 1512 case CB_COLOR6_FMASK:
1704 case CB_COLOR7_FMASK: 1513 case CB_COLOR7_FMASK:
1705 tmp = (reg - CB_COLOR0_FMASK) / 0x3c; 1514 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1706 r = evergreen_cs_packet_next_reloc(p, &reloc); 1515 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1707 if (r) { 1516 if (r) {
1708 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1517 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1709 return -EINVAL; 1518 return -EINVAL;
@@ -1720,7 +1529,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1720 case CB_COLOR6_CMASK: 1529 case CB_COLOR6_CMASK:
1721 case CB_COLOR7_CMASK: 1530 case CB_COLOR7_CMASK:
1722 tmp = (reg - CB_COLOR0_CMASK) / 0x3c; 1531 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1723 r = evergreen_cs_packet_next_reloc(p, &reloc); 1532 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1724 if (r) { 1533 if (r) {
1725 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1534 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1726 return -EINVAL; 1535 return -EINVAL;
@@ -1758,7 +1567,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1758 case CB_COLOR5_BASE: 1567 case CB_COLOR5_BASE:
1759 case CB_COLOR6_BASE: 1568 case CB_COLOR6_BASE:
1760 case CB_COLOR7_BASE: 1569 case CB_COLOR7_BASE:
1761 r = evergreen_cs_packet_next_reloc(p, &reloc); 1570 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1762 if (r) { 1571 if (r) {
1763 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1572 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1764 "0x%04X\n", reg); 1573 "0x%04X\n", reg);
@@ -1774,7 +1583,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1774 case CB_COLOR9_BASE: 1583 case CB_COLOR9_BASE:
1775 case CB_COLOR10_BASE: 1584 case CB_COLOR10_BASE:
1776 case CB_COLOR11_BASE: 1585 case CB_COLOR11_BASE:
1777 r = evergreen_cs_packet_next_reloc(p, &reloc); 1586 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1778 if (r) { 1587 if (r) {
1779 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1588 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1780 "0x%04X\n", reg); 1589 "0x%04X\n", reg);
@@ -1787,7 +1596,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1787 track->cb_dirty = true; 1596 track->cb_dirty = true;
1788 break; 1597 break;
1789 case DB_HTILE_DATA_BASE: 1598 case DB_HTILE_DATA_BASE:
1790 r = evergreen_cs_packet_next_reloc(p, &reloc); 1599 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1791 if (r) { 1600 if (r) {
1792 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1601 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1793 "0x%04X\n", reg); 1602 "0x%04X\n", reg);
@@ -1905,7 +1714,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1905 case SQ_ALU_CONST_CACHE_LS_13: 1714 case SQ_ALU_CONST_CACHE_LS_13:
1906 case SQ_ALU_CONST_CACHE_LS_14: 1715 case SQ_ALU_CONST_CACHE_LS_14:
1907 case SQ_ALU_CONST_CACHE_LS_15: 1716 case SQ_ALU_CONST_CACHE_LS_15:
1908 r = evergreen_cs_packet_next_reloc(p, &reloc); 1717 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1909 if (r) { 1718 if (r) {
1910 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1719 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1911 "0x%04X\n", reg); 1720 "0x%04X\n", reg);
@@ -1919,7 +1728,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1919 "0x%04X\n", reg); 1728 "0x%04X\n", reg);
1920 return -EINVAL; 1729 return -EINVAL;
1921 } 1730 }
1922 r = evergreen_cs_packet_next_reloc(p, &reloc); 1731 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1923 if (r) { 1732 if (r) {
1924 dev_warn(p->dev, "bad SET_CONFIG_REG " 1733 dev_warn(p->dev, "bad SET_CONFIG_REG "
1925 "0x%04X\n", reg); 1734 "0x%04X\n", reg);
@@ -1933,7 +1742,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1933 "0x%04X\n", reg); 1742 "0x%04X\n", reg);
1934 return -EINVAL; 1743 return -EINVAL;
1935 } 1744 }
1936 r = evergreen_cs_packet_next_reloc(p, &reloc); 1745 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1937 if (r) { 1746 if (r) {
1938 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1747 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1939 "0x%04X\n", reg); 1748 "0x%04X\n", reg);
@@ -2018,7 +1827,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2018 return -EINVAL; 1827 return -EINVAL;
2019 } 1828 }
2020 1829
2021 r = evergreen_cs_packet_next_reloc(p, &reloc); 1830 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2022 if (r) { 1831 if (r) {
2023 DRM_ERROR("bad SET PREDICATION\n"); 1832 DRM_ERROR("bad SET PREDICATION\n");
2024 return -EINVAL; 1833 return -EINVAL;
@@ -2064,7 +1873,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2064 DRM_ERROR("bad INDEX_BASE\n"); 1873 DRM_ERROR("bad INDEX_BASE\n");
2065 return -EINVAL; 1874 return -EINVAL;
2066 } 1875 }
2067 r = evergreen_cs_packet_next_reloc(p, &reloc); 1876 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2068 if (r) { 1877 if (r) {
2069 DRM_ERROR("bad INDEX_BASE\n"); 1878 DRM_ERROR("bad INDEX_BASE\n");
2070 return -EINVAL; 1879 return -EINVAL;
@@ -2091,7 +1900,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2091 DRM_ERROR("bad DRAW_INDEX\n"); 1900 DRM_ERROR("bad DRAW_INDEX\n");
2092 return -EINVAL; 1901 return -EINVAL;
2093 } 1902 }
2094 r = evergreen_cs_packet_next_reloc(p, &reloc); 1903 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2095 if (r) { 1904 if (r) {
2096 DRM_ERROR("bad DRAW_INDEX\n"); 1905 DRM_ERROR("bad DRAW_INDEX\n");
2097 return -EINVAL; 1906 return -EINVAL;
@@ -2119,7 +1928,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2119 DRM_ERROR("bad DRAW_INDEX_2\n"); 1928 DRM_ERROR("bad DRAW_INDEX_2\n");
2120 return -EINVAL; 1929 return -EINVAL;
2121 } 1930 }
2122 r = evergreen_cs_packet_next_reloc(p, &reloc); 1931 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2123 if (r) { 1932 if (r) {
2124 DRM_ERROR("bad DRAW_INDEX_2\n"); 1933 DRM_ERROR("bad DRAW_INDEX_2\n");
2125 return -EINVAL; 1934 return -EINVAL;
@@ -2210,7 +2019,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2210 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2019 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2211 return -EINVAL; 2020 return -EINVAL;
2212 } 2021 }
2213 r = evergreen_cs_packet_next_reloc(p, &reloc); 2022 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2214 if (r) { 2023 if (r) {
2215 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2024 DRM_ERROR("bad DISPATCH_INDIRECT\n");
2216 return -EINVAL; 2025 return -EINVAL;
@@ -2231,7 +2040,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2231 if (idx_value & 0x10) { 2040 if (idx_value & 0x10) {
2232 uint64_t offset; 2041 uint64_t offset;
2233 2042
2234 r = evergreen_cs_packet_next_reloc(p, &reloc); 2043 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2235 if (r) { 2044 if (r) {
2236 DRM_ERROR("bad WAIT_REG_MEM\n"); 2045 DRM_ERROR("bad WAIT_REG_MEM\n");
2237 return -EINVAL; 2046 return -EINVAL;
@@ -2243,6 +2052,9 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2243 2052
2244 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); 2053 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2245 ib[idx+2] = upper_32_bits(offset) & 0xff; 2054 ib[idx+2] = upper_32_bits(offset) & 0xff;
2055 } else if (idx_value & 0x100) {
2056 DRM_ERROR("cannot use PFP on REG wait\n");
2057 return -EINVAL;
2246 } 2058 }
2247 break; 2059 break;
2248 case PACKET3_CP_DMA: 2060 case PACKET3_CP_DMA:
@@ -2282,7 +2094,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2282 } 2094 }
2283 /* src address space is memory */ 2095 /* src address space is memory */
2284 if (((info & 0x60000000) >> 29) == 0) { 2096 if (((info & 0x60000000) >> 29) == 0) {
2285 r = evergreen_cs_packet_next_reloc(p, &reloc); 2097 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2286 if (r) { 2098 if (r) {
2287 DRM_ERROR("bad CP DMA SRC\n"); 2099 DRM_ERROR("bad CP DMA SRC\n");
2288 return -EINVAL; 2100 return -EINVAL;
@@ -2320,7 +2132,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2320 return -EINVAL; 2132 return -EINVAL;
2321 } 2133 }
2322 if (((info & 0x00300000) >> 20) == 0) { 2134 if (((info & 0x00300000) >> 20) == 0) {
2323 r = evergreen_cs_packet_next_reloc(p, &reloc); 2135 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2324 if (r) { 2136 if (r) {
2325 DRM_ERROR("bad CP DMA DST\n"); 2137 DRM_ERROR("bad CP DMA DST\n");
2326 return -EINVAL; 2138 return -EINVAL;
@@ -2354,7 +2166,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2354 /* 0xffffffff/0x0 is flush all cache flag */ 2166 /* 0xffffffff/0x0 is flush all cache flag */
2355 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 2167 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2356 radeon_get_ib_value(p, idx + 2) != 0) { 2168 radeon_get_ib_value(p, idx + 2) != 0) {
2357 r = evergreen_cs_packet_next_reloc(p, &reloc); 2169 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2358 if (r) { 2170 if (r) {
2359 DRM_ERROR("bad SURFACE_SYNC\n"); 2171 DRM_ERROR("bad SURFACE_SYNC\n");
2360 return -EINVAL; 2172 return -EINVAL;
@@ -2370,7 +2182,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2370 if (pkt->count) { 2182 if (pkt->count) {
2371 uint64_t offset; 2183 uint64_t offset;
2372 2184
2373 r = evergreen_cs_packet_next_reloc(p, &reloc); 2185 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2374 if (r) { 2186 if (r) {
2375 DRM_ERROR("bad EVENT_WRITE\n"); 2187 DRM_ERROR("bad EVENT_WRITE\n");
2376 return -EINVAL; 2188 return -EINVAL;
@@ -2391,7 +2203,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2391 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2203 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2392 return -EINVAL; 2204 return -EINVAL;
2393 } 2205 }
2394 r = evergreen_cs_packet_next_reloc(p, &reloc); 2206 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2395 if (r) { 2207 if (r) {
2396 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2208 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2397 return -EINVAL; 2209 return -EINVAL;
@@ -2413,7 +2225,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2413 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2225 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2414 return -EINVAL; 2226 return -EINVAL;
2415 } 2227 }
2416 r = evergreen_cs_packet_next_reloc(p, &reloc); 2228 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2417 if (r) { 2229 if (r) {
2418 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2230 DRM_ERROR("bad EVENT_WRITE_EOS\n");
2419 return -EINVAL; 2231 return -EINVAL;
@@ -2480,7 +2292,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2480 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { 2292 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2481 case SQ_TEX_VTX_VALID_TEXTURE: 2293 case SQ_TEX_VTX_VALID_TEXTURE:
2482 /* tex base */ 2294 /* tex base */
2483 r = evergreen_cs_packet_next_reloc(p, &reloc); 2295 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2484 if (r) { 2296 if (r) {
2485 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2297 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2486 return -EINVAL; 2298 return -EINVAL;
@@ -2511,13 +2323,13 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2511 2323
2512 if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) && 2324 if ((tex_dim == SQ_TEX_DIM_2D_MSAA || tex_dim == SQ_TEX_DIM_2D_ARRAY_MSAA) &&
2513 !mip_address && 2325 !mip_address &&
2514 !evergreen_cs_packet_next_is_pkt3_nop(p)) { 2326 !radeon_cs_packet_next_is_pkt3_nop(p)) {
2515 /* MIP_ADDRESS should point to FMASK for an MSAA texture. 2327 /* MIP_ADDRESS should point to FMASK for an MSAA texture.
2516 * It should be 0 if FMASK is disabled. */ 2328 * It should be 0 if FMASK is disabled. */
2517 moffset = 0; 2329 moffset = 0;
2518 mipmap = NULL; 2330 mipmap = NULL;
2519 } else { 2331 } else {
2520 r = evergreen_cs_packet_next_reloc(p, &reloc); 2332 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2521 if (r) { 2333 if (r) {
2522 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2334 DRM_ERROR("bad SET_RESOURCE (tex)\n");
2523 return -EINVAL; 2335 return -EINVAL;
@@ -2536,7 +2348,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2536 { 2348 {
2537 uint64_t offset64; 2349 uint64_t offset64;
2538 /* vtx base */ 2350 /* vtx base */
2539 r = evergreen_cs_packet_next_reloc(p, &reloc); 2351 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2540 if (r) { 2352 if (r) {
2541 DRM_ERROR("bad SET_RESOURCE (vtx)\n"); 2353 DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2542 return -EINVAL; 2354 return -EINVAL;
@@ -2618,7 +2430,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2618 /* Updating memory at DST_ADDRESS. */ 2430 /* Updating memory at DST_ADDRESS. */
2619 if (idx_value & 0x1) { 2431 if (idx_value & 0x1) {
2620 u64 offset; 2432 u64 offset;
2621 r = evergreen_cs_packet_next_reloc(p, &reloc); 2433 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2622 if (r) { 2434 if (r) {
2623 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2435 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2624 return -EINVAL; 2436 return -EINVAL;
@@ -2637,7 +2449,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2637 /* Reading data from SRC_ADDRESS. */ 2449 /* Reading data from SRC_ADDRESS. */
2638 if (((idx_value >> 1) & 0x3) == 2) { 2450 if (((idx_value >> 1) & 0x3) == 2) {
2639 u64 offset; 2451 u64 offset;
2640 r = evergreen_cs_packet_next_reloc(p, &reloc); 2452 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2641 if (r) { 2453 if (r) {
2642 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2454 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2643 return -EINVAL; 2455 return -EINVAL;
@@ -2662,7 +2474,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2662 DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2474 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2663 return -EINVAL; 2475 return -EINVAL;
2664 } 2476 }
2665 r = evergreen_cs_packet_next_reloc(p, &reloc); 2477 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2666 if (r) { 2478 if (r) {
2667 DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2479 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2668 return -EINVAL; 2480 return -EINVAL;
@@ -2691,7 +2503,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2691 if (idx_value & 0x1) { 2503 if (idx_value & 0x1) {
2692 u64 offset; 2504 u64 offset;
2693 /* SRC is memory. */ 2505 /* SRC is memory. */
2694 r = evergreen_cs_packet_next_reloc(p, &reloc); 2506 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2695 if (r) { 2507 if (r) {
2696 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2508 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2697 return -EINVAL; 2509 return -EINVAL;
@@ -2715,7 +2527,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
2715 if (idx_value & 0x2) { 2527 if (idx_value & 0x2) {
2716 u64 offset; 2528 u64 offset;
2717 /* DST is memory. */ 2529 /* DST is memory. */
2718 r = evergreen_cs_packet_next_reloc(p, &reloc); 2530 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2719 if (r) { 2531 if (r) {
2720 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2532 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2721 return -EINVAL; 2533 return -EINVAL;
@@ -2819,7 +2631,7 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
2819 p->track = track; 2631 p->track = track;
2820 } 2632 }
2821 do { 2633 do {
2822 r = evergreen_cs_packet_parse(p, &pkt, p->idx); 2634 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2823 if (r) { 2635 if (r) {
2824 kfree(p->track); 2636 kfree(p->track);
2825 p->track = NULL; 2637 p->track = NULL;
@@ -2827,12 +2639,12 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
2827 } 2639 }
2828 p->idx += pkt.count + 2; 2640 p->idx += pkt.count + 2;
2829 switch (pkt.type) { 2641 switch (pkt.type) {
2830 case PACKET_TYPE0: 2642 case RADEON_PACKET_TYPE0:
2831 r = evergreen_cs_parse_packet0(p, &pkt); 2643 r = evergreen_cs_parse_packet0(p, &pkt);
2832 break; 2644 break;
2833 case PACKET_TYPE2: 2645 case RADEON_PACKET_TYPE2:
2834 break; 2646 break;
2835 case PACKET_TYPE3: 2647 case RADEON_PACKET_TYPE3:
2836 r = evergreen_packet3_check(p, &pkt); 2648 r = evergreen_packet3_check(p, &pkt);
2837 break; 2649 break;
2838 default: 2650 default:
@@ -2858,16 +2670,6 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
2858 return 0; 2670 return 0;
2859} 2671}
2860 2672
2861/*
2862 * DMA
2863 */
2864
2865#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
2866#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
2867#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
2868#define GET_DMA_NEW(h) (((h) & 0x04000000) >> 26)
2869#define GET_DMA_MISC(h) (((h) & 0x0700000) >> 20)
2870
2871/** 2673/**
2872 * evergreen_dma_cs_parse() - parse the DMA IB 2674 * evergreen_dma_cs_parse() - parse the DMA IB
2873 * @p: parser structure holding parsing context. 2675 * @p: parser structure holding parsing context.
@@ -2881,9 +2683,9 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
2881{ 2683{
2882 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx]; 2684 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
2883 struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc; 2685 struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;
2884 u32 header, cmd, count, tiled, new_cmd, misc; 2686 u32 header, cmd, count, sub_cmd;
2885 volatile u32 *ib = p->ib.ptr; 2687 volatile u32 *ib = p->ib.ptr;
2886 u32 idx, idx_value; 2688 u32 idx;
2887 u64 src_offset, dst_offset, dst2_offset; 2689 u64 src_offset, dst_offset, dst2_offset;
2888 int r; 2690 int r;
2889 2691
@@ -2897,9 +2699,7 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
2897 header = radeon_get_ib_value(p, idx); 2699 header = radeon_get_ib_value(p, idx);
2898 cmd = GET_DMA_CMD(header); 2700 cmd = GET_DMA_CMD(header);
2899 count = GET_DMA_COUNT(header); 2701 count = GET_DMA_COUNT(header);
2900 tiled = GET_DMA_T(header); 2702 sub_cmd = GET_DMA_SUB_CMD(header);
2901 new_cmd = GET_DMA_NEW(header);
2902 misc = GET_DMA_MISC(header);
2903 2703
2904 switch (cmd) { 2704 switch (cmd) {
2905 case DMA_PACKET_WRITE: 2705 case DMA_PACKET_WRITE:
@@ -2908,19 +2708,27 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
2908 DRM_ERROR("bad DMA_PACKET_WRITE\n"); 2708 DRM_ERROR("bad DMA_PACKET_WRITE\n");
2909 return -EINVAL; 2709 return -EINVAL;
2910 } 2710 }
2911 if (tiled) { 2711 switch (sub_cmd) {
2712 /* tiled */
2713 case 8:
2912 dst_offset = ib[idx+1]; 2714 dst_offset = ib[idx+1];
2913 dst_offset <<= 8; 2715 dst_offset <<= 8;
2914 2716
2915 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2717 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2916 p->idx += count + 7; 2718 p->idx += count + 7;
2917 } else { 2719 break;
2720 /* linear */
2721 case 0:
2918 dst_offset = ib[idx+1]; 2722 dst_offset = ib[idx+1];
2919 dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32; 2723 dst_offset |= ((u64)(ib[idx+2] & 0xff)) << 32;
2920 2724
2921 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2725 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2922 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2726 ib[idx+2] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2923 p->idx += count + 3; 2727 p->idx += count + 3;
2728 break;
2729 default:
2730 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib[idx+0]);
2731 return -EINVAL;
2924 } 2732 }
2925 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2733 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2926 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n", 2734 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",
@@ -2939,338 +2747,330 @@ int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
2939 DRM_ERROR("bad DMA_PACKET_COPY\n"); 2747 DRM_ERROR("bad DMA_PACKET_COPY\n");
2940 return -EINVAL; 2748 return -EINVAL;
2941 } 2749 }
2942 if (tiled) { 2750 switch (sub_cmd) {
2943 idx_value = radeon_get_ib_value(p, idx + 2); 2751 /* Copy L2L, DW aligned */
2944 if (new_cmd) { 2752 case 0x00:
2945 switch (misc) { 2753 /* L2L, dw */
2946 case 0: 2754 src_offset = ib[idx+2];
2947 /* L2T, frame to fields */ 2755 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
2948 if (idx_value & (1 << 31)) { 2756 dst_offset = ib[idx+1];
2949 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); 2757 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
2950 return -EINVAL; 2758 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2951 } 2759 dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
2952 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 2760 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2953 if (r) { 2761 return -EINVAL;
2954 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n"); 2762 }
2955 return -EINVAL; 2763 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2956 } 2764 dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
2957 dst_offset = ib[idx+1]; 2765 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2958 dst_offset <<= 8; 2766 return -EINVAL;
2959 dst2_offset = ib[idx+2]; 2767 }
2960 dst2_offset <<= 8; 2768 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2961 src_offset = ib[idx+8]; 2769 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2962 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32; 2770 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2963 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2771 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2964 dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n", 2772 p->idx += 5;
2965 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2773 break;
2966 return -EINVAL; 2774 /* Copy L2T/T2L */
2967 } 2775 case 0x08:
2968 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2776 /* detile bit */
2969 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", 2777 if (ib[idx + 2] & (1 << 31)) {
2970 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2778 /* tiled src, linear dst */
2971 return -EINVAL; 2779 src_offset = ib[idx+1];
2972 } 2780 src_offset <<= 8;
2973 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 2781 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2974 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n", 2782
2975 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 2783 dst_offset = radeon_get_ib_value(p, idx + 7);
2976 return -EINVAL; 2784 dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
2977 } 2785 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2978 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8); 2786 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2979 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2980 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2981 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2982 p->idx += 10;
2983 break;
2984 case 1:
2985 /* L2T, T2L partial */
2986 if (p->family < CHIP_CAYMAN) {
2987 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
2988 return -EINVAL;
2989 }
2990 /* detile bit */
2991 if (idx_value & (1 << 31)) {
2992 /* tiled src, linear dst */
2993 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2994
2995 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2996 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2997 } else {
2998 /* linear src, tiled dst */
2999 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3000 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3001
3002 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3003 }
3004 p->idx += 12;
3005 break;
3006 case 3:
3007 /* L2T, broadcast */
3008 if (idx_value & (1 << 31)) {
3009 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3010 return -EINVAL;
3011 }
3012 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
3013 if (r) {
3014 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3015 return -EINVAL;
3016 }
3017 dst_offset = ib[idx+1];
3018 dst_offset <<= 8;
3019 dst2_offset = ib[idx+2];
3020 dst2_offset <<= 8;
3021 src_offset = ib[idx+8];
3022 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
3023 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3024 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3025 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3026 return -EINVAL;
3027 }
3028 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3029 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3030 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3031 return -EINVAL;
3032 }
3033 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3034 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
3035 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3036 return -EINVAL;
3037 }
3038 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3039 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
3040 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3041 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3042 p->idx += 10;
3043 break;
3044 case 4:
3045 /* L2T, T2L */
3046 /* detile bit */
3047 if (idx_value & (1 << 31)) {
3048 /* tiled src, linear dst */
3049 src_offset = ib[idx+1];
3050 src_offset <<= 8;
3051 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3052
3053 dst_offset = ib[idx+7];
3054 dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3055 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3056 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3057 } else {
3058 /* linear src, tiled dst */
3059 src_offset = ib[idx+7];
3060 src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3061 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3062 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3063
3064 dst_offset = ib[idx+1];
3065 dst_offset <<= 8;
3066 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3067 }
3068 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3069 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
3070 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3071 return -EINVAL;
3072 }
3073 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3074 dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
3075 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3076 return -EINVAL;
3077 }
3078 p->idx += 9;
3079 break;
3080 case 5:
3081 /* T2T partial */
3082 if (p->family < CHIP_CAYMAN) {
3083 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
3084 return -EINVAL;
3085 }
3086 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3087 ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3088 p->idx += 13;
3089 break;
3090 case 7:
3091 /* L2T, broadcast */
3092 if (idx_value & (1 << 31)) {
3093 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3094 return -EINVAL;
3095 }
3096 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
3097 if (r) {
3098 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3099 return -EINVAL;
3100 }
3101 dst_offset = ib[idx+1];
3102 dst_offset <<= 8;
3103 dst2_offset = ib[idx+2];
3104 dst2_offset <<= 8;
3105 src_offset = ib[idx+8];
3106 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
3107 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3108 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3109 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3110 return -EINVAL;
3111 }
3112 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3113 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3114 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3115 return -EINVAL;
3116 }
3117 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3118 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
3119 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3120 return -EINVAL;
3121 }
3122 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3123 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
3124 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3125 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3126 p->idx += 10;
3127 break;
3128 default:
3129 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3130 return -EINVAL;
3131 }
3132 } else { 2787 } else {
3133 switch (misc) { 2788 /* linear src, tiled dst */
3134 case 0: 2789 src_offset = ib[idx+7];
3135 /* detile bit */ 2790 src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3136 if (idx_value & (1 << 31)) { 2791 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3137 /* tiled src, linear dst */ 2792 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3138 src_offset = ib[idx+1]; 2793
3139 src_offset <<= 8; 2794 dst_offset = ib[idx+1];
3140 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8); 2795 dst_offset <<= 8;
3141 2796 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3142 dst_offset = ib[idx+7];
3143 dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3144 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3145 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3146 } else {
3147 /* linear src, tiled dst */
3148 src_offset = ib[idx+7];
3149 src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3150 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3151 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3152
3153 dst_offset = ib[idx+1];
3154 dst_offset <<= 8;
3155 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3156 }
3157 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3158 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3159 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3160 return -EINVAL;
3161 }
3162 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3163 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3164 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3165 return -EINVAL;
3166 }
3167 p->idx += 9;
3168 break;
3169 default:
3170 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3171 return -EINVAL;
3172 }
3173 } 2797 }
3174 } else { 2798 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3175 if (new_cmd) { 2799 dev_warn(p->dev, "DMA L2T, src buffer too small (%llu %lu)\n",
3176 switch (misc) { 2800 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3177 case 0: 2801 return -EINVAL;
3178 /* L2L, byte */ 2802 }
3179 src_offset = ib[idx+2]; 2803 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3180 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32; 2804 dev_warn(p->dev, "DMA L2T, dst buffer too small (%llu %lu)\n",
3181 dst_offset = ib[idx+1]; 2805 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3182 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32; 2806 return -EINVAL;
3183 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) { 2807 }
3184 dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n", 2808 p->idx += 9;
3185 src_offset + count, radeon_bo_size(src_reloc->robj)); 2809 break;
3186 return -EINVAL; 2810 /* Copy L2L, byte aligned */
3187 } 2811 case 0x40:
3188 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { 2812 /* L2L, byte */
3189 dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n", 2813 src_offset = ib[idx+2];
3190 dst_offset + count, radeon_bo_size(dst_reloc->robj)); 2814 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
3191 return -EINVAL; 2815 dst_offset = ib[idx+1];
3192 } 2816 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32;
3193 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); 2817 if ((src_offset + count) > radeon_bo_size(src_reloc->robj)) {
3194 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); 2818 dev_warn(p->dev, "DMA L2L, byte src buffer too small (%llu %lu)\n",
3195 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2819 src_offset + count, radeon_bo_size(src_reloc->robj));
3196 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2820 return -EINVAL;
3197 p->idx += 5; 2821 }
3198 break; 2822 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) {
3199 case 1: 2823 dev_warn(p->dev, "DMA L2L, byte dst buffer too small (%llu %lu)\n",
3200 /* L2L, partial */ 2824 dst_offset + count, radeon_bo_size(dst_reloc->robj));
3201 if (p->family < CHIP_CAYMAN) { 2825 return -EINVAL;
3202 DRM_ERROR("L2L Partial is cayman only !\n"); 2826 }
3203 return -EINVAL; 2827 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3204 } 2828 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3205 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff); 2829 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3206 ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2830 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3207 ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff); 2831 p->idx += 5;
3208 ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2832 break;
3209 2833 /* Copy L2L, partial */
3210 p->idx += 9; 2834 case 0x41:
3211 break; 2835 /* L2L, partial */
3212 case 4: 2836 if (p->family < CHIP_CAYMAN) {
3213 /* L2L, dw, broadcast */ 2837 DRM_ERROR("L2L Partial is cayman only !\n");
3214 r = r600_dma_cs_next_reloc(p, &dst2_reloc); 2838 return -EINVAL;
3215 if (r) { 2839 }
3216 DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n"); 2840 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset & 0xffffffff);
3217 return -EINVAL; 2841 ib[idx+2] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3218 } 2842 ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset & 0xffffffff);
3219 dst_offset = ib[idx+1]; 2843 ib[idx+5] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3220 dst_offset |= ((u64)(ib[idx+4] & 0xff)) << 32; 2844
3221 dst2_offset = ib[idx+2]; 2845 p->idx += 9;
3222 dst2_offset |= ((u64)(ib[idx+5] & 0xff)) << 32; 2846 break;
3223 src_offset = ib[idx+3]; 2847 /* Copy L2L, DW aligned, broadcast */
3224 src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32; 2848 case 0x44:
3225 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 2849 /* L2L, dw, broadcast */
3226 dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n", 2850 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
3227 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); 2851 if (r) {
3228 return -EINVAL; 2852 DRM_ERROR("bad L2L, dw, broadcast DMA_PACKET_COPY\n");
3229 } 2853 return -EINVAL;
3230 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { 2854 }
3231 dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n", 2855 dst_offset = ib[idx+1];
3232 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); 2856 dst_offset |= ((u64)(ib[idx+4] & 0xff)) << 32;
3233 return -EINVAL; 2857 dst2_offset = ib[idx+2];
3234 } 2858 dst2_offset |= ((u64)(ib[idx+5] & 0xff)) << 32;
3235 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) { 2859 src_offset = ib[idx+3];
3236 dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n", 2860 src_offset |= ((u64)(ib[idx+6] & 0xff)) << 32;
3237 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj)); 2861 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3238 return -EINVAL; 2862 dev_warn(p->dev, "DMA L2L, dw, broadcast src buffer too small (%llu %lu)\n",
3239 } 2863 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3240 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc); 2864 return -EINVAL;
3241 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc); 2865 }
3242 ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc); 2866 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3243 ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff; 2867 dev_warn(p->dev, "DMA L2L, dw, broadcast dst buffer too small (%llu %lu)\n",
3244 ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff; 2868 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3245 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff; 2869 return -EINVAL;
3246 p->idx += 7; 2870 }
3247 break; 2871 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3248 default: 2872 dev_warn(p->dev, "DMA L2L, dw, broadcast dst2 buffer too small (%llu %lu)\n",
3249 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc); 2873 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3250 return -EINVAL; 2874 return -EINVAL;
3251 } 2875 }
2876 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2877 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset & 0xfffffffc);
2878 ib[idx+3] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2879 ib[idx+4] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2880 ib[idx+5] += upper_32_bits(dst2_reloc->lobj.gpu_offset) & 0xff;
2881 ib[idx+6] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2882 p->idx += 7;
2883 break;
2884 /* Copy L2T Frame to Field */
2885 case 0x48:
2886 if (ib[idx + 2] & (1 << 31)) {
2887 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2888 return -EINVAL;
2889 }
2890 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
2891 if (r) {
2892 DRM_ERROR("bad L2T, frame to fields DMA_PACKET_COPY\n");
2893 return -EINVAL;
2894 }
2895 dst_offset = ib[idx+1];
2896 dst_offset <<= 8;
2897 dst2_offset = ib[idx+2];
2898 dst2_offset <<= 8;
2899 src_offset = ib[idx+8];
2900 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
2901 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2902 dev_warn(p->dev, "DMA L2T, frame to fields src buffer too small (%llu %lu)\n",
2903 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2904 return -EINVAL;
2905 }
2906 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2907 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2908 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2909 return -EINVAL;
2910 }
2911 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2912 dev_warn(p->dev, "DMA L2T, frame to fields buffer too small (%llu %lu)\n",
2913 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
2914 return -EINVAL;
2915 }
2916 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2917 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2918 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2919 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2920 p->idx += 10;
2921 break;
2922 /* Copy L2T/T2L, partial */
2923 case 0x49:
2924 /* L2T, T2L partial */
2925 if (p->family < CHIP_CAYMAN) {
2926 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
2927 return -EINVAL;
2928 }
2929 /* detile bit */
2930 if (ib[idx + 2 ] & (1 << 31)) {
2931 /* tiled src, linear dst */
2932 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2933
2934 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2935 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
2936 } else {
2937 /* linear src, tiled dst */
2938 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2939 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2940
2941 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2942 }
2943 p->idx += 12;
2944 break;
2945 /* Copy L2T broadcast */
2946 case 0x4b:
2947 /* L2T, broadcast */
2948 if (ib[idx + 2] & (1 << 31)) {
2949 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
2950 return -EINVAL;
2951 }
2952 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
2953 if (r) {
2954 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
2955 return -EINVAL;
2956 }
2957 dst_offset = ib[idx+1];
2958 dst_offset <<= 8;
2959 dst2_offset = ib[idx+2];
2960 dst2_offset <<= 8;
2961 src_offset = ib[idx+8];
2962 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
2963 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
2964 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
2965 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
2966 return -EINVAL;
2967 }
2968 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
2969 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
2970 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
2971 return -EINVAL;
2972 }
2973 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
2974 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
2975 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
2976 return -EINVAL;
2977 }
2978 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
2979 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
2980 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
2981 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
2982 p->idx += 10;
2983 break;
2984 /* Copy L2T/T2L (tile units) */
2985 case 0x4c:
2986 /* L2T, T2L */
2987 /* detile bit */
2988 if (ib[idx + 2] & (1 << 31)) {
2989 /* tiled src, linear dst */
2990 src_offset = ib[idx+1];
2991 src_offset <<= 8;
2992 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
2993
2994 dst_offset = ib[idx+7];
2995 dst_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
2996 ib[idx+7] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
2997 ib[idx+8] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3252 } else { 2998 } else {
3253 /* L2L, dw */ 2999 /* linear src, tiled dst */
3254 src_offset = ib[idx+2]; 3000 src_offset = ib[idx+7];
3255 src_offset |= ((u64)(ib[idx+4] & 0xff)) << 32; 3001 src_offset |= ((u64)(ib[idx+8] & 0xff)) << 32;
3002 ib[idx+7] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3003 ib[idx+8] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3004
3256 dst_offset = ib[idx+1]; 3005 dst_offset = ib[idx+1];
3257 dst_offset |= ((u64)(ib[idx+3] & 0xff)) << 32; 3006 dst_offset <<= 8;
3258 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { 3007 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3259 dev_warn(p->dev, "DMA L2L, dw src buffer too small (%llu %lu)\n",
3260 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3261 return -EINVAL;
3262 }
3263 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3264 dev_warn(p->dev, "DMA L2L, dw dst buffer too small (%llu %lu)\n",
3265 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3266 return -EINVAL;
3267 }
3268 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset & 0xfffffffc);
3269 ib[idx+2] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3270 ib[idx+3] += upper_32_bits(dst_reloc->lobj.gpu_offset) & 0xff;
3271 ib[idx+4] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3272 p->idx += 5;
3273 } 3008 }
3009 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3010 dev_warn(p->dev, "DMA L2T, T2L src buffer too small (%llu %lu)\n",
3011 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3012 return -EINVAL;
3013 }
3014 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3015 dev_warn(p->dev, "DMA L2T, T2L dst buffer too small (%llu %lu)\n",
3016 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3017 return -EINVAL;
3018 }
3019 p->idx += 9;
3020 break;
3021 /* Copy T2T, partial (tile units) */
3022 case 0x4d:
3023 /* T2T partial */
3024 if (p->family < CHIP_CAYMAN) {
3025 DRM_ERROR("L2T, T2L Partial is cayman only !\n");
3026 return -EINVAL;
3027 }
3028 ib[idx+1] += (u32)(src_reloc->lobj.gpu_offset >> 8);
3029 ib[idx+4] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3030 p->idx += 13;
3031 break;
3032 /* Copy L2T broadcast (tile units) */
3033 case 0x4f:
3034 /* L2T, broadcast */
3035 if (ib[idx + 2] & (1 << 31)) {
3036 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3037 return -EINVAL;
3038 }
3039 r = r600_dma_cs_next_reloc(p, &dst2_reloc);
3040 if (r) {
3041 DRM_ERROR("bad L2T, broadcast DMA_PACKET_COPY\n");
3042 return -EINVAL;
3043 }
3044 dst_offset = ib[idx+1];
3045 dst_offset <<= 8;
3046 dst2_offset = ib[idx+2];
3047 dst2_offset <<= 8;
3048 src_offset = ib[idx+8];
3049 src_offset |= ((u64)(ib[idx+9] & 0xff)) << 32;
3050 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {
3051 dev_warn(p->dev, "DMA L2T, broadcast src buffer too small (%llu %lu)\n",
3052 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));
3053 return -EINVAL;
3054 }
3055 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {
3056 dev_warn(p->dev, "DMA L2T, broadcast dst buffer too small (%llu %lu)\n",
3057 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));
3058 return -EINVAL;
3059 }
3060 if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {
3061 dev_warn(p->dev, "DMA L2T, broadcast dst2 buffer too small (%llu %lu)\n",
3062 dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));
3063 return -EINVAL;
3064 }
3065 ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
3066 ib[idx+2] += (u32)(dst2_reloc->lobj.gpu_offset >> 8);
3067 ib[idx+8] += (u32)(src_reloc->lobj.gpu_offset & 0xfffffffc);
3068 ib[idx+9] += upper_32_bits(src_reloc->lobj.gpu_offset) & 0xff;
3069 p->idx += 10;
3070 break;
3071 default:
3072 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib[idx+0]);
3073 return -EINVAL;
3274 } 3074 }
3275 break; 3075 break;
3276 case DMA_PACKET_CONSTANT_FILL: 3076 case DMA_PACKET_CONSTANT_FILL:
@@ -3583,19 +3383,19 @@ int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3583 3383
3584 do { 3384 do {
3585 pkt.idx = idx; 3385 pkt.idx = idx;
3586 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 3386 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
3587 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 3387 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
3588 pkt.one_reg_wr = 0; 3388 pkt.one_reg_wr = 0;
3589 switch (pkt.type) { 3389 switch (pkt.type) {
3590 case PACKET_TYPE0: 3390 case RADEON_PACKET_TYPE0:
3591 dev_err(rdev->dev, "Packet0 not allowed!\n"); 3391 dev_err(rdev->dev, "Packet0 not allowed!\n");
3592 ret = -EINVAL; 3392 ret = -EINVAL;
3593 break; 3393 break;
3594 case PACKET_TYPE2: 3394 case RADEON_PACKET_TYPE2:
3595 idx += 1; 3395 idx += 1;
3596 break; 3396 break;
3597 case PACKET_TYPE3: 3397 case RADEON_PACKET_TYPE3:
3598 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 3398 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
3599 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); 3399 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
3600 idx += pkt.count + 2; 3400 idx += pkt.count + 2;
3601 break; 3401 break;
@@ -3623,88 +3423,79 @@ int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3623int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) 3423int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3624{ 3424{
3625 u32 idx = 0; 3425 u32 idx = 0;
3626 u32 header, cmd, count, tiled, new_cmd, misc; 3426 u32 header, cmd, count, sub_cmd;
3627 3427
3628 do { 3428 do {
3629 header = ib->ptr[idx]; 3429 header = ib->ptr[idx];
3630 cmd = GET_DMA_CMD(header); 3430 cmd = GET_DMA_CMD(header);
3631 count = GET_DMA_COUNT(header); 3431 count = GET_DMA_COUNT(header);
3632 tiled = GET_DMA_T(header); 3432 sub_cmd = GET_DMA_SUB_CMD(header);
3633 new_cmd = GET_DMA_NEW(header);
3634 misc = GET_DMA_MISC(header);
3635 3433
3636 switch (cmd) { 3434 switch (cmd) {
3637 case DMA_PACKET_WRITE: 3435 case DMA_PACKET_WRITE:
3638 if (tiled) 3436 switch (sub_cmd) {
3437 /* tiled */
3438 case 8:
3639 idx += count + 7; 3439 idx += count + 7;
3640 else 3440 break;
3441 /* linear */
3442 case 0:
3641 idx += count + 3; 3443 idx += count + 3;
3444 break;
3445 default:
3446 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]);
3447 return -EINVAL;
3448 }
3642 break; 3449 break;
3643 case DMA_PACKET_COPY: 3450 case DMA_PACKET_COPY:
3644 if (tiled) { 3451 switch (sub_cmd) {
3645 if (new_cmd) { 3452 /* Copy L2L, DW aligned */
3646 switch (misc) { 3453 case 0x00:
3647 case 0: 3454 idx += 5;
3648 /* L2T, frame to fields */ 3455 break;
3649 idx += 10; 3456 /* Copy L2T/T2L */
3650 break; 3457 case 0x08:
3651 case 1: 3458 idx += 9;
3652 /* L2T, T2L partial */ 3459 break;
3653 idx += 12; 3460 /* Copy L2L, byte aligned */
3654 break; 3461 case 0x40:
3655 case 3: 3462 idx += 5;
3656 /* L2T, broadcast */ 3463 break;
3657 idx += 10; 3464 /* Copy L2L, partial */
3658 break; 3465 case 0x41:
3659 case 4: 3466 idx += 9;
3660 /* L2T, T2L */ 3467 break;
3661 idx += 9; 3468 /* Copy L2L, DW aligned, broadcast */
3662 break; 3469 case 0x44:
3663 case 5: 3470 idx += 7;
3664 /* T2T partial */ 3471 break;
3665 idx += 13; 3472 /* Copy L2T Frame to Field */
3666 break; 3473 case 0x48:
3667 case 7: 3474 idx += 10;
3668 /* L2T, broadcast */ 3475 break;
3669 idx += 10; 3476 /* Copy L2T/T2L, partial */
3670 break; 3477 case 0x49:
3671 default: 3478 idx += 12;
3672 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc); 3479 break;
3673 return -EINVAL; 3480 /* Copy L2T broadcast */
3674 } 3481 case 0x4b:
3675 } else { 3482 idx += 10;
3676 switch (misc) { 3483 break;
3677 case 0: 3484 /* Copy L2T/T2L (tile units) */
3678 idx += 9; 3485 case 0x4c:
3679 break; 3486 idx += 9;
3680 default: 3487 break;
3681 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc); 3488 /* Copy T2T, partial (tile units) */
3682 return -EINVAL; 3489 case 0x4d:
3683 } 3490 idx += 13;
3684 } 3491 break;
3685 } else { 3492 /* Copy L2T broadcast (tile units) */
3686 if (new_cmd) { 3493 case 0x4f:
3687 switch (misc) { 3494 idx += 10;
3688 case 0: 3495 break;
3689 /* L2L, byte */ 3496 default:
3690 idx += 5; 3497 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]);
3691 break; 3498 return -EINVAL;
3692 case 1:
3693 /* L2L, partial */
3694 idx += 9;
3695 break;
3696 case 4:
3697 /* L2L, dw, broadcast */
3698 idx += 7;
3699 break;
3700 default:
3701 DRM_ERROR("bad DMA_PACKET_COPY misc %u\n", misc);
3702 return -EINVAL;
3703 }
3704 } else {
3705 /* L2L, dw */
3706 idx += 5;
3707 }
3708 } 3499 }
3709 break; 3500 break;
3710 case DMA_PACKET_CONSTANT_FILL: 3501 case DMA_PACKET_CONSTANT_FILL:
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index 034f4c22e5db..f585be16e2d5 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -223,6 +223,7 @@
223#define EVERGREEN_CRTC_STATUS 0x6e8c 223#define EVERGREEN_CRTC_STATUS 0x6e8c
224# define EVERGREEN_CRTC_V_BLANK (1 << 0) 224# define EVERGREEN_CRTC_V_BLANK (1 << 0)
225#define EVERGREEN_CRTC_STATUS_POSITION 0x6e90 225#define EVERGREEN_CRTC_STATUS_POSITION 0x6e90
226#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0
226#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8 227#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
227#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 228#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
228 229
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 0bfd0e9e469b..982d25ad9af3 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -729,6 +729,18 @@
729#define WAIT_UNTIL 0x8040 729#define WAIT_UNTIL 0x8040
730 730
731#define SRBM_STATUS 0x0E50 731#define SRBM_STATUS 0x0E50
732#define RLC_RQ_PENDING (1 << 3)
733#define GRBM_RQ_PENDING (1 << 5)
734#define VMC_BUSY (1 << 8)
735#define MCB_BUSY (1 << 9)
736#define MCB_NON_DISPLAY_BUSY (1 << 10)
737#define MCC_BUSY (1 << 11)
738#define MCD_BUSY (1 << 12)
739#define SEM_BUSY (1 << 14)
740#define RLC_BUSY (1 << 15)
741#define IH_BUSY (1 << 17)
742#define SRBM_STATUS2 0x0EC4
743#define DMA_BUSY (1 << 5)
732#define SRBM_SOFT_RESET 0x0E60 744#define SRBM_SOFT_RESET 0x0E60
733#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6 745#define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
734#define SOFT_RESET_BIF (1 << 1) 746#define SOFT_RESET_BIF (1 << 1)
@@ -924,20 +936,23 @@
924#define CAYMAN_DMA1_CNTL 0xd82c 936#define CAYMAN_DMA1_CNTL 0xd82c
925 937
926/* async DMA packets */ 938/* async DMA packets */
927#define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 939#define DMA_PACKET(cmd, sub_cmd, n) ((((cmd) & 0xF) << 28) | \
928 (((t) & 0x1) << 23) | \ 940 (((sub_cmd) & 0xFF) << 20) |\
929 (((s) & 0x1) << 22) | \ 941 (((n) & 0xFFFFF) << 0))
930 (((n) & 0xFFFFF) << 0)) 942#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
943#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
944#define GET_DMA_SUB_CMD(h) (((h) & 0x0ff00000) >> 20)
945
931/* async DMA Packet types */ 946/* async DMA Packet types */
932#define DMA_PACKET_WRITE 0x2 947#define DMA_PACKET_WRITE 0x2
933#define DMA_PACKET_COPY 0x3 948#define DMA_PACKET_COPY 0x3
934#define DMA_PACKET_INDIRECT_BUFFER 0x4 949#define DMA_PACKET_INDIRECT_BUFFER 0x4
935#define DMA_PACKET_SEMAPHORE 0x5 950#define DMA_PACKET_SEMAPHORE 0x5
936#define DMA_PACKET_FENCE 0x6 951#define DMA_PACKET_FENCE 0x6
937#define DMA_PACKET_TRAP 0x7 952#define DMA_PACKET_TRAP 0x7
938#define DMA_PACKET_SRBM_WRITE 0x9 953#define DMA_PACKET_SRBM_WRITE 0x9
939#define DMA_PACKET_CONSTANT_FILL 0xd 954#define DMA_PACKET_CONSTANT_FILL 0xd
940#define DMA_PACKET_NOP 0xf 955#define DMA_PACKET_NOP 0xf
941 956
942/* PCIE link stuff */ 957/* PCIE link stuff */
943#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 958#define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
@@ -980,16 +995,7 @@
980/* 995/*
981 * PM4 996 * PM4
982 */ 997 */
983#define PACKET_TYPE0 0 998#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
984#define PACKET_TYPE1 1
985#define PACKET_TYPE2 2
986#define PACKET_TYPE3 3
987
988#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
989#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
990#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
991#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
992#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
993 (((reg) >> 2) & 0xFFFF) | \ 999 (((reg) >> 2) & 0xFFFF) | \
994 ((n) & 0x3FFF) << 16) 1000 ((n) & 0x3FFF) << 16)
995#define CP_PACKET2 0x80000000 1001#define CP_PACKET2 0x80000000
@@ -998,7 +1004,7 @@
998 1004
999#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1005#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1000 1006
1001#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1007#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1002 (((op) & 0xFF) << 8) | \ 1008 (((op) & 0xFF) << 8) | \
1003 ((n) & 0x3FFF) << 16) 1009 ((n) & 0x3FFF) << 16)
1004 1010
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 835992d8d067..7cead763be9e 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -34,6 +34,8 @@
34#include "ni_reg.h" 34#include "ni_reg.h"
35#include "cayman_blit_shaders.h" 35#include "cayman_blit_shaders.h"
36 36
37extern bool evergreen_is_display_hung(struct radeon_device *rdev);
38extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
37extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 39extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
38extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 40extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
39extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev); 41extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
@@ -1310,120 +1312,90 @@ void cayman_dma_fini(struct radeon_device *rdev)
1310 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); 1312 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
1311} 1313}
1312 1314
1313static void cayman_gpu_soft_reset_gfx(struct radeon_device *rdev) 1315static u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1314{ 1316{
1315 u32 grbm_reset = 0; 1317 u32 reset_mask = 0;
1318 u32 tmp;
1316 1319
1317 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1320 /* GRBM_STATUS */
1318 return; 1321 tmp = RREG32(GRBM_STATUS);
1322 if (tmp & (PA_BUSY | SC_BUSY |
1323 SH_BUSY | SX_BUSY |
1324 TA_BUSY | VGT_BUSY |
1325 DB_BUSY | CB_BUSY |
1326 GDS_BUSY | SPI_BUSY |
1327 IA_BUSY | IA_BUSY_NO_DMA))
1328 reset_mask |= RADEON_RESET_GFX;
1319 1329
1320 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", 1330 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1321 RREG32(GRBM_STATUS)); 1331 CP_BUSY | CP_COHERENCY_BUSY))
1322 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", 1332 reset_mask |= RADEON_RESET_CP;
1323 RREG32(GRBM_STATUS_SE0));
1324 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
1325 RREG32(GRBM_STATUS_SE1));
1326 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
1327 RREG32(SRBM_STATUS));
1328 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1329 RREG32(CP_STALLED_STAT1));
1330 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1331 RREG32(CP_STALLED_STAT2));
1332 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1333 RREG32(CP_BUSY_STAT));
1334 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1335 RREG32(CP_STAT));
1336 1333
1337 /* Disable CP parsing/prefetching */ 1334 if (tmp & GRBM_EE_BUSY)
1338 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); 1335 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1339 1336
1340 /* reset all the gfx blocks */ 1337 /* DMA_STATUS_REG 0 */
1341 grbm_reset = (SOFT_RESET_CP | 1338 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1342 SOFT_RESET_CB | 1339 if (!(tmp & DMA_IDLE))
1343 SOFT_RESET_DB | 1340 reset_mask |= RADEON_RESET_DMA;
1344 SOFT_RESET_GDS |
1345 SOFT_RESET_PA |
1346 SOFT_RESET_SC |
1347 SOFT_RESET_SPI |
1348 SOFT_RESET_SH |
1349 SOFT_RESET_SX |
1350 SOFT_RESET_TC |
1351 SOFT_RESET_TA |
1352 SOFT_RESET_VGT |
1353 SOFT_RESET_IA);
1354
1355 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1356 WREG32(GRBM_SOFT_RESET, grbm_reset);
1357 (void)RREG32(GRBM_SOFT_RESET);
1358 udelay(50);
1359 WREG32(GRBM_SOFT_RESET, 0);
1360 (void)RREG32(GRBM_SOFT_RESET);
1361
1362 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n",
1363 RREG32(GRBM_STATUS));
1364 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n",
1365 RREG32(GRBM_STATUS_SE0));
1366 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n",
1367 RREG32(GRBM_STATUS_SE1));
1368 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n",
1369 RREG32(SRBM_STATUS));
1370 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1371 RREG32(CP_STALLED_STAT1));
1372 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1373 RREG32(CP_STALLED_STAT2));
1374 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1375 RREG32(CP_BUSY_STAT));
1376 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1377 RREG32(CP_STAT));
1378 1341
1379} 1342 /* DMA_STATUS_REG 1 */
1343 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1344 if (!(tmp & DMA_IDLE))
1345 reset_mask |= RADEON_RESET_DMA1;
1380 1346
1381static void cayman_gpu_soft_reset_dma(struct radeon_device *rdev) 1347 /* SRBM_STATUS2 */
1382{ 1348 tmp = RREG32(SRBM_STATUS2);
1383 u32 tmp; 1349 if (tmp & DMA_BUSY)
1350 reset_mask |= RADEON_RESET_DMA;
1384 1351
1385 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1352 if (tmp & DMA1_BUSY)
1386 return; 1353 reset_mask |= RADEON_RESET_DMA1;
1387 1354
1388 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1355 /* SRBM_STATUS */
1389 RREG32(DMA_STATUS_REG)); 1356 tmp = RREG32(SRBM_STATUS);
1357 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1358 reset_mask |= RADEON_RESET_RLC;
1390 1359
1391 /* dma0 */ 1360 if (tmp & IH_BUSY)
1392 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 1361 reset_mask |= RADEON_RESET_IH;
1393 tmp &= ~DMA_RB_ENABLE;
1394 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1395 1362
1396 /* dma1 */ 1363 if (tmp & SEM_BUSY)
1397 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 1364 reset_mask |= RADEON_RESET_SEM;
1398 tmp &= ~DMA_RB_ENABLE;
1399 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1400 1365
1401 /* Reset dma */ 1366 if (tmp & GRBM_RQ_PENDING)
1402 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); 1367 reset_mask |= RADEON_RESET_GRBM;
1403 RREG32(SRBM_SOFT_RESET); 1368
1404 udelay(50); 1369 if (tmp & VMC_BUSY)
1405 WREG32(SRBM_SOFT_RESET, 0); 1370 reset_mask |= RADEON_RESET_VMC;
1371
1372 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1373 MCC_BUSY | MCD_BUSY))
1374 reset_mask |= RADEON_RESET_MC;
1406 1375
1407 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1376 if (evergreen_is_display_hung(rdev))
1408 RREG32(DMA_STATUS_REG)); 1377 reset_mask |= RADEON_RESET_DISPLAY;
1409 1378
1379 /* VM_L2_STATUS */
1380 tmp = RREG32(VM_L2_STATUS);
1381 if (tmp & L2_BUSY)
1382 reset_mask |= RADEON_RESET_VMC;
1383
1384 return reset_mask;
1410} 1385}
1411 1386
1412static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1387static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1413{ 1388{
1414 struct evergreen_mc_save save; 1389 struct evergreen_mc_save save;
1415 1390 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1416 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1391 u32 tmp;
1417 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
1418
1419 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1420 reset_mask &= ~RADEON_RESET_DMA;
1421 1392
1422 if (reset_mask == 0) 1393 if (reset_mask == 0)
1423 return 0; 1394 return;
1424 1395
1425 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1396 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1426 1397
1398 evergreen_print_gpu_status_regs(rdev);
1427 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", 1399 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1428 RREG32(0x14F8)); 1400 RREG32(0x14F8));
1429 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", 1401 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
@@ -1433,29 +1405,158 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1433 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1405 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1434 RREG32(0x14DC)); 1406 RREG32(0x14DC));
1435 1407
1408 /* Disable CP parsing/prefetching */
1409 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1410
1411 if (reset_mask & RADEON_RESET_DMA) {
1412 /* dma0 */
1413 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1414 tmp &= ~DMA_RB_ENABLE;
1415 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1416 }
1417
1418 if (reset_mask & RADEON_RESET_DMA1) {
1419 /* dma1 */
1420 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1421 tmp &= ~DMA_RB_ENABLE;
1422 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1423 }
1424
1425 udelay(50);
1426
1436 evergreen_mc_stop(rdev, &save); 1427 evergreen_mc_stop(rdev, &save);
1437 if (evergreen_mc_wait_for_idle(rdev)) { 1428 if (evergreen_mc_wait_for_idle(rdev)) {
1438 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1429 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1439 } 1430 }
1440 1431
1441 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 1432 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1442 cayman_gpu_soft_reset_gfx(rdev); 1433 grbm_soft_reset = SOFT_RESET_CB |
1434 SOFT_RESET_DB |
1435 SOFT_RESET_GDS |
1436 SOFT_RESET_PA |
1437 SOFT_RESET_SC |
1438 SOFT_RESET_SPI |
1439 SOFT_RESET_SH |
1440 SOFT_RESET_SX |
1441 SOFT_RESET_TC |
1442 SOFT_RESET_TA |
1443 SOFT_RESET_VGT |
1444 SOFT_RESET_IA;
1445 }
1446
1447 if (reset_mask & RADEON_RESET_CP) {
1448 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1449
1450 srbm_soft_reset |= SOFT_RESET_GRBM;
1451 }
1443 1452
1444 if (reset_mask & RADEON_RESET_DMA) 1453 if (reset_mask & RADEON_RESET_DMA)
1445 cayman_gpu_soft_reset_dma(rdev); 1454 srbm_soft_reset |= SOFT_RESET_DMA;
1455
1456 if (reset_mask & RADEON_RESET_DMA1)
1457 srbm_soft_reset |= SOFT_RESET_DMA1;
1458
1459 if (reset_mask & RADEON_RESET_DISPLAY)
1460 srbm_soft_reset |= SOFT_RESET_DC;
1461
1462 if (reset_mask & RADEON_RESET_RLC)
1463 srbm_soft_reset |= SOFT_RESET_RLC;
1464
1465 if (reset_mask & RADEON_RESET_SEM)
1466 srbm_soft_reset |= SOFT_RESET_SEM;
1467
1468 if (reset_mask & RADEON_RESET_IH)
1469 srbm_soft_reset |= SOFT_RESET_IH;
1470
1471 if (reset_mask & RADEON_RESET_GRBM)
1472 srbm_soft_reset |= SOFT_RESET_GRBM;
1473
1474 if (reset_mask & RADEON_RESET_VMC)
1475 srbm_soft_reset |= SOFT_RESET_VMC;
1476
1477 if (!(rdev->flags & RADEON_IS_IGP)) {
1478 if (reset_mask & RADEON_RESET_MC)
1479 srbm_soft_reset |= SOFT_RESET_MC;
1480 }
1481
1482 if (grbm_soft_reset) {
1483 tmp = RREG32(GRBM_SOFT_RESET);
1484 tmp |= grbm_soft_reset;
1485 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1486 WREG32(GRBM_SOFT_RESET, tmp);
1487 tmp = RREG32(GRBM_SOFT_RESET);
1488
1489 udelay(50);
1490
1491 tmp &= ~grbm_soft_reset;
1492 WREG32(GRBM_SOFT_RESET, tmp);
1493 tmp = RREG32(GRBM_SOFT_RESET);
1494 }
1495
1496 if (srbm_soft_reset) {
1497 tmp = RREG32(SRBM_SOFT_RESET);
1498 tmp |= srbm_soft_reset;
1499 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1500 WREG32(SRBM_SOFT_RESET, tmp);
1501 tmp = RREG32(SRBM_SOFT_RESET);
1502
1503 udelay(50);
1504
1505 tmp &= ~srbm_soft_reset;
1506 WREG32(SRBM_SOFT_RESET, tmp);
1507 tmp = RREG32(SRBM_SOFT_RESET);
1508 }
1446 1509
1447 /* Wait a little for things to settle down */ 1510 /* Wait a little for things to settle down */
1448 udelay(50); 1511 udelay(50);
1449 1512
1450 evergreen_mc_resume(rdev, &save); 1513 evergreen_mc_resume(rdev, &save);
1451 return 0; 1514 udelay(50);
1515
1516 evergreen_print_gpu_status_regs(rdev);
1452} 1517}
1453 1518
1454int cayman_asic_reset(struct radeon_device *rdev) 1519int cayman_asic_reset(struct radeon_device *rdev)
1455{ 1520{
1456 return cayman_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 1521 u32 reset_mask;
1457 RADEON_RESET_COMPUTE | 1522
1458 RADEON_RESET_DMA)); 1523 reset_mask = cayman_gpu_check_soft_reset(rdev);
1524
1525 if (reset_mask)
1526 r600_set_bios_scratch_engine_hung(rdev, true);
1527
1528 cayman_gpu_soft_reset(rdev, reset_mask);
1529
1530 reset_mask = cayman_gpu_check_soft_reset(rdev);
1531
1532 if (!reset_mask)
1533 r600_set_bios_scratch_engine_hung(rdev, false);
1534
1535 return 0;
1536}
1537
1538/**
1539 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1540 *
1541 * @rdev: radeon_device pointer
1542 * @ring: radeon_ring structure holding ring information
1543 *
1544 * Check if the GFX engine is locked up.
1545 * Returns true if the engine appears to be locked up, false if not.
1546 */
1547bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1548{
1549 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1550
1551 if (!(reset_mask & (RADEON_RESET_GFX |
1552 RADEON_RESET_COMPUTE |
1553 RADEON_RESET_CP))) {
1554 radeon_ring_lockup_update(ring);
1555 return false;
1556 }
1557 /* force CP activities */
1558 radeon_ring_force_activity(rdev, ring);
1559 return radeon_ring_test_lockup(rdev, ring);
1459} 1560}
1460 1561
1461/** 1562/**
@@ -1464,18 +1565,20 @@ int cayman_asic_reset(struct radeon_device *rdev)
1464 * @rdev: radeon_device pointer 1565 * @rdev: radeon_device pointer
1465 * @ring: radeon_ring structure holding ring information 1566 * @ring: radeon_ring structure holding ring information
1466 * 1567 *
1467 * Check if the async DMA engine is locked up (cayman-SI). 1568 * Check if the async DMA engine is locked up.
1468 * Returns true if the engine appears to be locked up, false if not. 1569 * Returns true if the engine appears to be locked up, false if not.
1469 */ 1570 */
1470bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1571bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1471{ 1572{
1472 u32 dma_status_reg; 1573 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1574 u32 mask;
1473 1575
1474 if (ring->idx == R600_RING_TYPE_DMA_INDEX) 1576 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
1475 dma_status_reg = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET); 1577 mask = RADEON_RESET_DMA;
1476 else 1578 else
1477 dma_status_reg = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); 1579 mask = RADEON_RESET_DMA1;
1478 if (dma_status_reg & DMA_IDLE) { 1580
1581 if (!(reset_mask & mask)) {
1479 radeon_ring_lockup_update(ring); 1582 radeon_ring_lockup_update(ring);
1480 return false; 1583 return false;
1481 } 1584 }
@@ -1843,19 +1946,21 @@ uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags)
1843 * cayman_vm_set_page - update the page tables using the CP 1946 * cayman_vm_set_page - update the page tables using the CP
1844 * 1947 *
1845 * @rdev: radeon_device pointer 1948 * @rdev: radeon_device pointer
1949 * @ib: indirect buffer to fill with commands
1846 * @pe: addr of the page entry 1950 * @pe: addr of the page entry
1847 * @addr: dst addr to write into pe 1951 * @addr: dst addr to write into pe
1848 * @count: number of page entries to update 1952 * @count: number of page entries to update
1849 * @incr: increase next addr by incr bytes 1953 * @incr: increase next addr by incr bytes
1850 * @flags: access flags 1954 * @flags: access flags
1851 * 1955 *
1852 * Update the page tables using the CP (cayman-si). 1956 * Update the page tables using the CP (cayman/TN).
1853 */ 1957 */
1854void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, 1958void cayman_vm_set_page(struct radeon_device *rdev,
1959 struct radeon_ib *ib,
1960 uint64_t pe,
1855 uint64_t addr, unsigned count, 1961 uint64_t addr, unsigned count,
1856 uint32_t incr, uint32_t flags) 1962 uint32_t incr, uint32_t flags)
1857{ 1963{
1858 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
1859 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 1964 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
1860 uint64_t value; 1965 uint64_t value;
1861 unsigned ndw; 1966 unsigned ndw;
@@ -1866,9 +1971,9 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1866 if (ndw > 0x3FFF) 1971 if (ndw > 0x3FFF)
1867 ndw = 0x3FFF; 1972 ndw = 0x3FFF;
1868 1973
1869 radeon_ring_write(ring, PACKET3(PACKET3_ME_WRITE, ndw)); 1974 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_ME_WRITE, ndw);
1870 radeon_ring_write(ring, pe); 1975 ib->ptr[ib->length_dw++] = pe;
1871 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 1976 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
1872 for (; ndw > 1; ndw -= 2, --count, pe += 8) { 1977 for (; ndw > 1; ndw -= 2, --count, pe += 8) {
1873 if (flags & RADEON_VM_PAGE_SYSTEM) { 1978 if (flags & RADEON_VM_PAGE_SYSTEM) {
1874 value = radeon_vm_map_gart(rdev, addr); 1979 value = radeon_vm_map_gart(rdev, addr);
@@ -1880,8 +1985,8 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1880 } 1985 }
1881 addr += incr; 1986 addr += incr;
1882 value |= r600_flags; 1987 value |= r600_flags;
1883 radeon_ring_write(ring, value); 1988 ib->ptr[ib->length_dw++] = value;
1884 radeon_ring_write(ring, upper_32_bits(value)); 1989 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1885 } 1990 }
1886 } 1991 }
1887 } else { 1992 } else {
@@ -1891,9 +1996,9 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1891 ndw = 0xFFFFE; 1996 ndw = 0xFFFFE;
1892 1997
1893 /* for non-physically contiguous pages (system) */ 1998 /* for non-physically contiguous pages (system) */
1894 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw)); 1999 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
1895 radeon_ring_write(ring, pe); 2000 ib->ptr[ib->length_dw++] = pe;
1896 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 2001 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
1897 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 2002 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
1898 if (flags & RADEON_VM_PAGE_SYSTEM) { 2003 if (flags & RADEON_VM_PAGE_SYSTEM) {
1899 value = radeon_vm_map_gart(rdev, addr); 2004 value = radeon_vm_map_gart(rdev, addr);
@@ -1905,10 +2010,12 @@ void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
1905 } 2010 }
1906 addr += incr; 2011 addr += incr;
1907 value |= r600_flags; 2012 value |= r600_flags;
1908 radeon_ring_write(ring, value); 2013 ib->ptr[ib->length_dw++] = value;
1909 radeon_ring_write(ring, upper_32_bits(value)); 2014 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1910 } 2015 }
1911 } 2016 }
2017 while (ib->length_dw & 0x7)
2018 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
1912 } 2019 }
1913} 2020}
1914 2021
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 48e5022ee921..079dee202a9e 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -49,6 +49,16 @@
49#define RINGID(x) (((x) & 0x3) << 0) 49#define RINGID(x) (((x) & 0x3) << 0)
50#define VMID(x) (((x) & 0x7) << 0) 50#define VMID(x) (((x) & 0x7) << 0)
51#define SRBM_STATUS 0x0E50 51#define SRBM_STATUS 0x0E50
52#define RLC_RQ_PENDING (1 << 3)
53#define GRBM_RQ_PENDING (1 << 5)
54#define VMC_BUSY (1 << 8)
55#define MCB_BUSY (1 << 9)
56#define MCB_NON_DISPLAY_BUSY (1 << 10)
57#define MCC_BUSY (1 << 11)
58#define MCD_BUSY (1 << 12)
59#define SEM_BUSY (1 << 14)
60#define RLC_BUSY (1 << 15)
61#define IH_BUSY (1 << 17)
52 62
53#define SRBM_SOFT_RESET 0x0E60 63#define SRBM_SOFT_RESET 0x0E60
54#define SOFT_RESET_BIF (1 << 1) 64#define SOFT_RESET_BIF (1 << 1)
@@ -68,6 +78,10 @@
68#define SOFT_RESET_REGBB (1 << 22) 78#define SOFT_RESET_REGBB (1 << 22)
69#define SOFT_RESET_ORB (1 << 23) 79#define SOFT_RESET_ORB (1 << 23)
70 80
81#define SRBM_STATUS2 0x0EC4
82#define DMA_BUSY (1 << 5)
83#define DMA1_BUSY (1 << 6)
84
71#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 85#define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
72#define REQUEST_TYPE(x) (((x) & 0xf) << 0) 86#define REQUEST_TYPE(x) (((x) & 0xf) << 0)
73#define RESPONSE_TYPE_MASK 0x000000F0 87#define RESPONSE_TYPE_MASK 0x000000F0
@@ -474,16 +488,7 @@
474/* 488/*
475 * PM4 489 * PM4
476 */ 490 */
477#define PACKET_TYPE0 0 491#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
478#define PACKET_TYPE1 1
479#define PACKET_TYPE2 2
480#define PACKET_TYPE3 3
481
482#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
483#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
484#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
485#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
486#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
487 (((reg) >> 2) & 0xFFFF) | \ 492 (((reg) >> 2) & 0xFFFF) | \
488 ((n) & 0x3FFF) << 16) 493 ((n) & 0x3FFF) << 16)
489#define CP_PACKET2 0x80000000 494#define CP_PACKET2 0x80000000
@@ -492,7 +497,7 @@
492 497
493#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 498#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
494 499
495#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 500#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
496 (((op) & 0xFF) << 8) | \ 501 (((op) & 0xFF) << 8) | \
497 ((n) & 0x3FFF) << 16) 502 ((n) & 0x3FFF) << 16)
498 503
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 8ff7cac222dc..9db58530be37 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1215,11 +1215,11 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1215 struct radeon_cs_reloc *reloc; 1215 struct radeon_cs_reloc *reloc;
1216 u32 value; 1216 u32 value;
1217 1217
1218 r = r100_cs_packet_next_reloc(p, &reloc); 1218 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1219 if (r) { 1219 if (r) {
1220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1221 idx, reg); 1221 idx, reg);
1222 r100_cs_dump_packet(p, pkt); 1222 radeon_cs_dump_packet(p, pkt);
1223 return r; 1223 return r;
1224 } 1224 }
1225 1225
@@ -1233,7 +1233,7 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1233 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1233 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1234 if (reg == RADEON_SRC_PITCH_OFFSET) { 1234 if (reg == RADEON_SRC_PITCH_OFFSET) {
1235 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1235 DRM_ERROR("Cannot src blit from microtiled surface\n");
1236 r100_cs_dump_packet(p, pkt); 1236 radeon_cs_dump_packet(p, pkt);
1237 return -EINVAL; 1237 return -EINVAL;
1238 } 1238 }
1239 tile_flags |= RADEON_DST_TILE_MICRO; 1239 tile_flags |= RADEON_DST_TILE_MICRO;
@@ -1263,16 +1263,16 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1263 if (c > 16) { 1263 if (c > 16) {
1264 DRM_ERROR("Only 16 vertex buffers are allowed %d\n", 1264 DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1265 pkt->opcode); 1265 pkt->opcode);
1266 r100_cs_dump_packet(p, pkt); 1266 radeon_cs_dump_packet(p, pkt);
1267 return -EINVAL; 1267 return -EINVAL;
1268 } 1268 }
1269 track->num_arrays = c; 1269 track->num_arrays = c;
1270 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1270 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1271 r = r100_cs_packet_next_reloc(p, &reloc); 1271 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1272 if (r) { 1272 if (r) {
1273 DRM_ERROR("No reloc for packet3 %d\n", 1273 DRM_ERROR("No reloc for packet3 %d\n",
1274 pkt->opcode); 1274 pkt->opcode);
1275 r100_cs_dump_packet(p, pkt); 1275 radeon_cs_dump_packet(p, pkt);
1276 return r; 1276 return r;
1277 } 1277 }
1278 idx_value = radeon_get_ib_value(p, idx); 1278 idx_value = radeon_get_ib_value(p, idx);
@@ -1281,11 +1281,11 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1281 track->arrays[i + 0].esize = idx_value >> 8; 1281 track->arrays[i + 0].esize = idx_value >> 8;
1282 track->arrays[i + 0].robj = reloc->robj; 1282 track->arrays[i + 0].robj = reloc->robj;
1283 track->arrays[i + 0].esize &= 0x7F; 1283 track->arrays[i + 0].esize &= 0x7F;
1284 r = r100_cs_packet_next_reloc(p, &reloc); 1284 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1285 if (r) { 1285 if (r) {
1286 DRM_ERROR("No reloc for packet3 %d\n", 1286 DRM_ERROR("No reloc for packet3 %d\n",
1287 pkt->opcode); 1287 pkt->opcode);
1288 r100_cs_dump_packet(p, pkt); 1288 radeon_cs_dump_packet(p, pkt);
1289 return r; 1289 return r;
1290 } 1290 }
1291 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 1291 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
@@ -1294,11 +1294,11 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1294 track->arrays[i + 1].esize &= 0x7F; 1294 track->arrays[i + 1].esize &= 0x7F;
1295 } 1295 }
1296 if (c & 1) { 1296 if (c & 1) {
1297 r = r100_cs_packet_next_reloc(p, &reloc); 1297 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1298 if (r) { 1298 if (r) {
1299 DRM_ERROR("No reloc for packet3 %d\n", 1299 DRM_ERROR("No reloc for packet3 %d\n",
1300 pkt->opcode); 1300 pkt->opcode);
1301 r100_cs_dump_packet(p, pkt); 1301 radeon_cs_dump_packet(p, pkt);
1302 return r; 1302 return r;
1303 } 1303 }
1304 idx_value = radeon_get_ib_value(p, idx); 1304 idx_value = radeon_get_ib_value(p, idx);
@@ -1355,67 +1355,6 @@ int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1355 return 0; 1355 return 0;
1356} 1356}
1357 1357
1358void r100_cs_dump_packet(struct radeon_cs_parser *p,
1359 struct radeon_cs_packet *pkt)
1360{
1361 volatile uint32_t *ib;
1362 unsigned i;
1363 unsigned idx;
1364
1365 ib = p->ib.ptr;
1366 idx = pkt->idx;
1367 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1368 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1369 }
1370}
1371
1372/**
1373 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1374 * @parser: parser structure holding parsing context.
1375 * @pkt: where to store packet informations
1376 *
1377 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1378 * if packet is bigger than remaining ib size. or if packets is unknown.
1379 **/
1380int r100_cs_packet_parse(struct radeon_cs_parser *p,
1381 struct radeon_cs_packet *pkt,
1382 unsigned idx)
1383{
1384 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1385 uint32_t header;
1386
1387 if (idx >= ib_chunk->length_dw) {
1388 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1389 idx, ib_chunk->length_dw);
1390 return -EINVAL;
1391 }
1392 header = radeon_get_ib_value(p, idx);
1393 pkt->idx = idx;
1394 pkt->type = CP_PACKET_GET_TYPE(header);
1395 pkt->count = CP_PACKET_GET_COUNT(header);
1396 switch (pkt->type) {
1397 case PACKET_TYPE0:
1398 pkt->reg = CP_PACKET0_GET_REG(header);
1399 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1400 break;
1401 case PACKET_TYPE3:
1402 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1403 break;
1404 case PACKET_TYPE2:
1405 pkt->count = -1;
1406 break;
1407 default:
1408 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1409 return -EINVAL;
1410 }
1411 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1412 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1413 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1414 return -EINVAL;
1415 }
1416 return 0;
1417}
1418
1419/** 1358/**
1420 * r100_cs_packet_next_vline() - parse userspace VLINE packet 1359 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1421 * @parser: parser structure holding parsing context. 1360 * @parser: parser structure holding parsing context.
@@ -1444,7 +1383,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1444 ib = p->ib.ptr; 1383 ib = p->ib.ptr;
1445 1384
1446 /* parse the wait until */ 1385 /* parse the wait until */
1447 r = r100_cs_packet_parse(p, &waitreloc, p->idx); 1386 r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1448 if (r) 1387 if (r)
1449 return r; 1388 return r;
1450 1389
@@ -1461,7 +1400,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1461 } 1400 }
1462 1401
1463 /* jump over the NOP */ 1402 /* jump over the NOP */
1464 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2); 1403 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1465 if (r) 1404 if (r)
1466 return r; 1405 return r;
1467 1406
@@ -1471,7 +1410,7 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1471 1410
1472 header = radeon_get_ib_value(p, h_idx); 1411 header = radeon_get_ib_value(p, h_idx);
1473 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1412 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1474 reg = CP_PACKET0_GET_REG(header); 1413 reg = R100_CP_PACKET0_GET_REG(header);
1475 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1414 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1476 if (!obj) { 1415 if (!obj) {
1477 DRM_ERROR("cannot find crtc %d\n", crtc_id); 1416 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -1506,54 +1445,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1506 return 0; 1445 return 0;
1507} 1446}
1508 1447
1509/**
1510 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1511 * @parser: parser structure holding parsing context.
1512 * @data: pointer to relocation data
1513 * @offset_start: starting offset
1514 * @offset_mask: offset mask (to align start offset on)
1515 * @reloc: reloc informations
1516 *
1517 * Check next packet is relocation packet3, do bo validation and compute
1518 * GPU offset using the provided start.
1519 **/
1520int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1521 struct radeon_cs_reloc **cs_reloc)
1522{
1523 struct radeon_cs_chunk *relocs_chunk;
1524 struct radeon_cs_packet p3reloc;
1525 unsigned idx;
1526 int r;
1527
1528 if (p->chunk_relocs_idx == -1) {
1529 DRM_ERROR("No relocation chunk !\n");
1530 return -EINVAL;
1531 }
1532 *cs_reloc = NULL;
1533 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1534 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1535 if (r) {
1536 return r;
1537 }
1538 p->idx += p3reloc.count + 2;
1539 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1540 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1541 p3reloc.idx);
1542 r100_cs_dump_packet(p, &p3reloc);
1543 return -EINVAL;
1544 }
1545 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1546 if (idx >= relocs_chunk->length_dw) {
1547 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1548 idx, relocs_chunk->length_dw);
1549 r100_cs_dump_packet(p, &p3reloc);
1550 return -EINVAL;
1551 }
1552 /* FIXME: we assume reloc size is 4 dwords */
1553 *cs_reloc = p->relocs_ptr[(idx / 4)];
1554 return 0;
1555}
1556
1557static int r100_get_vtx_size(uint32_t vtx_fmt) 1448static int r100_get_vtx_size(uint32_t vtx_fmt)
1558{ 1449{
1559 int vtx_size; 1450 int vtx_size;
@@ -1631,7 +1522,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1631 if (r) { 1522 if (r) {
1632 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1523 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1633 idx, reg); 1524 idx, reg);
1634 r100_cs_dump_packet(p, pkt); 1525 radeon_cs_dump_packet(p, pkt);
1635 return r; 1526 return r;
1636 } 1527 }
1637 break; 1528 break;
@@ -1644,11 +1535,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1644 return r; 1535 return r;
1645 break; 1536 break;
1646 case RADEON_RB3D_DEPTHOFFSET: 1537 case RADEON_RB3D_DEPTHOFFSET:
1647 r = r100_cs_packet_next_reloc(p, &reloc); 1538 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1648 if (r) { 1539 if (r) {
1649 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1540 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1650 idx, reg); 1541 idx, reg);
1651 r100_cs_dump_packet(p, pkt); 1542 radeon_cs_dump_packet(p, pkt);
1652 return r; 1543 return r;
1653 } 1544 }
1654 track->zb.robj = reloc->robj; 1545 track->zb.robj = reloc->robj;
@@ -1657,11 +1548,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1657 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1548 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1658 break; 1549 break;
1659 case RADEON_RB3D_COLOROFFSET: 1550 case RADEON_RB3D_COLOROFFSET:
1660 r = r100_cs_packet_next_reloc(p, &reloc); 1551 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1661 if (r) { 1552 if (r) {
1662 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1553 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1663 idx, reg); 1554 idx, reg);
1664 r100_cs_dump_packet(p, pkt); 1555 radeon_cs_dump_packet(p, pkt);
1665 return r; 1556 return r;
1666 } 1557 }
1667 track->cb[0].robj = reloc->robj; 1558 track->cb[0].robj = reloc->robj;
@@ -1673,11 +1564,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1673 case RADEON_PP_TXOFFSET_1: 1564 case RADEON_PP_TXOFFSET_1:
1674 case RADEON_PP_TXOFFSET_2: 1565 case RADEON_PP_TXOFFSET_2:
1675 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1566 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1676 r = r100_cs_packet_next_reloc(p, &reloc); 1567 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1677 if (r) { 1568 if (r) {
1678 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1569 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1679 idx, reg); 1570 idx, reg);
1680 r100_cs_dump_packet(p, pkt); 1571 radeon_cs_dump_packet(p, pkt);
1681 return r; 1572 return r;
1682 } 1573 }
1683 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1574 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
@@ -1700,11 +1591,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1700 case RADEON_PP_CUBIC_OFFSET_T0_3: 1591 case RADEON_PP_CUBIC_OFFSET_T0_3:
1701 case RADEON_PP_CUBIC_OFFSET_T0_4: 1592 case RADEON_PP_CUBIC_OFFSET_T0_4:
1702 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1593 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1703 r = r100_cs_packet_next_reloc(p, &reloc); 1594 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1704 if (r) { 1595 if (r) {
1705 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1596 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1706 idx, reg); 1597 idx, reg);
1707 r100_cs_dump_packet(p, pkt); 1598 radeon_cs_dump_packet(p, pkt);
1708 return r; 1599 return r;
1709 } 1600 }
1710 track->textures[0].cube_info[i].offset = idx_value; 1601 track->textures[0].cube_info[i].offset = idx_value;
@@ -1718,11 +1609,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1718 case RADEON_PP_CUBIC_OFFSET_T1_3: 1609 case RADEON_PP_CUBIC_OFFSET_T1_3:
1719 case RADEON_PP_CUBIC_OFFSET_T1_4: 1610 case RADEON_PP_CUBIC_OFFSET_T1_4:
1720 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1611 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1721 r = r100_cs_packet_next_reloc(p, &reloc); 1612 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1722 if (r) { 1613 if (r) {
1723 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1614 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1724 idx, reg); 1615 idx, reg);
1725 r100_cs_dump_packet(p, pkt); 1616 radeon_cs_dump_packet(p, pkt);
1726 return r; 1617 return r;
1727 } 1618 }
1728 track->textures[1].cube_info[i].offset = idx_value; 1619 track->textures[1].cube_info[i].offset = idx_value;
@@ -1736,11 +1627,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1736 case RADEON_PP_CUBIC_OFFSET_T2_3: 1627 case RADEON_PP_CUBIC_OFFSET_T2_3:
1737 case RADEON_PP_CUBIC_OFFSET_T2_4: 1628 case RADEON_PP_CUBIC_OFFSET_T2_4:
1738 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1629 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1739 r = r100_cs_packet_next_reloc(p, &reloc); 1630 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1740 if (r) { 1631 if (r) {
1741 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1632 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1742 idx, reg); 1633 idx, reg);
1743 r100_cs_dump_packet(p, pkt); 1634 radeon_cs_dump_packet(p, pkt);
1744 return r; 1635 return r;
1745 } 1636 }
1746 track->textures[2].cube_info[i].offset = idx_value; 1637 track->textures[2].cube_info[i].offset = idx_value;
@@ -1754,11 +1645,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1754 track->zb_dirty = true; 1645 track->zb_dirty = true;
1755 break; 1646 break;
1756 case RADEON_RB3D_COLORPITCH: 1647 case RADEON_RB3D_COLORPITCH:
1757 r = r100_cs_packet_next_reloc(p, &reloc); 1648 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1758 if (r) { 1649 if (r) {
1759 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1650 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1760 idx, reg); 1651 idx, reg);
1761 r100_cs_dump_packet(p, pkt); 1652 radeon_cs_dump_packet(p, pkt);
1762 return r; 1653 return r;
1763 } 1654 }
1764 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1655 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
@@ -1825,11 +1716,11 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1825 track->zb_dirty = true; 1716 track->zb_dirty = true;
1826 break; 1717 break;
1827 case RADEON_RB3D_ZPASS_ADDR: 1718 case RADEON_RB3D_ZPASS_ADDR:
1828 r = r100_cs_packet_next_reloc(p, &reloc); 1719 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1829 if (r) { 1720 if (r) {
1830 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1721 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1831 idx, reg); 1722 idx, reg);
1832 r100_cs_dump_packet(p, pkt); 1723 radeon_cs_dump_packet(p, pkt);
1833 return r; 1724 return r;
1834 } 1725 }
1835 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1726 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
@@ -1986,10 +1877,10 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1986 return r; 1877 return r;
1987 break; 1878 break;
1988 case PACKET3_INDX_BUFFER: 1879 case PACKET3_INDX_BUFFER:
1989 r = r100_cs_packet_next_reloc(p, &reloc); 1880 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1990 if (r) { 1881 if (r) {
1991 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1882 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1992 r100_cs_dump_packet(p, pkt); 1883 radeon_cs_dump_packet(p, pkt);
1993 return r; 1884 return r;
1994 } 1885 }
1995 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1886 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
@@ -2000,10 +1891,10 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
2000 break; 1891 break;
2001 case 0x23: 1892 case 0x23:
2002 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1893 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
2003 r = r100_cs_packet_next_reloc(p, &reloc); 1894 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
2004 if (r) { 1895 if (r) {
2005 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1896 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2006 r100_cs_dump_packet(p, pkt); 1897 radeon_cs_dump_packet(p, pkt);
2007 return r; 1898 return r;
2008 } 1899 }
2009 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1900 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
@@ -2100,37 +1991,36 @@ int r100_cs_parse(struct radeon_cs_parser *p)
2100 r100_cs_track_clear(p->rdev, track); 1991 r100_cs_track_clear(p->rdev, track);
2101 p->track = track; 1992 p->track = track;
2102 do { 1993 do {
2103 r = r100_cs_packet_parse(p, &pkt, p->idx); 1994 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2104 if (r) { 1995 if (r) {
2105 return r; 1996 return r;
2106 } 1997 }
2107 p->idx += pkt.count + 2; 1998 p->idx += pkt.count + 2;
2108 switch (pkt.type) { 1999 switch (pkt.type) {
2109 case PACKET_TYPE0: 2000 case RADEON_PACKET_TYPE0:
2110 if (p->rdev->family >= CHIP_R200) 2001 if (p->rdev->family >= CHIP_R200)
2111 r = r100_cs_parse_packet0(p, &pkt, 2002 r = r100_cs_parse_packet0(p, &pkt,
2112 p->rdev->config.r100.reg_safe_bm, 2003 p->rdev->config.r100.reg_safe_bm,
2113 p->rdev->config.r100.reg_safe_bm_size, 2004 p->rdev->config.r100.reg_safe_bm_size,
2114 &r200_packet0_check); 2005 &r200_packet0_check);
2115 else 2006 else
2116 r = r100_cs_parse_packet0(p, &pkt, 2007 r = r100_cs_parse_packet0(p, &pkt,
2117 p->rdev->config.r100.reg_safe_bm, 2008 p->rdev->config.r100.reg_safe_bm,
2118 p->rdev->config.r100.reg_safe_bm_size, 2009 p->rdev->config.r100.reg_safe_bm_size,
2119 &r100_packet0_check); 2010 &r100_packet0_check);
2120 break; 2011 break;
2121 case PACKET_TYPE2: 2012 case RADEON_PACKET_TYPE2:
2122 break; 2013 break;
2123 case PACKET_TYPE3: 2014 case RADEON_PACKET_TYPE3:
2124 r = r100_packet3_check(p, &pkt); 2015 r = r100_packet3_check(p, &pkt);
2125 break; 2016 break;
2126 default: 2017 default:
2127 DRM_ERROR("Unknown packet type %d !\n", 2018 DRM_ERROR("Unknown packet type %d !\n",
2128 pkt.type); 2019 pkt.type);
2129 return -EINVAL; 2020 return -EINVAL;
2130 } 2021 }
2131 if (r) { 2022 if (r)
2132 return r; 2023 return r;
2133 }
2134 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw); 2024 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2135 return 0; 2025 return 0;
2136} 2026}
diff --git a/drivers/gpu/drm/radeon/r100_track.h b/drivers/gpu/drm/radeon/r100_track.h
index 6a603b378adb..eb40888bdfcc 100644
--- a/drivers/gpu/drm/radeon/r100_track.h
+++ b/drivers/gpu/drm/radeon/r100_track.h
@@ -81,10 +81,6 @@ struct r100_cs_track {
81 81
82int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 82int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
83void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 83void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
84int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
85 struct radeon_cs_reloc **cs_reloc);
86void r100_cs_dump_packet(struct radeon_cs_parser *p,
87 struct radeon_cs_packet *pkt);
88 84
89int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 85int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
90 86
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h
index eab91760fae0..f0f8ee69f480 100644
--- a/drivers/gpu/drm/radeon/r100d.h
+++ b/drivers/gpu/drm/radeon/r100d.h
@@ -64,17 +64,6 @@
64 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 64 REG_SET(PACKET3_IT_OPCODE, (op)) | \
65 REG_SET(PACKET3_COUNT, (n))) 65 REG_SET(PACKET3_COUNT, (n)))
66 66
67#define PACKET_TYPE0 0
68#define PACKET_TYPE1 1
69#define PACKET_TYPE2 2
70#define PACKET_TYPE3 3
71
72#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
73#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
74#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
75#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
76#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
77
78/* Registers */ 67/* Registers */
79#define R_0000F0_RBBM_SOFT_RESET 0x0000F0 68#define R_0000F0_RBBM_SOFT_RESET 0x0000F0
80#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 69#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index 98143a5c5b73..b3807edb1936 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -162,7 +162,7 @@ int r200_packet0_check(struct radeon_cs_parser *p,
162 if (r) { 162 if (r) {
163 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 163 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
164 idx, reg); 164 idx, reg);
165 r100_cs_dump_packet(p, pkt); 165 radeon_cs_dump_packet(p, pkt);
166 return r; 166 return r;
167 } 167 }
168 break; 168 break;
@@ -175,11 +175,11 @@ int r200_packet0_check(struct radeon_cs_parser *p,
175 return r; 175 return r;
176 break; 176 break;
177 case RADEON_RB3D_DEPTHOFFSET: 177 case RADEON_RB3D_DEPTHOFFSET:
178 r = r100_cs_packet_next_reloc(p, &reloc); 178 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
179 if (r) { 179 if (r) {
180 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 180 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
181 idx, reg); 181 idx, reg);
182 r100_cs_dump_packet(p, pkt); 182 radeon_cs_dump_packet(p, pkt);
183 return r; 183 return r;
184 } 184 }
185 track->zb.robj = reloc->robj; 185 track->zb.robj = reloc->robj;
@@ -188,11 +188,11 @@ int r200_packet0_check(struct radeon_cs_parser *p,
188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
189 break; 189 break;
190 case RADEON_RB3D_COLOROFFSET: 190 case RADEON_RB3D_COLOROFFSET:
191 r = r100_cs_packet_next_reloc(p, &reloc); 191 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
192 if (r) { 192 if (r) {
193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
194 idx, reg); 194 idx, reg);
195 r100_cs_dump_packet(p, pkt); 195 radeon_cs_dump_packet(p, pkt);
196 return r; 196 return r;
197 } 197 }
198 track->cb[0].robj = reloc->robj; 198 track->cb[0].robj = reloc->robj;
@@ -207,11 +207,11 @@ int r200_packet0_check(struct radeon_cs_parser *p,
207 case R200_PP_TXOFFSET_4: 207 case R200_PP_TXOFFSET_4:
208 case R200_PP_TXOFFSET_5: 208 case R200_PP_TXOFFSET_5:
209 i = (reg - R200_PP_TXOFFSET_0) / 24; 209 i = (reg - R200_PP_TXOFFSET_0) / 24;
210 r = r100_cs_packet_next_reloc(p, &reloc); 210 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
211 if (r) { 211 if (r) {
212 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 212 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
213 idx, reg); 213 idx, reg);
214 r100_cs_dump_packet(p, pkt); 214 radeon_cs_dump_packet(p, pkt);
215 return r; 215 return r;
216 } 216 }
217 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 217 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
@@ -260,11 +260,11 @@ int r200_packet0_check(struct radeon_cs_parser *p,
260 case R200_PP_CUBIC_OFFSET_F5_5: 260 case R200_PP_CUBIC_OFFSET_F5_5:
261 i = (reg - R200_PP_TXOFFSET_0) / 24; 261 i = (reg - R200_PP_TXOFFSET_0) / 24;
262 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; 262 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
263 r = r100_cs_packet_next_reloc(p, &reloc); 263 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
264 if (r) { 264 if (r) {
265 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 265 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
266 idx, reg); 266 idx, reg);
267 r100_cs_dump_packet(p, pkt); 267 radeon_cs_dump_packet(p, pkt);
268 return r; 268 return r;
269 } 269 }
270 track->textures[i].cube_info[face - 1].offset = idx_value; 270 track->textures[i].cube_info[face - 1].offset = idx_value;
@@ -278,11 +278,11 @@ int r200_packet0_check(struct radeon_cs_parser *p,
278 track->zb_dirty = true; 278 track->zb_dirty = true;
279 break; 279 break;
280 case RADEON_RB3D_COLORPITCH: 280 case RADEON_RB3D_COLORPITCH:
281 r = r100_cs_packet_next_reloc(p, &reloc); 281 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
282 if (r) { 282 if (r) {
283 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 283 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
284 idx, reg); 284 idx, reg);
285 r100_cs_dump_packet(p, pkt); 285 radeon_cs_dump_packet(p, pkt);
286 return r; 286 return r;
287 } 287 }
288 288
@@ -355,11 +355,11 @@ int r200_packet0_check(struct radeon_cs_parser *p,
355 track->zb_dirty = true; 355 track->zb_dirty = true;
356 break; 356 break;
357 case RADEON_RB3D_ZPASS_ADDR: 357 case RADEON_RB3D_ZPASS_ADDR:
358 r = r100_cs_packet_next_reloc(p, &reloc); 358 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
359 if (r) { 359 if (r) {
360 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 360 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
361 idx, reg); 361 idx, reg);
362 r100_cs_dump_packet(p, pkt); 362 radeon_cs_dump_packet(p, pkt);
363 return r; 363 return r;
364 } 364 }
365 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 365 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index d0ba6023a1f8..c60350e6872d 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -615,7 +615,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
615 if (r) { 615 if (r) {
616 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 616 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
617 idx, reg); 617 idx, reg);
618 r100_cs_dump_packet(p, pkt); 618 radeon_cs_dump_packet(p, pkt);
619 return r; 619 return r;
620 } 620 }
621 break; 621 break;
@@ -630,11 +630,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
630 case R300_RB3D_COLOROFFSET2: 630 case R300_RB3D_COLOROFFSET2:
631 case R300_RB3D_COLOROFFSET3: 631 case R300_RB3D_COLOROFFSET3:
632 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 632 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
633 r = r100_cs_packet_next_reloc(p, &reloc); 633 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
634 if (r) { 634 if (r) {
635 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 635 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
636 idx, reg); 636 idx, reg);
637 r100_cs_dump_packet(p, pkt); 637 radeon_cs_dump_packet(p, pkt);
638 return r; 638 return r;
639 } 639 }
640 track->cb[i].robj = reloc->robj; 640 track->cb[i].robj = reloc->robj;
@@ -643,11 +643,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
643 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 643 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
644 break; 644 break;
645 case R300_ZB_DEPTHOFFSET: 645 case R300_ZB_DEPTHOFFSET:
646 r = r100_cs_packet_next_reloc(p, &reloc); 646 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
647 if (r) { 647 if (r) {
648 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 648 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
649 idx, reg); 649 idx, reg);
650 r100_cs_dump_packet(p, pkt); 650 radeon_cs_dump_packet(p, pkt);
651 return r; 651 return r;
652 } 652 }
653 track->zb.robj = reloc->robj; 653 track->zb.robj = reloc->robj;
@@ -672,11 +672,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
672 case R300_TX_OFFSET_0+56: 672 case R300_TX_OFFSET_0+56:
673 case R300_TX_OFFSET_0+60: 673 case R300_TX_OFFSET_0+60:
674 i = (reg - R300_TX_OFFSET_0) >> 2; 674 i = (reg - R300_TX_OFFSET_0) >> 2;
675 r = r100_cs_packet_next_reloc(p, &reloc); 675 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
676 if (r) { 676 if (r) {
677 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 677 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
678 idx, reg); 678 idx, reg);
679 r100_cs_dump_packet(p, pkt); 679 radeon_cs_dump_packet(p, pkt);
680 return r; 680 return r;
681 } 681 }
682 682
@@ -745,11 +745,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
745 /* RB3D_COLORPITCH2 */ 745 /* RB3D_COLORPITCH2 */
746 /* RB3D_COLORPITCH3 */ 746 /* RB3D_COLORPITCH3 */
747 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 747 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
748 r = r100_cs_packet_next_reloc(p, &reloc); 748 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
749 if (r) { 749 if (r) {
750 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 750 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
751 idx, reg); 751 idx, reg);
752 r100_cs_dump_packet(p, pkt); 752 radeon_cs_dump_packet(p, pkt);
753 return r; 753 return r;
754 } 754 }
755 755
@@ -830,11 +830,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
830 case 0x4F24: 830 case 0x4F24:
831 /* ZB_DEPTHPITCH */ 831 /* ZB_DEPTHPITCH */
832 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 832 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
833 r = r100_cs_packet_next_reloc(p, &reloc); 833 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
834 if (r) { 834 if (r) {
835 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 835 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
836 idx, reg); 836 idx, reg);
837 r100_cs_dump_packet(p, pkt); 837 radeon_cs_dump_packet(p, pkt);
838 return r; 838 return r;
839 } 839 }
840 840
@@ -1045,11 +1045,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1045 track->tex_dirty = true; 1045 track->tex_dirty = true;
1046 break; 1046 break;
1047 case R300_ZB_ZPASS_ADDR: 1047 case R300_ZB_ZPASS_ADDR:
1048 r = r100_cs_packet_next_reloc(p, &reloc); 1048 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1049 if (r) { 1049 if (r) {
1050 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1050 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1051 idx, reg); 1051 idx, reg);
1052 r100_cs_dump_packet(p, pkt); 1052 radeon_cs_dump_packet(p, pkt);
1053 return r; 1053 return r;
1054 } 1054 }
1055 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1055 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
@@ -1087,11 +1087,11 @@ static int r300_packet0_check(struct radeon_cs_parser *p,
1087 track->cb_dirty = true; 1087 track->cb_dirty = true;
1088 break; 1088 break;
1089 case R300_RB3D_AARESOLVE_OFFSET: 1089 case R300_RB3D_AARESOLVE_OFFSET:
1090 r = r100_cs_packet_next_reloc(p, &reloc); 1090 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1091 if (r) { 1091 if (r) {
1092 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1092 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1093 idx, reg); 1093 idx, reg);
1094 r100_cs_dump_packet(p, pkt); 1094 radeon_cs_dump_packet(p, pkt);
1095 return r; 1095 return r;
1096 } 1096 }
1097 track->aa.robj = reloc->robj; 1097 track->aa.robj = reloc->robj;
@@ -1156,10 +1156,10 @@ static int r300_packet3_check(struct radeon_cs_parser *p,
1156 return r; 1156 return r;
1157 break; 1157 break;
1158 case PACKET3_INDX_BUFFER: 1158 case PACKET3_INDX_BUFFER:
1159 r = r100_cs_packet_next_reloc(p, &reloc); 1159 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1160 if (r) { 1160 if (r) {
1161 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1161 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1162 r100_cs_dump_packet(p, pkt); 1162 radeon_cs_dump_packet(p, pkt);
1163 return r; 1163 return r;
1164 } 1164 }
1165 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1165 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
@@ -1257,21 +1257,21 @@ int r300_cs_parse(struct radeon_cs_parser *p)
1257 r100_cs_track_clear(p->rdev, track); 1257 r100_cs_track_clear(p->rdev, track);
1258 p->track = track; 1258 p->track = track;
1259 do { 1259 do {
1260 r = r100_cs_packet_parse(p, &pkt, p->idx); 1260 r = radeon_cs_packet_parse(p, &pkt, p->idx);
1261 if (r) { 1261 if (r) {
1262 return r; 1262 return r;
1263 } 1263 }
1264 p->idx += pkt.count + 2; 1264 p->idx += pkt.count + 2;
1265 switch (pkt.type) { 1265 switch (pkt.type) {
1266 case PACKET_TYPE0: 1266 case RADEON_PACKET_TYPE0:
1267 r = r100_cs_parse_packet0(p, &pkt, 1267 r = r100_cs_parse_packet0(p, &pkt,
1268 p->rdev->config.r300.reg_safe_bm, 1268 p->rdev->config.r300.reg_safe_bm,
1269 p->rdev->config.r300.reg_safe_bm_size, 1269 p->rdev->config.r300.reg_safe_bm_size,
1270 &r300_packet0_check); 1270 &r300_packet0_check);
1271 break; 1271 break;
1272 case PACKET_TYPE2: 1272 case RADEON_PACKET_TYPE2:
1273 break; 1273 break;
1274 case PACKET_TYPE3: 1274 case RADEON_PACKET_TYPE3:
1275 r = r300_packet3_check(p, &pkt); 1275 r = r300_packet3_check(p, &pkt);
1276 break; 1276 break;
1277 default: 1277 default:
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
index 002ab038d2ab..865e2c9980db 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
@@ -29,6 +29,8 @@
29 * 29 *
30 * Authors: 30 * Authors:
31 * Nicolai Haehnle <prefect_@gmx.net> 31 * Nicolai Haehnle <prefect_@gmx.net>
32 *
33 * ------------------------ This file is DEPRECATED! -------------------------
32 */ 34 */
33 35
34#include <drm/drmP.h> 36#include <drm/drmP.h>
diff --git a/drivers/gpu/drm/radeon/r300d.h b/drivers/gpu/drm/radeon/r300d.h
index 1f519a5ffb8c..ff229a00d273 100644
--- a/drivers/gpu/drm/radeon/r300d.h
+++ b/drivers/gpu/drm/radeon/r300d.h
@@ -65,17 +65,6 @@
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n))) 66 REG_SET(PACKET3_COUNT, (n)))
67 67
68#define PACKET_TYPE0 0
69#define PACKET_TYPE1 1
70#define PACKET_TYPE2 2
71#define PACKET_TYPE3 3
72
73#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
74#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
75#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
76#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
77#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
78
79/* Registers */ 68/* Registers */
80#define R_000148_MC_FB_LOCATION 0x000148 69#define R_000148_MC_FB_LOCATION 0x000148
81#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0) 70#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index ec576aaafb73..c0dc8d3ba0bb 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -355,6 +355,7 @@
355# define AVIVO_D1CRTC_V_BLANK (1 << 0) 355# define AVIVO_D1CRTC_V_BLANK (1 << 0)
356#define AVIVO_D1CRTC_STATUS_POSITION 0x60a0 356#define AVIVO_D1CRTC_STATUS_POSITION 0x60a0
357#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4 357#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
358#define AVIVO_D1CRTC_STATUS_HV_COUNT 0x60ac
358#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 359#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
359 360
360#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 361#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index becb03e8b32f..dbcb0752f083 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -94,6 +94,12 @@ MODULE_FIRMWARE("radeon/SUMO_me.bin");
94MODULE_FIRMWARE("radeon/SUMO2_pfp.bin"); 94MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
95MODULE_FIRMWARE("radeon/SUMO2_me.bin"); 95MODULE_FIRMWARE("radeon/SUMO2_me.bin");
96 96
97static const u32 crtc_offsets[2] =
98{
99 0,
100 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
101};
102
97int r600_debugfs_mc_info_init(struct radeon_device *rdev); 103int r600_debugfs_mc_info_init(struct radeon_device *rdev);
98 104
99/* r600,rv610,rv630,rv620,rv635,rv670 */ 105/* r600,rv610,rv630,rv620,rv635,rv670 */
@@ -1254,169 +1260,301 @@ void r600_vram_scratch_fini(struct radeon_device *rdev)
1254 radeon_bo_unref(&rdev->vram_scratch.robj); 1260 radeon_bo_unref(&rdev->vram_scratch.robj);
1255} 1261}
1256 1262
1257/* We doesn't check that the GPU really needs a reset we simply do the 1263void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung)
1258 * reset, it's up to the caller to determine if the GPU needs one. We
1259 * might add an helper function to check that.
1260 */
1261static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
1262{ 1264{
1263 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) | 1265 u32 tmp = RREG32(R600_BIOS_3_SCRATCH);
1264 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1265 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1266 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1267 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1268 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1269 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1270 S_008010_GUI_ACTIVE(1);
1271 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1272 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1273 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1274 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1275 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1276 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1277 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1278 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1279 u32 tmp;
1280 1266
1281 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1267 if (hung)
1282 return; 1268 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1269 else
1270 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1283 1271
1272 WREG32(R600_BIOS_3_SCRATCH, tmp);
1273}
1274
1275static void r600_print_gpu_status_regs(struct radeon_device *rdev)
1276{
1284 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1277 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n",
1285 RREG32(R_008010_GRBM_STATUS)); 1278 RREG32(R_008010_GRBM_STATUS));
1286 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1279 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n",
1287 RREG32(R_008014_GRBM_STATUS2)); 1280 RREG32(R_008014_GRBM_STATUS2));
1288 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1281 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n",
1289 RREG32(R_000E50_SRBM_STATUS)); 1282 RREG32(R_000E50_SRBM_STATUS));
1290 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1283 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n",
1291 RREG32(CP_STALLED_STAT1)); 1284 RREG32(CP_STALLED_STAT1));
1292 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1285 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n",
1293 RREG32(CP_STALLED_STAT2)); 1286 RREG32(CP_STALLED_STAT2));
1294 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1287 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n",
1295 RREG32(CP_BUSY_STAT)); 1288 RREG32(CP_BUSY_STAT));
1296 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", 1289 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1297 RREG32(CP_STAT)); 1290 RREG32(CP_STAT));
1298 1291 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n",
1299 /* Disable CP parsing/prefetching */ 1292 RREG32(DMA_STATUS_REG));
1300 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); 1293}
1301 1294
1302 /* Check if any of the rendering block is busy and reset it */ 1295static bool r600_is_display_hung(struct radeon_device *rdev)
1303 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) || 1296{
1304 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) { 1297 u32 crtc_hung = 0;
1305 tmp = S_008020_SOFT_RESET_CR(1) | 1298 u32 crtc_status[2];
1306 S_008020_SOFT_RESET_DB(1) | 1299 u32 i, j, tmp;
1307 S_008020_SOFT_RESET_CB(1) | 1300
1308 S_008020_SOFT_RESET_PA(1) | 1301 for (i = 0; i < rdev->num_crtc; i++) {
1309 S_008020_SOFT_RESET_SC(1) | 1302 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {
1310 S_008020_SOFT_RESET_SMX(1) | 1303 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1311 S_008020_SOFT_RESET_SPI(1) | 1304 crtc_hung |= (1 << i);
1312 S_008020_SOFT_RESET_SX(1) | 1305 }
1313 S_008020_SOFT_RESET_SH(1) |
1314 S_008020_SOFT_RESET_TC(1) |
1315 S_008020_SOFT_RESET_TA(1) |
1316 S_008020_SOFT_RESET_VC(1) |
1317 S_008020_SOFT_RESET_VGT(1);
1318 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1319 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1320 RREG32(R_008020_GRBM_SOFT_RESET);
1321 mdelay(15);
1322 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1323 } 1306 }
1324 /* Reset CP (we always reset CP) */
1325 tmp = S_008020_SOFT_RESET_CP(1);
1326 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1327 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1328 RREG32(R_008020_GRBM_SOFT_RESET);
1329 mdelay(15);
1330 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1331 1307
1332 dev_info(rdev->dev, " R_008010_GRBM_STATUS = 0x%08X\n", 1308 for (j = 0; j < 10; j++) {
1333 RREG32(R_008010_GRBM_STATUS)); 1309 for (i = 0; i < rdev->num_crtc; i++) {
1334 dev_info(rdev->dev, " R_008014_GRBM_STATUS2 = 0x%08X\n", 1310 if (crtc_hung & (1 << i)) {
1335 RREG32(R_008014_GRBM_STATUS2)); 1311 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);
1336 dev_info(rdev->dev, " R_000E50_SRBM_STATUS = 0x%08X\n", 1312 if (tmp != crtc_status[i])
1337 RREG32(R_000E50_SRBM_STATUS)); 1313 crtc_hung &= ~(1 << i);
1338 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", 1314 }
1339 RREG32(CP_STALLED_STAT1)); 1315 }
1340 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", 1316 if (crtc_hung == 0)
1341 RREG32(CP_STALLED_STAT2)); 1317 return false;
1342 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", 1318 udelay(100);
1343 RREG32(CP_BUSY_STAT)); 1319 }
1344 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n",
1345 RREG32(CP_STAT));
1346 1320
1321 return true;
1347} 1322}
1348 1323
1349static void r600_gpu_soft_reset_dma(struct radeon_device *rdev) 1324static u32 r600_gpu_check_soft_reset(struct radeon_device *rdev)
1350{ 1325{
1326 u32 reset_mask = 0;
1351 u32 tmp; 1327 u32 tmp;
1352 1328
1353 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 1329 /* GRBM_STATUS */
1354 return; 1330 tmp = RREG32(R_008010_GRBM_STATUS);
1331 if (rdev->family >= CHIP_RV770) {
1332 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1333 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1334 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1335 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1336 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1337 reset_mask |= RADEON_RESET_GFX;
1338 } else {
1339 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) |
1340 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) |
1341 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) |
1342 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) |
1343 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp))
1344 reset_mask |= RADEON_RESET_GFX;
1345 }
1355 1346
1356 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1347 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) |
1357 RREG32(DMA_STATUS_REG)); 1348 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp))
1349 reset_mask |= RADEON_RESET_CP;
1358 1350
1359 /* Disable DMA */ 1351 if (G_008010_GRBM_EE_BUSY(tmp))
1360 tmp = RREG32(DMA_RB_CNTL); 1352 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1361 tmp &= ~DMA_RB_ENABLE;
1362 WREG32(DMA_RB_CNTL, tmp);
1363 1353
1364 /* Reset dma */ 1354 /* DMA_STATUS_REG */
1365 if (rdev->family >= CHIP_RV770) 1355 tmp = RREG32(DMA_STATUS_REG);
1366 WREG32(SRBM_SOFT_RESET, RV770_SOFT_RESET_DMA); 1356 if (!(tmp & DMA_IDLE))
1367 else 1357 reset_mask |= RADEON_RESET_DMA;
1368 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
1369 RREG32(SRBM_SOFT_RESET);
1370 udelay(50);
1371 WREG32(SRBM_SOFT_RESET, 0);
1372 1358
1373 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", 1359 /* SRBM_STATUS */
1374 RREG32(DMA_STATUS_REG)); 1360 tmp = RREG32(R_000E50_SRBM_STATUS);
1361 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp))
1362 reset_mask |= RADEON_RESET_RLC;
1363
1364 if (G_000E50_IH_BUSY(tmp))
1365 reset_mask |= RADEON_RESET_IH;
1366
1367 if (G_000E50_SEM_BUSY(tmp))
1368 reset_mask |= RADEON_RESET_SEM;
1369
1370 if (G_000E50_GRBM_RQ_PENDING(tmp))
1371 reset_mask |= RADEON_RESET_GRBM;
1372
1373 if (G_000E50_VMC_BUSY(tmp))
1374 reset_mask |= RADEON_RESET_VMC;
1375
1376 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) |
1377 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) |
1378 G_000E50_MCDW_BUSY(tmp))
1379 reset_mask |= RADEON_RESET_MC;
1380
1381 if (r600_is_display_hung(rdev))
1382 reset_mask |= RADEON_RESET_DISPLAY;
1383
1384 return reset_mask;
1375} 1385}
1376 1386
1377static int r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 1387static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1378{ 1388{
1379 struct rv515_mc_save save; 1389 struct rv515_mc_save save;
1380 1390 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1381 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 1391 u32 tmp;
1382 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
1383
1384 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
1385 reset_mask &= ~RADEON_RESET_DMA;
1386 1392
1387 if (reset_mask == 0) 1393 if (reset_mask == 0)
1388 return 0; 1394 return;
1389 1395
1390 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1396 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1391 1397
1398 r600_print_gpu_status_regs(rdev);
1399
1400 /* Disable CP parsing/prefetching */
1401 if (rdev->family >= CHIP_RV770)
1402 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1));
1403 else
1404 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1405
1406 /* disable the RLC */
1407 WREG32(RLC_CNTL, 0);
1408
1409 if (reset_mask & RADEON_RESET_DMA) {
1410 /* Disable DMA */
1411 tmp = RREG32(DMA_RB_CNTL);
1412 tmp &= ~DMA_RB_ENABLE;
1413 WREG32(DMA_RB_CNTL, tmp);
1414 }
1415
1416 mdelay(50);
1417
1392 rv515_mc_stop(rdev, &save); 1418 rv515_mc_stop(rdev, &save);
1393 if (r600_mc_wait_for_idle(rdev)) { 1419 if (r600_mc_wait_for_idle(rdev)) {
1394 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 1420 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1395 } 1421 }
1396 1422
1397 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 1423 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1398 r600_gpu_soft_reset_gfx(rdev); 1424 if (rdev->family >= CHIP_RV770)
1425 grbm_soft_reset |= S_008020_SOFT_RESET_DB(1) |
1426 S_008020_SOFT_RESET_CB(1) |
1427 S_008020_SOFT_RESET_PA(1) |
1428 S_008020_SOFT_RESET_SC(1) |
1429 S_008020_SOFT_RESET_SPI(1) |
1430 S_008020_SOFT_RESET_SX(1) |
1431 S_008020_SOFT_RESET_SH(1) |
1432 S_008020_SOFT_RESET_TC(1) |
1433 S_008020_SOFT_RESET_TA(1) |
1434 S_008020_SOFT_RESET_VC(1) |
1435 S_008020_SOFT_RESET_VGT(1);
1436 else
1437 grbm_soft_reset |= S_008020_SOFT_RESET_CR(1) |
1438 S_008020_SOFT_RESET_DB(1) |
1439 S_008020_SOFT_RESET_CB(1) |
1440 S_008020_SOFT_RESET_PA(1) |
1441 S_008020_SOFT_RESET_SC(1) |
1442 S_008020_SOFT_RESET_SMX(1) |
1443 S_008020_SOFT_RESET_SPI(1) |
1444 S_008020_SOFT_RESET_SX(1) |
1445 S_008020_SOFT_RESET_SH(1) |
1446 S_008020_SOFT_RESET_TC(1) |
1447 S_008020_SOFT_RESET_TA(1) |
1448 S_008020_SOFT_RESET_VC(1) |
1449 S_008020_SOFT_RESET_VGT(1);
1450 }
1451
1452 if (reset_mask & RADEON_RESET_CP) {
1453 grbm_soft_reset |= S_008020_SOFT_RESET_CP(1) |
1454 S_008020_SOFT_RESET_VGT(1);
1455
1456 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1457 }
1458
1459 if (reset_mask & RADEON_RESET_DMA) {
1460 if (rdev->family >= CHIP_RV770)
1461 srbm_soft_reset |= RV770_SOFT_RESET_DMA;
1462 else
1463 srbm_soft_reset |= SOFT_RESET_DMA;
1464 }
1465
1466 if (reset_mask & RADEON_RESET_RLC)
1467 srbm_soft_reset |= S_000E60_SOFT_RESET_RLC(1);
1468
1469 if (reset_mask & RADEON_RESET_SEM)
1470 srbm_soft_reset |= S_000E60_SOFT_RESET_SEM(1);
1471
1472 if (reset_mask & RADEON_RESET_IH)
1473 srbm_soft_reset |= S_000E60_SOFT_RESET_IH(1);
1474
1475 if (reset_mask & RADEON_RESET_GRBM)
1476 srbm_soft_reset |= S_000E60_SOFT_RESET_GRBM(1);
1477
1478 if (!(rdev->flags & RADEON_IS_IGP)) {
1479 if (reset_mask & RADEON_RESET_MC)
1480 srbm_soft_reset |= S_000E60_SOFT_RESET_MC(1);
1481 }
1482
1483 if (reset_mask & RADEON_RESET_VMC)
1484 srbm_soft_reset |= S_000E60_SOFT_RESET_VMC(1);
1485
1486 if (grbm_soft_reset) {
1487 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1488 tmp |= grbm_soft_reset;
1489 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1490 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1491 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1492
1493 udelay(50);
1494
1495 tmp &= ~grbm_soft_reset;
1496 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1497 tmp = RREG32(R_008020_GRBM_SOFT_RESET);
1498 }
1499
1500 if (srbm_soft_reset) {
1501 tmp = RREG32(SRBM_SOFT_RESET);
1502 tmp |= srbm_soft_reset;
1503 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1504 WREG32(SRBM_SOFT_RESET, tmp);
1505 tmp = RREG32(SRBM_SOFT_RESET);
1506
1507 udelay(50);
1399 1508
1400 if (reset_mask & RADEON_RESET_DMA) 1509 tmp &= ~srbm_soft_reset;
1401 r600_gpu_soft_reset_dma(rdev); 1510 WREG32(SRBM_SOFT_RESET, tmp);
1511 tmp = RREG32(SRBM_SOFT_RESET);
1512 }
1402 1513
1403 /* Wait a little for things to settle down */ 1514 /* Wait a little for things to settle down */
1404 mdelay(1); 1515 mdelay(1);
1405 1516
1406 rv515_mc_resume(rdev, &save); 1517 rv515_mc_resume(rdev, &save);
1518 udelay(50);
1519
1520 r600_print_gpu_status_regs(rdev);
1521}
1522
1523int r600_asic_reset(struct radeon_device *rdev)
1524{
1525 u32 reset_mask;
1526
1527 reset_mask = r600_gpu_check_soft_reset(rdev);
1528
1529 if (reset_mask)
1530 r600_set_bios_scratch_engine_hung(rdev, true);
1531
1532 r600_gpu_soft_reset(rdev, reset_mask);
1533
1534 reset_mask = r600_gpu_check_soft_reset(rdev);
1535
1536 if (!reset_mask)
1537 r600_set_bios_scratch_engine_hung(rdev, false);
1538
1407 return 0; 1539 return 0;
1408} 1540}
1409 1541
1410bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1542/**
1543 * r600_gfx_is_lockup - Check if the GFX engine is locked up
1544 *
1545 * @rdev: radeon_device pointer
1546 * @ring: radeon_ring structure holding ring information
1547 *
1548 * Check if the GFX engine is locked up.
1549 * Returns true if the engine appears to be locked up, false if not.
1550 */
1551bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1411{ 1552{
1412 u32 srbm_status; 1553 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1413 u32 grbm_status; 1554
1414 u32 grbm_status2; 1555 if (!(reset_mask & (RADEON_RESET_GFX |
1415 1556 RADEON_RESET_COMPUTE |
1416 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1557 RADEON_RESET_CP))) {
1417 grbm_status = RREG32(R_008010_GRBM_STATUS);
1418 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1419 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1420 radeon_ring_lockup_update(ring); 1558 radeon_ring_lockup_update(ring);
1421 return false; 1559 return false;
1422 } 1560 }
@@ -1431,15 +1569,14 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1431 * @rdev: radeon_device pointer 1569 * @rdev: radeon_device pointer
1432 * @ring: radeon_ring structure holding ring information 1570 * @ring: radeon_ring structure holding ring information
1433 * 1571 *
1434 * Check if the async DMA engine is locked up (r6xx-evergreen). 1572 * Check if the async DMA engine is locked up.
1435 * Returns true if the engine appears to be locked up, false if not. 1573 * Returns true if the engine appears to be locked up, false if not.
1436 */ 1574 */
1437bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 1575bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1438{ 1576{
1439 u32 dma_status_reg; 1577 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1440 1578
1441 dma_status_reg = RREG32(DMA_STATUS_REG); 1579 if (!(reset_mask & RADEON_RESET_DMA)) {
1442 if (dma_status_reg & DMA_IDLE) {
1443 radeon_ring_lockup_update(ring); 1580 radeon_ring_lockup_update(ring);
1444 return false; 1581 return false;
1445 } 1582 }
@@ -1448,13 +1585,6 @@ bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1448 return radeon_ring_test_lockup(rdev, ring); 1585 return radeon_ring_test_lockup(rdev, ring);
1449} 1586}
1450 1587
1451int r600_asic_reset(struct radeon_device *rdev)
1452{
1453 return r600_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
1454 RADEON_RESET_COMPUTE |
1455 RADEON_RESET_DMA));
1456}
1457
1458u32 r6xx_remap_render_backend(struct radeon_device *rdev, 1588u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1459 u32 tiling_pipe_num, 1589 u32 tiling_pipe_num,
1460 u32 max_rb_num, 1590 u32 max_rb_num,
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index 77da1f9c0b8e..f651881eb0ae 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -22,6 +22,8 @@
22 * 22 *
23 * Authors: 23 * Authors:
24 * Alex Deucher <alexander.deucher@amd.com> 24 * Alex Deucher <alexander.deucher@amd.com>
25 *
26 * ------------------------ This file is DEPRECATED! -------------------------
25 */ 27 */
26#include <drm/drmP.h> 28#include <drm/drmP.h>
27#include <drm/radeon_drm.h> 29#include <drm/radeon_drm.h>
@@ -488,37 +490,6 @@ set_default_state(drm_radeon_private_t *dev_priv)
488 ADVANCE_RING(); 490 ADVANCE_RING();
489} 491}
490 492
491/* 23 bits of float fractional data */
492#define I2F_FRAC_BITS 23
493#define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
494
495/*
496 * Converts unsigned integer into 32-bit IEEE floating point representation.
497 * Will be exact from 0 to 2^24. Above that, we round towards zero
498 * as the fractional bits will not fit in a float. (It would be better to
499 * round towards even as the fpu does, but that is slower.)
500 */
501__pure uint32_t int2float(uint32_t x)
502{
503 uint32_t msb, exponent, fraction;
504
505 /* Zero is special */
506 if (!x) return 0;
507
508 /* Get location of the most significant bit */
509 msb = __fls(x);
510
511 /*
512 * Use a rotate instead of a shift because that works both leftwards
513 * and rightwards due to the mod(32) behaviour. This means we don't
514 * need to check to see if we are above 2^24 or not.
515 */
516 fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
517 exponent = (127 + msb) << I2F_FRAC_BITS;
518
519 return fraction + exponent;
520}
521
522static int r600_nomm_get_vb(struct drm_device *dev) 493static int r600_nomm_get_vb(struct drm_device *dev)
523{ 494{
524 drm_radeon_private_t *dev_priv = dev->dev_private; 495 drm_radeon_private_t *dev_priv = dev->dev_private;
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index e082dca6feee..9fb5780a552f 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -31,6 +31,37 @@
31#include "r600_blit_shaders.h" 31#include "r600_blit_shaders.h"
32#include "radeon_blit_common.h" 32#include "radeon_blit_common.h"
33 33
34/* 23 bits of float fractional data */
35#define I2F_FRAC_BITS 23
36#define I2F_MASK ((1 << I2F_FRAC_BITS) - 1)
37
38/*
39 * Converts unsigned integer into 32-bit IEEE floating point representation.
40 * Will be exact from 0 to 2^24. Above that, we round towards zero
41 * as the fractional bits will not fit in a float. (It would be better to
42 * round towards even as the fpu does, but that is slower.)
43 */
44__pure uint32_t int2float(uint32_t x)
45{
46 uint32_t msb, exponent, fraction;
47
48 /* Zero is special */
49 if (!x) return 0;
50
51 /* Get location of the most significant bit */
52 msb = __fls(x);
53
54 /*
55 * Use a rotate instead of a shift because that works both leftwards
56 * and rightwards due to the mod(32) behaviour. This means we don't
57 * need to check to see if we are above 2^24 or not.
58 */
59 fraction = ror32(x, (msb - I2F_FRAC_BITS) & 0x1f) & I2F_MASK;
60 exponent = (127 + msb) << I2F_FRAC_BITS;
61
62 return fraction + exponent;
63}
64
34/* emits 21 on rv770+, 23 on r600 */ 65/* emits 21 on rv770+, 23 on r600 */
35static void 66static void
36set_render_target(struct radeon_device *rdev, int format, 67set_render_target(struct radeon_device *rdev, int format,
diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index be85f75aedda..1c51c08b1fde 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -24,6 +24,8 @@
24 * Authors: 24 * Authors:
25 * Dave Airlie <airlied@redhat.com> 25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com> 26 * Alex Deucher <alexander.deucher@amd.com>
27 *
28 * ------------------------ This file is DEPRECATED! -------------------------
27 */ 29 */
28 30
29#include <linux/module.h> 31#include <linux/module.h>
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 69ec24ab8d63..931a70289033 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -31,12 +31,7 @@
31#include "r600d.h" 31#include "r600d.h"
32#include "r600_reg_safe.h" 32#include "r600_reg_safe.h"
33 33
34static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, 34static int r600_nomm;
35 struct radeon_cs_reloc **cs_reloc);
36static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p,
37 struct radeon_cs_reloc **cs_reloc);
38typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**);
39static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm;
40extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); 35extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size);
41 36
42 37
@@ -784,170 +779,29 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
784} 779}
785 780
786/** 781/**
787 * r600_cs_packet_parse() - parse cp packet and point ib index to next packet 782 * r600_cs_packet_parse_vline() - parse userspace VLINE packet
788 * @parser: parser structure holding parsing context.
789 * @pkt: where to store packet informations
790 *
791 * Assume that chunk_ib_index is properly set. Will return -EINVAL
792 * if packet is bigger than remaining ib size. or if packets is unknown.
793 **/
794static int r600_cs_packet_parse(struct radeon_cs_parser *p,
795 struct radeon_cs_packet *pkt,
796 unsigned idx)
797{
798 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
799 uint32_t header;
800
801 if (idx >= ib_chunk->length_dw) {
802 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
803 idx, ib_chunk->length_dw);
804 return -EINVAL;
805 }
806 header = radeon_get_ib_value(p, idx);
807 pkt->idx = idx;
808 pkt->type = CP_PACKET_GET_TYPE(header);
809 pkt->count = CP_PACKET_GET_COUNT(header);
810 pkt->one_reg_wr = 0;
811 switch (pkt->type) {
812 case PACKET_TYPE0:
813 pkt->reg = CP_PACKET0_GET_REG(header);
814 break;
815 case PACKET_TYPE3:
816 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
817 break;
818 case PACKET_TYPE2:
819 pkt->count = -1;
820 break;
821 default:
822 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
823 return -EINVAL;
824 }
825 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
826 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
827 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
828 return -EINVAL;
829 }
830 return 0;
831}
832
833/**
834 * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3
835 * @parser: parser structure holding parsing context.
836 * @data: pointer to relocation data
837 * @offset_start: starting offset
838 * @offset_mask: offset mask (to align start offset on)
839 * @reloc: reloc informations
840 *
841 * Check next packet is relocation packet3, do bo validation and compute
842 * GPU offset using the provided start.
843 **/
844static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p,
845 struct radeon_cs_reloc **cs_reloc)
846{
847 struct radeon_cs_chunk *relocs_chunk;
848 struct radeon_cs_packet p3reloc;
849 unsigned idx;
850 int r;
851
852 if (p->chunk_relocs_idx == -1) {
853 DRM_ERROR("No relocation chunk !\n");
854 return -EINVAL;
855 }
856 *cs_reloc = NULL;
857 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
858 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
859 if (r) {
860 return r;
861 }
862 p->idx += p3reloc.count + 2;
863 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
864 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
865 p3reloc.idx);
866 return -EINVAL;
867 }
868 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
869 if (idx >= relocs_chunk->length_dw) {
870 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
871 idx, relocs_chunk->length_dw);
872 return -EINVAL;
873 }
874 /* FIXME: we assume reloc size is 4 dwords */
875 *cs_reloc = p->relocs_ptr[(idx / 4)];
876 return 0;
877}
878
879/**
880 * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3
881 * @parser: parser structure holding parsing context. 783 * @parser: parser structure holding parsing context.
882 * @data: pointer to relocation data
883 * @offset_start: starting offset
884 * @offset_mask: offset mask (to align start offset on)
885 * @reloc: reloc informations
886 * 784 *
887 * Check next packet is relocation packet3, do bo validation and compute 785 * This is an R600-specific function for parsing VLINE packets.
888 * GPU offset using the provided start. 786 * Real work is done by r600_cs_common_vline_parse function.
889 **/ 787 * Here we just set up ASIC-specific register table and call
890static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, 788 * the common implementation function.
891 struct radeon_cs_reloc **cs_reloc) 789 */
892{ 790static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
893 struct radeon_cs_chunk *relocs_chunk;
894 struct radeon_cs_packet p3reloc;
895 unsigned idx;
896 int r;
897
898 if (p->chunk_relocs_idx == -1) {
899 DRM_ERROR("No relocation chunk !\n");
900 return -EINVAL;
901 }
902 *cs_reloc = NULL;
903 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
904 r = r600_cs_packet_parse(p, &p3reloc, p->idx);
905 if (r) {
906 return r;
907 }
908 p->idx += p3reloc.count + 2;
909 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
910 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
911 p3reloc.idx);
912 return -EINVAL;
913 }
914 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
915 if (idx >= relocs_chunk->length_dw) {
916 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
917 idx, relocs_chunk->length_dw);
918 return -EINVAL;
919 }
920 *cs_reloc = p->relocs;
921 (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32;
922 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
923 return 0;
924}
925
926/**
927 * r600_cs_packet_next_is_pkt3_nop() - test if next packet is packet3 nop for reloc
928 * @parser: parser structure holding parsing context.
929 *
930 * Check next packet is relocation packet3, do bo validation and compute
931 * GPU offset using the provided start.
932 **/
933static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
934{ 791{
935 struct radeon_cs_packet p3reloc; 792 static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END,
936 int r; 793 AVIVO_D2MODE_VLINE_START_END};
794 static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS,
795 AVIVO_D2MODE_VLINE_STATUS};
937 796
938 r = r600_cs_packet_parse(p, &p3reloc, p->idx); 797 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);
939 if (r) {
940 return 0;
941 }
942 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
943 return 0;
944 }
945 return 1;
946} 798}
947 799
948/** 800/**
949 * r600_cs_packet_next_vline() - parse userspace VLINE packet 801 * r600_cs_common_vline_parse() - common vline parser
950 * @parser: parser structure holding parsing context. 802 * @parser: parser structure holding parsing context.
803 * @vline_start_end: table of vline_start_end registers
804 * @vline_status: table of vline_status registers
951 * 805 *
952 * Userspace sends a special sequence for VLINE waits. 806 * Userspace sends a special sequence for VLINE waits.
953 * PACKET0 - VLINE_START_END + value 807 * PACKET0 - VLINE_START_END + value
@@ -957,9 +811,16 @@ static int r600_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
957 * This function parses this and relocates the VLINE START END 811 * This function parses this and relocates the VLINE START END
958 * and WAIT_REG_MEM packets to the correct crtc. 812 * and WAIT_REG_MEM packets to the correct crtc.
959 * It also detects a switched off crtc and nulls out the 813 * It also detects a switched off crtc and nulls out the
960 * wait in that case. 814 * wait in that case. This function is common for all ASICs that
815 * are R600 and newer. The parsing algorithm is the same, and only
816 * differs in which registers are used.
817 *
818 * Caller is the ASIC-specific function which passes the parser
819 * context and ASIC-specific register table
961 */ 820 */
962static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p) 821int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
822 uint32_t *vline_start_end,
823 uint32_t *vline_status)
963{ 824{
964 struct drm_mode_object *obj; 825 struct drm_mode_object *obj;
965 struct drm_crtc *crtc; 826 struct drm_crtc *crtc;
@@ -973,12 +834,12 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
973 ib = p->ib.ptr; 834 ib = p->ib.ptr;
974 835
975 /* parse the WAIT_REG_MEM */ 836 /* parse the WAIT_REG_MEM */
976 r = r600_cs_packet_parse(p, &wait_reg_mem, p->idx); 837 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);
977 if (r) 838 if (r)
978 return r; 839 return r;
979 840
980 /* check its a WAIT_REG_MEM */ 841 /* check its a WAIT_REG_MEM */
981 if (wait_reg_mem.type != PACKET_TYPE3 || 842 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 ||
982 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
983 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 844 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
984 return -EINVAL; 845 return -EINVAL;
@@ -987,7 +848,12 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
987 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1); 848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
988 /* bit 4 is reg (0) or mem (1) */ 849 /* bit 4 is reg (0) or mem (1) */
989 if (wait_reg_mem_info & 0x10) { 850 if (wait_reg_mem_info & 0x10) {
990 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n"); 851 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");
852 return -EINVAL;
853 }
854 /* bit 8 is me (0) or pfp (1) */
855 if (wait_reg_mem_info & 0x100) {
856 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");
991 return -EINVAL; 857 return -EINVAL;
992 } 858 }
993 /* waiting for value to be equal */ 859 /* waiting for value to be equal */
@@ -995,18 +861,18 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
995 DRM_ERROR("vline WAIT_REG_MEM function not equal\n"); 861 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
996 return -EINVAL; 862 return -EINVAL;
997 } 863 }
998 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != AVIVO_D1MODE_VLINE_STATUS) { 864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {
999 DRM_ERROR("vline WAIT_REG_MEM bad reg\n"); 865 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1000 return -EINVAL; 866 return -EINVAL;
1001 } 867 }
1002 868
1003 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != AVIVO_D1MODE_VLINE_STAT) { 869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {
1004 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n"); 870 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1005 return -EINVAL; 871 return -EINVAL;
1006 } 872 }
1007 873
1008 /* jump over the NOP */ 874 /* jump over the NOP */
1009 r = r600_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2); 875 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1010 if (r) 876 if (r)
1011 return r; 877 return r;
1012 878
@@ -1016,7 +882,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
1016 882
1017 header = radeon_get_ib_value(p, h_idx); 883 header = radeon_get_ib_value(p, h_idx);
1018 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 884 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1019 reg = CP_PACKET0_GET_REG(header); 885 reg = R600_CP_PACKET0_GET_REG(header);
1020 886
1021 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 887 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1022 if (!obj) { 888 if (!obj) {
@@ -1028,7 +894,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
1028 crtc_id = radeon_crtc->crtc_id; 894 crtc_id = radeon_crtc->crtc_id;
1029 895
1030 if (!crtc->enabled) { 896 if (!crtc->enabled) {
1031 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */ 897 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1032 ib[h_idx + 2] = PACKET2(0); 898 ib[h_idx + 2] = PACKET2(0);
1033 ib[h_idx + 3] = PACKET2(0); 899 ib[h_idx + 3] = PACKET2(0);
1034 ib[h_idx + 4] = PACKET2(0); 900 ib[h_idx + 4] = PACKET2(0);
@@ -1036,20 +902,15 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
1036 ib[h_idx + 6] = PACKET2(0); 902 ib[h_idx + 6] = PACKET2(0);
1037 ib[h_idx + 7] = PACKET2(0); 903 ib[h_idx + 7] = PACKET2(0);
1038 ib[h_idx + 8] = PACKET2(0); 904 ib[h_idx + 8] = PACKET2(0);
1039 } else if (crtc_id == 1) { 905 } else if (reg == vline_start_end[0]) {
1040 switch (reg) { 906 header &= ~R600_CP_PACKET0_REG_MASK;
1041 case AVIVO_D1MODE_VLINE_START_END: 907 header |= vline_start_end[crtc_id] >> 2;
1042 header &= ~R600_CP_PACKET0_REG_MASK;
1043 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1044 break;
1045 default:
1046 DRM_ERROR("unknown crtc reloc\n");
1047 return -EINVAL;
1048 }
1049 ib[h_idx] = header; 908 ib[h_idx] = header;
1050 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2; 909 ib[h_idx + 4] = vline_status[crtc_id] >> 2;
910 } else {
911 DRM_ERROR("unknown crtc reloc\n");
912 return -EINVAL;
1051 } 913 }
1052
1053 return 0; 914 return 0;
1054} 915}
1055 916
@@ -1155,8 +1016,8 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1155 break; 1016 break;
1156 case R_028010_DB_DEPTH_INFO: 1017 case R_028010_DB_DEPTH_INFO:
1157 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1018 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1158 r600_cs_packet_next_is_pkt3_nop(p)) { 1019 radeon_cs_packet_next_is_pkt3_nop(p)) {
1159 r = r600_cs_packet_next_reloc(p, &reloc); 1020 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1160 if (r) { 1021 if (r) {
1161 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1022 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1162 "0x%04X\n", reg); 1023 "0x%04X\n", reg);
@@ -1198,7 +1059,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1198 case VGT_STRMOUT_BUFFER_BASE_1: 1059 case VGT_STRMOUT_BUFFER_BASE_1:
1199 case VGT_STRMOUT_BUFFER_BASE_2: 1060 case VGT_STRMOUT_BUFFER_BASE_2:
1200 case VGT_STRMOUT_BUFFER_BASE_3: 1061 case VGT_STRMOUT_BUFFER_BASE_3:
1201 r = r600_cs_packet_next_reloc(p, &reloc); 1062 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1202 if (r) { 1063 if (r) {
1203 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1064 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1204 "0x%04X\n", reg); 1065 "0x%04X\n", reg);
@@ -1221,7 +1082,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1221 track->streamout_dirty = true; 1082 track->streamout_dirty = true;
1222 break; 1083 break;
1223 case CP_COHER_BASE: 1084 case CP_COHER_BASE:
1224 r = r600_cs_packet_next_reloc(p, &reloc); 1085 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1225 if (r) { 1086 if (r) {
1226 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1087 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1227 "0x%04X\n", reg); 1088 "0x%04X\n", reg);
@@ -1256,8 +1117,8 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1256 case R_0280B8_CB_COLOR6_INFO: 1117 case R_0280B8_CB_COLOR6_INFO:
1257 case R_0280BC_CB_COLOR7_INFO: 1118 case R_0280BC_CB_COLOR7_INFO:
1258 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1119 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&
1259 r600_cs_packet_next_is_pkt3_nop(p)) { 1120 radeon_cs_packet_next_is_pkt3_nop(p)) {
1260 r = r600_cs_packet_next_reloc(p, &reloc); 1121 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1261 if (r) { 1122 if (r) {
1262 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1123 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1263 return -EINVAL; 1124 return -EINVAL;
@@ -1320,7 +1181,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1320 case R_0280F8_CB_COLOR6_FRAG: 1181 case R_0280F8_CB_COLOR6_FRAG:
1321 case R_0280FC_CB_COLOR7_FRAG: 1182 case R_0280FC_CB_COLOR7_FRAG:
1322 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4; 1183 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;
1323 if (!r600_cs_packet_next_is_pkt3_nop(p)) { 1184 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
1324 if (!track->cb_color_base_last[tmp]) { 1185 if (!track->cb_color_base_last[tmp]) {
1325 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1186 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1326 return -EINVAL; 1187 return -EINVAL;
@@ -1329,7 +1190,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1329 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; 1190 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1330 ib[idx] = track->cb_color_base_last[tmp]; 1191 ib[idx] = track->cb_color_base_last[tmp];
1331 } else { 1192 } else {
1332 r = r600_cs_packet_next_reloc(p, &reloc); 1193 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1333 if (r) { 1194 if (r) {
1334 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1195 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1335 return -EINVAL; 1196 return -EINVAL;
@@ -1351,7 +1212,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1351 case R_0280D8_CB_COLOR6_TILE: 1212 case R_0280D8_CB_COLOR6_TILE:
1352 case R_0280DC_CB_COLOR7_TILE: 1213 case R_0280DC_CB_COLOR7_TILE:
1353 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4; 1214 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;
1354 if (!r600_cs_packet_next_is_pkt3_nop(p)) { 1215 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {
1355 if (!track->cb_color_base_last[tmp]) { 1216 if (!track->cb_color_base_last[tmp]) {
1356 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1217 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1357 return -EINVAL; 1218 return -EINVAL;
@@ -1360,7 +1221,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1360 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; 1221 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1361 ib[idx] = track->cb_color_base_last[tmp]; 1222 ib[idx] = track->cb_color_base_last[tmp];
1362 } else { 1223 } else {
1363 r = r600_cs_packet_next_reloc(p, &reloc); 1224 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1364 if (r) { 1225 if (r) {
1365 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1226 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1366 return -EINVAL; 1227 return -EINVAL;
@@ -1395,7 +1256,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1395 case CB_COLOR5_BASE: 1256 case CB_COLOR5_BASE:
1396 case CB_COLOR6_BASE: 1257 case CB_COLOR6_BASE:
1397 case CB_COLOR7_BASE: 1258 case CB_COLOR7_BASE:
1398 r = r600_cs_packet_next_reloc(p, &reloc); 1259 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1399 if (r) { 1260 if (r) {
1400 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1261 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1401 "0x%04X\n", reg); 1262 "0x%04X\n", reg);
@@ -1410,7 +1271,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1410 track->cb_dirty = true; 1271 track->cb_dirty = true;
1411 break; 1272 break;
1412 case DB_DEPTH_BASE: 1273 case DB_DEPTH_BASE:
1413 r = r600_cs_packet_next_reloc(p, &reloc); 1274 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1414 if (r) { 1275 if (r) {
1415 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1276 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1416 "0x%04X\n", reg); 1277 "0x%04X\n", reg);
@@ -1423,7 +1284,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1423 track->db_dirty = true; 1284 track->db_dirty = true;
1424 break; 1285 break;
1425 case DB_HTILE_DATA_BASE: 1286 case DB_HTILE_DATA_BASE:
1426 r = r600_cs_packet_next_reloc(p, &reloc); 1287 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1427 if (r) { 1288 if (r) {
1428 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1289 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1429 "0x%04X\n", reg); 1290 "0x%04X\n", reg);
@@ -1493,7 +1354,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1493 case SQ_ALU_CONST_CACHE_VS_13: 1354 case SQ_ALU_CONST_CACHE_VS_13:
1494 case SQ_ALU_CONST_CACHE_VS_14: 1355 case SQ_ALU_CONST_CACHE_VS_14:
1495 case SQ_ALU_CONST_CACHE_VS_15: 1356 case SQ_ALU_CONST_CACHE_VS_15:
1496 r = r600_cs_packet_next_reloc(p, &reloc); 1357 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1497 if (r) { 1358 if (r) {
1498 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1359 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1499 "0x%04X\n", reg); 1360 "0x%04X\n", reg);
@@ -1502,7 +1363,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1502 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1363 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1503 break; 1364 break;
1504 case SX_MEMORY_EXPORT_BASE: 1365 case SX_MEMORY_EXPORT_BASE:
1505 r = r600_cs_packet_next_reloc(p, &reloc); 1366 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1506 if (r) { 1367 if (r) {
1507 dev_warn(p->dev, "bad SET_CONFIG_REG " 1368 dev_warn(p->dev, "bad SET_CONFIG_REG "
1508 "0x%04X\n", reg); 1369 "0x%04X\n", reg);
@@ -1788,7 +1649,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1788 return -EINVAL; 1649 return -EINVAL;
1789 } 1650 }
1790 1651
1791 r = r600_cs_packet_next_reloc(p, &reloc); 1652 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1792 if (r) { 1653 if (r) {
1793 DRM_ERROR("bad SET PREDICATION\n"); 1654 DRM_ERROR("bad SET PREDICATION\n");
1794 return -EINVAL; 1655 return -EINVAL;
@@ -1829,7 +1690,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1829 DRM_ERROR("bad DRAW_INDEX\n"); 1690 DRM_ERROR("bad DRAW_INDEX\n");
1830 return -EINVAL; 1691 return -EINVAL;
1831 } 1692 }
1832 r = r600_cs_packet_next_reloc(p, &reloc); 1693 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1833 if (r) { 1694 if (r) {
1834 DRM_ERROR("bad DRAW_INDEX\n"); 1695 DRM_ERROR("bad DRAW_INDEX\n");
1835 return -EINVAL; 1696 return -EINVAL;
@@ -1881,7 +1742,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1881 if (idx_value & 0x10) { 1742 if (idx_value & 0x10) {
1882 uint64_t offset; 1743 uint64_t offset;
1883 1744
1884 r = r600_cs_packet_next_reloc(p, &reloc); 1745 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1885 if (r) { 1746 if (r) {
1886 DRM_ERROR("bad WAIT_REG_MEM\n"); 1747 DRM_ERROR("bad WAIT_REG_MEM\n");
1887 return -EINVAL; 1748 return -EINVAL;
@@ -1893,6 +1754,9 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1893 1754
1894 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); 1755 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);
1895 ib[idx+2] = upper_32_bits(offset) & 0xff; 1756 ib[idx+2] = upper_32_bits(offset) & 0xff;
1757 } else if (idx_value & 0x100) {
1758 DRM_ERROR("cannot use PFP on REG wait\n");
1759 return -EINVAL;
1896 } 1760 }
1897 break; 1761 break;
1898 case PACKET3_CP_DMA: 1762 case PACKET3_CP_DMA:
@@ -1915,7 +1779,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1915 return -EINVAL; 1779 return -EINVAL;
1916 } 1780 }
1917 /* src address space is memory */ 1781 /* src address space is memory */
1918 r = r600_cs_packet_next_reloc(p, &reloc); 1782 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1919 if (r) { 1783 if (r) {
1920 DRM_ERROR("bad CP DMA SRC\n"); 1784 DRM_ERROR("bad CP DMA SRC\n");
1921 return -EINVAL; 1785 return -EINVAL;
@@ -1945,7 +1809,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1945 DRM_ERROR("CP DMA DAIC only supported for registers\n"); 1809 DRM_ERROR("CP DMA DAIC only supported for registers\n");
1946 return -EINVAL; 1810 return -EINVAL;
1947 } 1811 }
1948 r = r600_cs_packet_next_reloc(p, &reloc); 1812 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1949 if (r) { 1813 if (r) {
1950 DRM_ERROR("bad CP DMA DST\n"); 1814 DRM_ERROR("bad CP DMA DST\n");
1951 return -EINVAL; 1815 return -EINVAL;
@@ -1975,7 +1839,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1975 /* 0xffffffff/0x0 is flush all cache flag */ 1839 /* 0xffffffff/0x0 is flush all cache flag */
1976 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 1840 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
1977 radeon_get_ib_value(p, idx + 2) != 0) { 1841 radeon_get_ib_value(p, idx + 2) != 0) {
1978 r = r600_cs_packet_next_reloc(p, &reloc); 1842 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1979 if (r) { 1843 if (r) {
1980 DRM_ERROR("bad SURFACE_SYNC\n"); 1844 DRM_ERROR("bad SURFACE_SYNC\n");
1981 return -EINVAL; 1845 return -EINVAL;
@@ -1991,7 +1855,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1991 if (pkt->count) { 1855 if (pkt->count) {
1992 uint64_t offset; 1856 uint64_t offset;
1993 1857
1994 r = r600_cs_packet_next_reloc(p, &reloc); 1858 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
1995 if (r) { 1859 if (r) {
1996 DRM_ERROR("bad EVENT_WRITE\n"); 1860 DRM_ERROR("bad EVENT_WRITE\n");
1997 return -EINVAL; 1861 return -EINVAL;
@@ -2012,7 +1876,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2012 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 1876 DRM_ERROR("bad EVENT_WRITE_EOP\n");
2013 return -EINVAL; 1877 return -EINVAL;
2014 } 1878 }
2015 r = r600_cs_packet_next_reloc(p, &reloc); 1879 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2016 if (r) { 1880 if (r) {
2017 DRM_ERROR("bad EVENT_WRITE\n"); 1881 DRM_ERROR("bad EVENT_WRITE\n");
2018 return -EINVAL; 1882 return -EINVAL;
@@ -2078,7 +1942,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2078 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 1942 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {
2079 case SQ_TEX_VTX_VALID_TEXTURE: 1943 case SQ_TEX_VTX_VALID_TEXTURE:
2080 /* tex base */ 1944 /* tex base */
2081 r = r600_cs_packet_next_reloc(p, &reloc); 1945 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2082 if (r) { 1946 if (r) {
2083 DRM_ERROR("bad SET_RESOURCE\n"); 1947 DRM_ERROR("bad SET_RESOURCE\n");
2084 return -EINVAL; 1948 return -EINVAL;
@@ -2092,7 +1956,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2092 } 1956 }
2093 texture = reloc->robj; 1957 texture = reloc->robj;
2094 /* tex mip base */ 1958 /* tex mip base */
2095 r = r600_cs_packet_next_reloc(p, &reloc); 1959 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2096 if (r) { 1960 if (r) {
2097 DRM_ERROR("bad SET_RESOURCE\n"); 1961 DRM_ERROR("bad SET_RESOURCE\n");
2098 return -EINVAL; 1962 return -EINVAL;
@@ -2113,7 +1977,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2113 { 1977 {
2114 uint64_t offset64; 1978 uint64_t offset64;
2115 /* vtx base */ 1979 /* vtx base */
2116 r = r600_cs_packet_next_reloc(p, &reloc); 1980 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2117 if (r) { 1981 if (r) {
2118 DRM_ERROR("bad SET_RESOURCE\n"); 1982 DRM_ERROR("bad SET_RESOURCE\n");
2119 return -EINVAL; 1983 return -EINVAL;
@@ -2214,7 +2078,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2214 { 2078 {
2215 u64 offset; 2079 u64 offset;
2216 2080
2217 r = r600_cs_packet_next_reloc(p, &reloc); 2081 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2218 if (r) { 2082 if (r) {
2219 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n"); 2083 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");
2220 return -EINVAL; 2084 return -EINVAL;
@@ -2258,7 +2122,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2258 /* Updating memory at DST_ADDRESS. */ 2122 /* Updating memory at DST_ADDRESS. */
2259 if (idx_value & 0x1) { 2123 if (idx_value & 0x1) {
2260 u64 offset; 2124 u64 offset;
2261 r = r600_cs_packet_next_reloc(p, &reloc); 2125 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2262 if (r) { 2126 if (r) {
2263 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2127 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2264 return -EINVAL; 2128 return -EINVAL;
@@ -2277,7 +2141,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2277 /* Reading data from SRC_ADDRESS. */ 2141 /* Reading data from SRC_ADDRESS. */
2278 if (((idx_value >> 1) & 0x3) == 2) { 2142 if (((idx_value >> 1) & 0x3) == 2) {
2279 u64 offset; 2143 u64 offset;
2280 r = r600_cs_packet_next_reloc(p, &reloc); 2144 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2281 if (r) { 2145 if (r) {
2282 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2146 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2283 return -EINVAL; 2147 return -EINVAL;
@@ -2302,7 +2166,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2302 DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2166 DRM_ERROR("bad MEM_WRITE (invalid count)\n");
2303 return -EINVAL; 2167 return -EINVAL;
2304 } 2168 }
2305 r = r600_cs_packet_next_reloc(p, &reloc); 2169 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2306 if (r) { 2170 if (r) {
2307 DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2171 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");
2308 return -EINVAL; 2172 return -EINVAL;
@@ -2331,7 +2195,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2331 if (idx_value & 0x1) { 2195 if (idx_value & 0x1) {
2332 u64 offset; 2196 u64 offset;
2333 /* SRC is memory. */ 2197 /* SRC is memory. */
2334 r = r600_cs_packet_next_reloc(p, &reloc); 2198 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2335 if (r) { 2199 if (r) {
2336 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2200 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2337 return -EINVAL; 2201 return -EINVAL;
@@ -2355,7 +2219,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
2355 if (idx_value & 0x2) { 2219 if (idx_value & 0x2) {
2356 u64 offset; 2220 u64 offset;
2357 /* DST is memory. */ 2221 /* DST is memory. */
2358 r = r600_cs_packet_next_reloc(p, &reloc); 2222 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);
2359 if (r) { 2223 if (r) {
2360 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2224 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2361 return -EINVAL; 2225 return -EINVAL;
@@ -2410,7 +2274,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
2410 p->track = track; 2274 p->track = track;
2411 } 2275 }
2412 do { 2276 do {
2413 r = r600_cs_packet_parse(p, &pkt, p->idx); 2277 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2414 if (r) { 2278 if (r) {
2415 kfree(p->track); 2279 kfree(p->track);
2416 p->track = NULL; 2280 p->track = NULL;
@@ -2418,12 +2282,12 @@ int r600_cs_parse(struct radeon_cs_parser *p)
2418 } 2282 }
2419 p->idx += pkt.count + 2; 2283 p->idx += pkt.count + 2;
2420 switch (pkt.type) { 2284 switch (pkt.type) {
2421 case PACKET_TYPE0: 2285 case RADEON_PACKET_TYPE0:
2422 r = r600_cs_parse_packet0(p, &pkt); 2286 r = r600_cs_parse_packet0(p, &pkt);
2423 break; 2287 break;
2424 case PACKET_TYPE2: 2288 case RADEON_PACKET_TYPE2:
2425 break; 2289 break;
2426 case PACKET_TYPE3: 2290 case RADEON_PACKET_TYPE3:
2427 r = r600_packet3_check(p, &pkt); 2291 r = r600_packet3_check(p, &pkt);
2428 break; 2292 break;
2429 default: 2293 default:
@@ -2449,17 +2313,7 @@ int r600_cs_parse(struct radeon_cs_parser *p)
2449 return 0; 2313 return 0;
2450} 2314}
2451 2315
2452static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p) 2316#ifdef CONFIG_DRM_RADEON_UMS
2453{
2454 if (p->chunk_relocs_idx == -1) {
2455 return 0;
2456 }
2457 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
2458 if (p->relocs == NULL) {
2459 return -ENOMEM;
2460 }
2461 return 0;
2462}
2463 2317
2464/** 2318/**
2465 * cs_parser_fini() - clean parser states 2319 * cs_parser_fini() - clean parser states
@@ -2485,6 +2339,18 @@ static void r600_cs_parser_fini(struct radeon_cs_parser *parser, int error)
2485 kfree(parser->chunks_array); 2339 kfree(parser->chunks_array);
2486} 2340}
2487 2341
2342static int r600_cs_parser_relocs_legacy(struct radeon_cs_parser *p)
2343{
2344 if (p->chunk_relocs_idx == -1) {
2345 return 0;
2346 }
2347 p->relocs = kzalloc(sizeof(struct radeon_cs_reloc), GFP_KERNEL);
2348 if (p->relocs == NULL) {
2349 return -ENOMEM;
2350 }
2351 return 0;
2352}
2353
2488int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp, 2354int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2489 unsigned family, u32 *ib, int *l) 2355 unsigned family, u32 *ib, int *l)
2490{ 2356{
@@ -2543,9 +2409,11 @@ int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
2543 2409
2544void r600_cs_legacy_init(void) 2410void r600_cs_legacy_init(void)
2545{ 2411{
2546 r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm; 2412 r600_nomm = 1;
2547} 2413}
2548 2414
2415#endif
2416
2549/* 2417/*
2550 * DMA 2418 * DMA
2551 */ 2419 */
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 4a53402b1852..a42ba11a3bed 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -182,6 +182,8 @@
182#define CP_COHER_BASE 0x85F8 182#define CP_COHER_BASE 0x85F8
183#define CP_DEBUG 0xC1FC 183#define CP_DEBUG 0xC1FC
184#define R_0086D8_CP_ME_CNTL 0x86D8 184#define R_0086D8_CP_ME_CNTL 0x86D8
185#define S_0086D8_CP_PFP_HALT(x) (((x) & 1)<<26)
186#define C_0086D8_CP_PFP_HALT(x) ((x) & 0xFBFFFFFF)
185#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 187#define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28)
186#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 188#define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF)
187#define CP_ME_RAM_DATA 0xC160 189#define CP_ME_RAM_DATA 0xC160
@@ -1143,19 +1145,10 @@
1143/* 1145/*
1144 * PM4 1146 * PM4
1145 */ 1147 */
1146#define PACKET_TYPE0 0 1148#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
1147#define PACKET_TYPE1 1
1148#define PACKET_TYPE2 2
1149#define PACKET_TYPE3 3
1150
1151#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1152#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1153#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1154#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1155#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1156 (((reg) >> 2) & 0xFFFF) | \ 1149 (((reg) >> 2) & 0xFFFF) | \
1157 ((n) & 0x3FFF) << 16) 1150 ((n) & 0x3FFF) << 16)
1158#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1151#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
1159 (((op) & 0xFF) << 8) | \ 1152 (((op) & 0xFF) << 8) | \
1160 ((n) & 0x3FFF) << 16) 1153 ((n) & 0x3FFF) << 16)
1161 1154
@@ -1328,6 +1321,7 @@
1328#define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1321#define G_008010_VC_BUSY(x) (((x) >> 11) & 1)
1329#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1322#define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1)
1330#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1323#define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1)
1324#define G_008010_TA_BUSY(x) (((x) >> 14) & 1)
1331#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1325#define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1)
1332#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1326#define G_008010_VGT_BUSY(x) (((x) >> 17) & 1)
1333#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1327#define G_008010_TA03_BUSY(x) (((x) >> 18) & 1)
@@ -1395,6 +1389,7 @@
1395#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1389#define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1)
1396#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1390#define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1)
1397#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1391#define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1)
1392#define G_000E50_IH_BUSY(x) (((x) >> 17) & 1)
1398#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1393#define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1)
1399#define R_000E60_SRBM_SOFT_RESET 0x0E60 1394#define R_000E60_SRBM_SOFT_RESET 0x0E60
1400#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1395#define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1)
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a08f657329a0..59bfbd3868c9 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -136,6 +136,15 @@ extern int radeon_lockup_timeout;
136#define RADEON_RESET_GFX (1 << 0) 136#define RADEON_RESET_GFX (1 << 0)
137#define RADEON_RESET_COMPUTE (1 << 1) 137#define RADEON_RESET_COMPUTE (1 << 1)
138#define RADEON_RESET_DMA (1 << 2) 138#define RADEON_RESET_DMA (1 << 2)
139#define RADEON_RESET_CP (1 << 3)
140#define RADEON_RESET_GRBM (1 << 4)
141#define RADEON_RESET_DMA1 (1 << 5)
142#define RADEON_RESET_RLC (1 << 6)
143#define RADEON_RESET_SEM (1 << 7)
144#define RADEON_RESET_IH (1 << 8)
145#define RADEON_RESET_VMC (1 << 9)
146#define RADEON_RESET_MC (1 << 10)
147#define RADEON_RESET_DISPLAY (1 << 11)
139 148
140/* 149/*
141 * Errata workarounds. 150 * Errata workarounds.
@@ -771,6 +780,7 @@ int radeon_ib_get(struct radeon_device *rdev, int ring,
771 struct radeon_ib *ib, struct radeon_vm *vm, 780 struct radeon_ib *ib, struct radeon_vm *vm,
772 unsigned size); 781 unsigned size);
773void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); 782void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib);
783void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence);
774int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, 784int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
775 struct radeon_ib *const_ib); 785 struct radeon_ib *const_ib);
776int radeon_ib_pool_init(struct radeon_device *rdev); 786int radeon_ib_pool_init(struct radeon_device *rdev);
@@ -1179,7 +1189,9 @@ struct radeon_asic {
1179 void (*fini)(struct radeon_device *rdev); 1189 void (*fini)(struct radeon_device *rdev);
1180 1190
1181 u32 pt_ring_index; 1191 u32 pt_ring_index;
1182 void (*set_page)(struct radeon_device *rdev, uint64_t pe, 1192 void (*set_page)(struct radeon_device *rdev,
1193 struct radeon_ib *ib,
1194 uint64_t pe,
1183 uint64_t addr, unsigned count, 1195 uint64_t addr, unsigned count,
1184 uint32_t incr, uint32_t flags); 1196 uint32_t incr, uint32_t flags);
1185 } vm; 1197 } vm;
@@ -1757,6 +1769,7 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
1757#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) 1769#define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA))
1758#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ 1770#define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \
1759 (rdev->flags & RADEON_IS_IGP)) 1771 (rdev->flags & RADEON_IS_IGP))
1772#define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
1760 1773
1761/* 1774/*
1762 * BIOS helpers. 1775 * BIOS helpers.
@@ -1801,7 +1814,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1801#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) 1814#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p))
1802#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) 1815#define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev))
1803#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) 1816#define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev))
1804#define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) 1817#define radeon_asic_vm_set_page(rdev, ib, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (ib), (pe), (addr), (count), (incr), (flags)))
1805#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) 1818#define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp))
1806#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) 1819#define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp))
1807#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) 1820#define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp))
@@ -1851,6 +1864,7 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1851/* Common functions */ 1864/* Common functions */
1852/* AGP */ 1865/* AGP */
1853extern int radeon_gpu_reset(struct radeon_device *rdev); 1866extern int radeon_gpu_reset(struct radeon_device *rdev);
1867extern void r600_set_bios_scratch_engine_hung(struct radeon_device *rdev, bool hung);
1854extern void radeon_agp_disable(struct radeon_device *rdev); 1868extern void radeon_agp_disable(struct radeon_device *rdev);
1855extern int radeon_modeset_init(struct radeon_device *rdev); 1869extern int radeon_modeset_init(struct radeon_device *rdev);
1856extern void radeon_modeset_fini(struct radeon_device *rdev); 1870extern void radeon_modeset_fini(struct radeon_device *rdev);
@@ -1972,6 +1986,19 @@ static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1972static inline void radeon_acpi_fini(struct radeon_device *rdev) { } 1986static inline void radeon_acpi_fini(struct radeon_device *rdev) { }
1973#endif 1987#endif
1974 1988
1989int radeon_cs_packet_parse(struct radeon_cs_parser *p,
1990 struct radeon_cs_packet *pkt,
1991 unsigned idx);
1992bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
1993void radeon_cs_dump_packet(struct radeon_cs_parser *p,
1994 struct radeon_cs_packet *pkt);
1995int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
1996 struct radeon_cs_reloc **cs_reloc,
1997 int nomm);
1998int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
1999 uint32_t *vline_start_end,
2000 uint32_t *vline_status);
2001
1975#include "radeon_object.h" 2002#include "radeon_object.h"
1976 2003
1977#endif 2004#endif
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 0b202c07fe50..67f008febec7 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -946,7 +946,7 @@ static struct radeon_asic r600_asic = {
946 .cs_parse = &r600_cs_parse, 946 .cs_parse = &r600_cs_parse,
947 .ring_test = &r600_ring_test, 947 .ring_test = &r600_ring_test,
948 .ib_test = &r600_ib_test, 948 .ib_test = &r600_ib_test,
949 .is_lockup = &r600_gpu_is_lockup, 949 .is_lockup = &r600_gfx_is_lockup,
950 }, 950 },
951 [R600_RING_TYPE_DMA_INDEX] = { 951 [R600_RING_TYPE_DMA_INDEX] = {
952 .ib_execute = &r600_dma_ring_ib_execute, 952 .ib_execute = &r600_dma_ring_ib_execute,
@@ -1030,7 +1030,7 @@ static struct radeon_asic rs780_asic = {
1030 .cs_parse = &r600_cs_parse, 1030 .cs_parse = &r600_cs_parse,
1031 .ring_test = &r600_ring_test, 1031 .ring_test = &r600_ring_test,
1032 .ib_test = &r600_ib_test, 1032 .ib_test = &r600_ib_test,
1033 .is_lockup = &r600_gpu_is_lockup, 1033 .is_lockup = &r600_gfx_is_lockup,
1034 }, 1034 },
1035 [R600_RING_TYPE_DMA_INDEX] = { 1035 [R600_RING_TYPE_DMA_INDEX] = {
1036 .ib_execute = &r600_dma_ring_ib_execute, 1036 .ib_execute = &r600_dma_ring_ib_execute,
@@ -1114,7 +1114,7 @@ static struct radeon_asic rv770_asic = {
1114 .cs_parse = &r600_cs_parse, 1114 .cs_parse = &r600_cs_parse,
1115 .ring_test = &r600_ring_test, 1115 .ring_test = &r600_ring_test,
1116 .ib_test = &r600_ib_test, 1116 .ib_test = &r600_ib_test,
1117 .is_lockup = &r600_gpu_is_lockup, 1117 .is_lockup = &r600_gfx_is_lockup,
1118 }, 1118 },
1119 [R600_RING_TYPE_DMA_INDEX] = { 1119 [R600_RING_TYPE_DMA_INDEX] = {
1120 .ib_execute = &r600_dma_ring_ib_execute, 1120 .ib_execute = &r600_dma_ring_ib_execute,
@@ -1198,7 +1198,7 @@ static struct radeon_asic evergreen_asic = {
1198 .cs_parse = &evergreen_cs_parse, 1198 .cs_parse = &evergreen_cs_parse,
1199 .ring_test = &r600_ring_test, 1199 .ring_test = &r600_ring_test,
1200 .ib_test = &r600_ib_test, 1200 .ib_test = &r600_ib_test,
1201 .is_lockup = &evergreen_gpu_is_lockup, 1201 .is_lockup = &evergreen_gfx_is_lockup,
1202 }, 1202 },
1203 [R600_RING_TYPE_DMA_INDEX] = { 1203 [R600_RING_TYPE_DMA_INDEX] = {
1204 .ib_execute = &evergreen_dma_ring_ib_execute, 1204 .ib_execute = &evergreen_dma_ring_ib_execute,
@@ -1207,7 +1207,7 @@ static struct radeon_asic evergreen_asic = {
1207 .cs_parse = &evergreen_dma_cs_parse, 1207 .cs_parse = &evergreen_dma_cs_parse,
1208 .ring_test = &r600_dma_ring_test, 1208 .ring_test = &r600_dma_ring_test,
1209 .ib_test = &r600_dma_ib_test, 1209 .ib_test = &r600_dma_ib_test,
1210 .is_lockup = &r600_dma_is_lockup, 1210 .is_lockup = &evergreen_dma_is_lockup,
1211 } 1211 }
1212 }, 1212 },
1213 .irq = { 1213 .irq = {
@@ -1282,7 +1282,7 @@ static struct radeon_asic sumo_asic = {
1282 .cs_parse = &evergreen_cs_parse, 1282 .cs_parse = &evergreen_cs_parse,
1283 .ring_test = &r600_ring_test, 1283 .ring_test = &r600_ring_test,
1284 .ib_test = &r600_ib_test, 1284 .ib_test = &r600_ib_test,
1285 .is_lockup = &evergreen_gpu_is_lockup, 1285 .is_lockup = &evergreen_gfx_is_lockup,
1286 }, 1286 },
1287 [R600_RING_TYPE_DMA_INDEX] = { 1287 [R600_RING_TYPE_DMA_INDEX] = {
1288 .ib_execute = &evergreen_dma_ring_ib_execute, 1288 .ib_execute = &evergreen_dma_ring_ib_execute,
@@ -1291,7 +1291,7 @@ static struct radeon_asic sumo_asic = {
1291 .cs_parse = &evergreen_dma_cs_parse, 1291 .cs_parse = &evergreen_dma_cs_parse,
1292 .ring_test = &r600_dma_ring_test, 1292 .ring_test = &r600_dma_ring_test,
1293 .ib_test = &r600_dma_ib_test, 1293 .ib_test = &r600_dma_ib_test,
1294 .is_lockup = &r600_dma_is_lockup, 1294 .is_lockup = &evergreen_dma_is_lockup,
1295 } 1295 }
1296 }, 1296 },
1297 .irq = { 1297 .irq = {
@@ -1366,7 +1366,7 @@ static struct radeon_asic btc_asic = {
1366 .cs_parse = &evergreen_cs_parse, 1366 .cs_parse = &evergreen_cs_parse,
1367 .ring_test = &r600_ring_test, 1367 .ring_test = &r600_ring_test,
1368 .ib_test = &r600_ib_test, 1368 .ib_test = &r600_ib_test,
1369 .is_lockup = &evergreen_gpu_is_lockup, 1369 .is_lockup = &evergreen_gfx_is_lockup,
1370 }, 1370 },
1371 [R600_RING_TYPE_DMA_INDEX] = { 1371 [R600_RING_TYPE_DMA_INDEX] = {
1372 .ib_execute = &evergreen_dma_ring_ib_execute, 1372 .ib_execute = &evergreen_dma_ring_ib_execute,
@@ -1375,7 +1375,7 @@ static struct radeon_asic btc_asic = {
1375 .cs_parse = &evergreen_dma_cs_parse, 1375 .cs_parse = &evergreen_dma_cs_parse,
1376 .ring_test = &r600_dma_ring_test, 1376 .ring_test = &r600_dma_ring_test,
1377 .ib_test = &r600_dma_ib_test, 1377 .ib_test = &r600_dma_ib_test,
1378 .is_lockup = &r600_dma_is_lockup, 1378 .is_lockup = &evergreen_dma_is_lockup,
1379 } 1379 }
1380 }, 1380 },
1381 .irq = { 1381 .irq = {
@@ -1445,7 +1445,7 @@ static struct radeon_asic cayman_asic = {
1445 .vm = { 1445 .vm = {
1446 .init = &cayman_vm_init, 1446 .init = &cayman_vm_init,
1447 .fini = &cayman_vm_fini, 1447 .fini = &cayman_vm_fini,
1448 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1448 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1449 .set_page = &cayman_vm_set_page, 1449 .set_page = &cayman_vm_set_page,
1450 }, 1450 },
1451 .ring = { 1451 .ring = {
@@ -1457,7 +1457,7 @@ static struct radeon_asic cayman_asic = {
1457 .cs_parse = &evergreen_cs_parse, 1457 .cs_parse = &evergreen_cs_parse,
1458 .ring_test = &r600_ring_test, 1458 .ring_test = &r600_ring_test,
1459 .ib_test = &r600_ib_test, 1459 .ib_test = &r600_ib_test,
1460 .is_lockup = &evergreen_gpu_is_lockup, 1460 .is_lockup = &cayman_gfx_is_lockup,
1461 .vm_flush = &cayman_vm_flush, 1461 .vm_flush = &cayman_vm_flush,
1462 }, 1462 },
1463 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1463 [CAYMAN_RING_TYPE_CP1_INDEX] = {
@@ -1468,7 +1468,7 @@ static struct radeon_asic cayman_asic = {
1468 .cs_parse = &evergreen_cs_parse, 1468 .cs_parse = &evergreen_cs_parse,
1469 .ring_test = &r600_ring_test, 1469 .ring_test = &r600_ring_test,
1470 .ib_test = &r600_ib_test, 1470 .ib_test = &r600_ib_test,
1471 .is_lockup = &evergreen_gpu_is_lockup, 1471 .is_lockup = &cayman_gfx_is_lockup,
1472 .vm_flush = &cayman_vm_flush, 1472 .vm_flush = &cayman_vm_flush,
1473 }, 1473 },
1474 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1474 [CAYMAN_RING_TYPE_CP2_INDEX] = {
@@ -1479,7 +1479,7 @@ static struct radeon_asic cayman_asic = {
1479 .cs_parse = &evergreen_cs_parse, 1479 .cs_parse = &evergreen_cs_parse,
1480 .ring_test = &r600_ring_test, 1480 .ring_test = &r600_ring_test,
1481 .ib_test = &r600_ib_test, 1481 .ib_test = &r600_ib_test,
1482 .is_lockup = &evergreen_gpu_is_lockup, 1482 .is_lockup = &cayman_gfx_is_lockup,
1483 .vm_flush = &cayman_vm_flush, 1483 .vm_flush = &cayman_vm_flush,
1484 }, 1484 },
1485 [R600_RING_TYPE_DMA_INDEX] = { 1485 [R600_RING_TYPE_DMA_INDEX] = {
@@ -1572,7 +1572,7 @@ static struct radeon_asic trinity_asic = {
1572 .vm = { 1572 .vm = {
1573 .init = &cayman_vm_init, 1573 .init = &cayman_vm_init,
1574 .fini = &cayman_vm_fini, 1574 .fini = &cayman_vm_fini,
1575 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1575 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1576 .set_page = &cayman_vm_set_page, 1576 .set_page = &cayman_vm_set_page,
1577 }, 1577 },
1578 .ring = { 1578 .ring = {
@@ -1584,7 +1584,7 @@ static struct radeon_asic trinity_asic = {
1584 .cs_parse = &evergreen_cs_parse, 1584 .cs_parse = &evergreen_cs_parse,
1585 .ring_test = &r600_ring_test, 1585 .ring_test = &r600_ring_test,
1586 .ib_test = &r600_ib_test, 1586 .ib_test = &r600_ib_test,
1587 .is_lockup = &evergreen_gpu_is_lockup, 1587 .is_lockup = &cayman_gfx_is_lockup,
1588 .vm_flush = &cayman_vm_flush, 1588 .vm_flush = &cayman_vm_flush,
1589 }, 1589 },
1590 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1590 [CAYMAN_RING_TYPE_CP1_INDEX] = {
@@ -1595,7 +1595,7 @@ static struct radeon_asic trinity_asic = {
1595 .cs_parse = &evergreen_cs_parse, 1595 .cs_parse = &evergreen_cs_parse,
1596 .ring_test = &r600_ring_test, 1596 .ring_test = &r600_ring_test,
1597 .ib_test = &r600_ib_test, 1597 .ib_test = &r600_ib_test,
1598 .is_lockup = &evergreen_gpu_is_lockup, 1598 .is_lockup = &cayman_gfx_is_lockup,
1599 .vm_flush = &cayman_vm_flush, 1599 .vm_flush = &cayman_vm_flush,
1600 }, 1600 },
1601 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1601 [CAYMAN_RING_TYPE_CP2_INDEX] = {
@@ -1606,7 +1606,7 @@ static struct radeon_asic trinity_asic = {
1606 .cs_parse = &evergreen_cs_parse, 1606 .cs_parse = &evergreen_cs_parse,
1607 .ring_test = &r600_ring_test, 1607 .ring_test = &r600_ring_test,
1608 .ib_test = &r600_ib_test, 1608 .ib_test = &r600_ib_test,
1609 .is_lockup = &evergreen_gpu_is_lockup, 1609 .is_lockup = &cayman_gfx_is_lockup,
1610 .vm_flush = &cayman_vm_flush, 1610 .vm_flush = &cayman_vm_flush,
1611 }, 1611 },
1612 [R600_RING_TYPE_DMA_INDEX] = { 1612 [R600_RING_TYPE_DMA_INDEX] = {
@@ -1699,7 +1699,7 @@ static struct radeon_asic si_asic = {
1699 .vm = { 1699 .vm = {
1700 .init = &si_vm_init, 1700 .init = &si_vm_init,
1701 .fini = &si_vm_fini, 1701 .fini = &si_vm_fini,
1702 .pt_ring_index = RADEON_RING_TYPE_GFX_INDEX, 1702 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1703 .set_page = &si_vm_set_page, 1703 .set_page = &si_vm_set_page,
1704 }, 1704 },
1705 .ring = { 1705 .ring = {
@@ -1711,7 +1711,7 @@ static struct radeon_asic si_asic = {
1711 .cs_parse = NULL, 1711 .cs_parse = NULL,
1712 .ring_test = &r600_ring_test, 1712 .ring_test = &r600_ring_test,
1713 .ib_test = &r600_ib_test, 1713 .ib_test = &r600_ib_test,
1714 .is_lockup = &si_gpu_is_lockup, 1714 .is_lockup = &si_gfx_is_lockup,
1715 .vm_flush = &si_vm_flush, 1715 .vm_flush = &si_vm_flush,
1716 }, 1716 },
1717 [CAYMAN_RING_TYPE_CP1_INDEX] = { 1717 [CAYMAN_RING_TYPE_CP1_INDEX] = {
@@ -1722,7 +1722,7 @@ static struct radeon_asic si_asic = {
1722 .cs_parse = NULL, 1722 .cs_parse = NULL,
1723 .ring_test = &r600_ring_test, 1723 .ring_test = &r600_ring_test,
1724 .ib_test = &r600_ib_test, 1724 .ib_test = &r600_ib_test,
1725 .is_lockup = &si_gpu_is_lockup, 1725 .is_lockup = &si_gfx_is_lockup,
1726 .vm_flush = &si_vm_flush, 1726 .vm_flush = &si_vm_flush,
1727 }, 1727 },
1728 [CAYMAN_RING_TYPE_CP2_INDEX] = { 1728 [CAYMAN_RING_TYPE_CP2_INDEX] = {
@@ -1733,7 +1733,7 @@ static struct radeon_asic si_asic = {
1733 .cs_parse = NULL, 1733 .cs_parse = NULL,
1734 .ring_test = &r600_ring_test, 1734 .ring_test = &r600_ring_test,
1735 .ib_test = &r600_ib_test, 1735 .ib_test = &r600_ib_test,
1736 .is_lockup = &si_gpu_is_lockup, 1736 .is_lockup = &si_gfx_is_lockup,
1737 .vm_flush = &si_vm_flush, 1737 .vm_flush = &si_vm_flush,
1738 }, 1738 },
1739 [R600_RING_TYPE_DMA_INDEX] = { 1739 [R600_RING_TYPE_DMA_INDEX] = {
@@ -1744,7 +1744,7 @@ static struct radeon_asic si_asic = {
1744 .cs_parse = NULL, 1744 .cs_parse = NULL,
1745 .ring_test = &r600_dma_ring_test, 1745 .ring_test = &r600_dma_ring_test,
1746 .ib_test = &r600_dma_ib_test, 1746 .ib_test = &r600_dma_ib_test,
1747 .is_lockup = &cayman_dma_is_lockup, 1747 .is_lockup = &si_dma_is_lockup,
1748 .vm_flush = &si_dma_vm_flush, 1748 .vm_flush = &si_dma_vm_flush,
1749 }, 1749 },
1750 [CAYMAN_RING_TYPE_DMA1_INDEX] = { 1750 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
@@ -1755,7 +1755,7 @@ static struct radeon_asic si_asic = {
1755 .cs_parse = NULL, 1755 .cs_parse = NULL,
1756 .ring_test = &r600_dma_ring_test, 1756 .ring_test = &r600_dma_ring_test,
1757 .ib_test = &r600_dma_ib_test, 1757 .ib_test = &r600_dma_ib_test,
1758 .is_lockup = &cayman_dma_is_lockup, 1758 .is_lockup = &si_dma_is_lockup,
1759 .vm_flush = &si_dma_vm_flush, 1759 .vm_flush = &si_dma_vm_flush,
1760 } 1760 }
1761 }, 1761 },
@@ -1944,9 +1944,13 @@ int radeon_asic_init(struct radeon_device *rdev)
1944 case CHIP_TAHITI: 1944 case CHIP_TAHITI:
1945 case CHIP_PITCAIRN: 1945 case CHIP_PITCAIRN:
1946 case CHIP_VERDE: 1946 case CHIP_VERDE:
1947 case CHIP_OLAND:
1947 rdev->asic = &si_asic; 1948 rdev->asic = &si_asic;
1948 /* set num crtcs */ 1949 /* set num crtcs */
1949 rdev->num_crtc = 6; 1950 if (rdev->family == CHIP_OLAND)
1951 rdev->num_crtc = 2;
1952 else
1953 rdev->num_crtc = 6;
1950 break; 1954 break;
1951 default: 1955 default:
1952 /* FIXME: not supported yet */ 1956 /* FIXME: not supported yet */
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 15d70e613076..f4134a823958 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -319,7 +319,7 @@ void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
319 bool emit_wait); 319 bool emit_wait);
320void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 320void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
321bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 321bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
322bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 322bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
323int r600_asic_reset(struct radeon_device *rdev); 323int r600_asic_reset(struct radeon_device *rdev);
324int r600_set_surface_reg(struct radeon_device *rdev, int reg, 324int r600_set_surface_reg(struct radeon_device *rdev, int reg,
325 uint32_t tiling_flags, uint32_t pitch, 325 uint32_t tiling_flags, uint32_t pitch,
@@ -422,7 +422,8 @@ int evergreen_init(struct radeon_device *rdev);
422void evergreen_fini(struct radeon_device *rdev); 422void evergreen_fini(struct radeon_device *rdev);
423int evergreen_suspend(struct radeon_device *rdev); 423int evergreen_suspend(struct radeon_device *rdev);
424int evergreen_resume(struct radeon_device *rdev); 424int evergreen_resume(struct radeon_device *rdev);
425bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 425bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
426bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
426int evergreen_asic_reset(struct radeon_device *rdev); 427int evergreen_asic_reset(struct radeon_device *rdev);
427void evergreen_bandwidth_update(struct radeon_device *rdev); 428void evergreen_bandwidth_update(struct radeon_device *rdev);
428void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 429void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -473,13 +474,16 @@ int cayman_vm_init(struct radeon_device *rdev);
473void cayman_vm_fini(struct radeon_device *rdev); 474void cayman_vm_fini(struct radeon_device *rdev);
474void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 475void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
475uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags); 476uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
476void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe, 477void cayman_vm_set_page(struct radeon_device *rdev,
478 struct radeon_ib *ib,
479 uint64_t pe,
477 uint64_t addr, unsigned count, 480 uint64_t addr, unsigned count,
478 uint32_t incr, uint32_t flags); 481 uint32_t incr, uint32_t flags);
479int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 482int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
480int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); 483int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
481void cayman_dma_ring_ib_execute(struct radeon_device *rdev, 484void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
482 struct radeon_ib *ib); 485 struct radeon_ib *ib);
486bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
483bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring); 487bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
484void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 488void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
485 489
@@ -496,14 +500,17 @@ int si_init(struct radeon_device *rdev);
496void si_fini(struct radeon_device *rdev); 500void si_fini(struct radeon_device *rdev);
497int si_suspend(struct radeon_device *rdev); 501int si_suspend(struct radeon_device *rdev);
498int si_resume(struct radeon_device *rdev); 502int si_resume(struct radeon_device *rdev);
499bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp); 503bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
504bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
500int si_asic_reset(struct radeon_device *rdev); 505int si_asic_reset(struct radeon_device *rdev);
501void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 506void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
502int si_irq_set(struct radeon_device *rdev); 507int si_irq_set(struct radeon_device *rdev);
503int si_irq_process(struct radeon_device *rdev); 508int si_irq_process(struct radeon_device *rdev);
504int si_vm_init(struct radeon_device *rdev); 509int si_vm_init(struct radeon_device *rdev);
505void si_vm_fini(struct radeon_device *rdev); 510void si_vm_fini(struct radeon_device *rdev);
506void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 511void si_vm_set_page(struct radeon_device *rdev,
512 struct radeon_ib *ib,
513 uint64_t pe,
507 uint64_t addr, unsigned count, 514 uint64_t addr, unsigned count,
508 uint32_t incr, uint32_t flags); 515 uint32_t incr, uint32_t flags);
509void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 516void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 9143fc45e35b..efc4f6441ef4 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -27,6 +27,8 @@
27 * Authors: 27 * Authors:
28 * Kevin E. Martin <martin@valinux.com> 28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com> 29 * Gareth Hughes <gareth@valinux.com>
30 *
31 * ------------------------ This file is DEPRECATED! -------------------------
30 */ 32 */
31 33
32#include <linux/module.h> 34#include <linux/module.h>
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index 5407459e56d2..70d38241b083 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -29,9 +29,6 @@
29#include "radeon_reg.h" 29#include "radeon_reg.h"
30#include "radeon.h" 30#include "radeon.h"
31 31
32void r100_cs_dump_packet(struct radeon_cs_parser *p,
33 struct radeon_cs_packet *pkt);
34
35static int radeon_cs_parser_relocs(struct radeon_cs_parser *p) 32static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
36{ 33{
37 struct drm_device *ddev = p->rdev->ddev; 34 struct drm_device *ddev = p->rdev->ddev;
@@ -128,18 +125,6 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
128 return 0; 125 return 0;
129} 126}
130 127
131static void radeon_cs_sync_to(struct radeon_cs_parser *p,
132 struct radeon_fence *fence)
133{
134 struct radeon_fence *other;
135
136 if (!fence)
137 return;
138
139 other = p->ib.sync_to[fence->ring];
140 p->ib.sync_to[fence->ring] = radeon_fence_later(fence, other);
141}
142
143static void radeon_cs_sync_rings(struct radeon_cs_parser *p) 128static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
144{ 129{
145 int i; 130 int i;
@@ -148,7 +133,7 @@ static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
148 if (!p->relocs[i].robj) 133 if (!p->relocs[i].robj)
149 continue; 134 continue;
150 135
151 radeon_cs_sync_to(p, p->relocs[i].robj->tbo.sync_obj); 136 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
152 } 137 }
153} 138}
154 139
@@ -203,7 +188,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
203 p->chunks[i].length_dw = user_chunk.length_dw; 188 p->chunks[i].length_dw = user_chunk.length_dw;
204 p->chunks[i].kdata = NULL; 189 p->chunks[i].kdata = NULL;
205 p->chunks[i].chunk_id = user_chunk.chunk_id; 190 p->chunks[i].chunk_id = user_chunk.chunk_id;
206 191 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
207 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) { 192 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
208 p->chunk_relocs_idx = i; 193 p->chunk_relocs_idx = i;
209 } 194 }
@@ -226,9 +211,6 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
226 return -EINVAL; 211 return -EINVAL;
227 } 212 }
228 213
229 p->chunks[i].length_dw = user_chunk.length_dw;
230 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
231
232 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data; 214 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
233 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) || 215 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
234 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) { 216 (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
@@ -478,8 +460,9 @@ static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
478 goto out; 460 goto out;
479 } 461 }
480 radeon_cs_sync_rings(parser); 462 radeon_cs_sync_rings(parser);
481 radeon_cs_sync_to(parser, vm->fence); 463 radeon_ib_sync_to(&parser->ib, vm->fence);
482 radeon_cs_sync_to(parser, radeon_vm_grab_id(rdev, vm, parser->ring)); 464 radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
465 rdev, vm, parser->ring));
483 466
484 if ((rdev->family >= CHIP_TAHITI) && 467 if ((rdev->family >= CHIP_TAHITI) &&
485 (parser->chunk_const_ib_idx != -1)) { 468 (parser->chunk_const_ib_idx != -1)) {
@@ -648,3 +631,152 @@ u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
648 idx_value = ibc->kpage[new_page][pg_offset/4]; 631 idx_value = ibc->kpage[new_page][pg_offset/4];
649 return idx_value; 632 return idx_value;
650} 633}
634
635/**
636 * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
637 * @parser: parser structure holding parsing context.
638 * @pkt: where to store packet information
639 *
640 * Assume that chunk_ib_index is properly set. Will return -EINVAL
641 * if packet is bigger than remaining ib size. or if packets is unknown.
642 **/
643int radeon_cs_packet_parse(struct radeon_cs_parser *p,
644 struct radeon_cs_packet *pkt,
645 unsigned idx)
646{
647 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
648 struct radeon_device *rdev = p->rdev;
649 uint32_t header;
650
651 if (idx >= ib_chunk->length_dw) {
652 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
653 idx, ib_chunk->length_dw);
654 return -EINVAL;
655 }
656 header = radeon_get_ib_value(p, idx);
657 pkt->idx = idx;
658 pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
659 pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
660 pkt->one_reg_wr = 0;
661 switch (pkt->type) {
662 case RADEON_PACKET_TYPE0:
663 if (rdev->family < CHIP_R600) {
664 pkt->reg = R100_CP_PACKET0_GET_REG(header);
665 pkt->one_reg_wr =
666 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
667 } else
668 pkt->reg = R600_CP_PACKET0_GET_REG(header);
669 break;
670 case RADEON_PACKET_TYPE3:
671 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
672 break;
673 case RADEON_PACKET_TYPE2:
674 pkt->count = -1;
675 break;
676 default:
677 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
678 return -EINVAL;
679 }
680 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
681 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
682 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
683 return -EINVAL;
684 }
685 return 0;
686}
687
688/**
689 * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
690 * @p: structure holding the parser context.
691 *
692 * Check if the next packet is NOP relocation packet3.
693 **/
694bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
695{
696 struct radeon_cs_packet p3reloc;
697 int r;
698
699 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
700 if (r)
701 return false;
702 if (p3reloc.type != RADEON_PACKET_TYPE3)
703 return false;
704 if (p3reloc.opcode != RADEON_PACKET3_NOP)
705 return false;
706 return true;
707}
708
709/**
710 * radeon_cs_dump_packet() - dump raw packet context
711 * @p: structure holding the parser context.
712 * @pkt: structure holding the packet.
713 *
714 * Used mostly for debugging and error reporting.
715 **/
716void radeon_cs_dump_packet(struct radeon_cs_parser *p,
717 struct radeon_cs_packet *pkt)
718{
719 volatile uint32_t *ib;
720 unsigned i;
721 unsigned idx;
722
723 ib = p->ib.ptr;
724 idx = pkt->idx;
725 for (i = 0; i <= (pkt->count + 1); i++, idx++)
726 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
727}
728
729/**
730 * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
731 * @parser: parser structure holding parsing context.
732 * @data: pointer to relocation data
733 * @offset_start: starting offset
734 * @offset_mask: offset mask (to align start offset on)
735 * @reloc: reloc informations
736 *
737 * Check if next packet is relocation packet3, do bo validation and compute
738 * GPU offset using the provided start.
739 **/
740int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
741 struct radeon_cs_reloc **cs_reloc,
742 int nomm)
743{
744 struct radeon_cs_chunk *relocs_chunk;
745 struct radeon_cs_packet p3reloc;
746 unsigned idx;
747 int r;
748
749 if (p->chunk_relocs_idx == -1) {
750 DRM_ERROR("No relocation chunk !\n");
751 return -EINVAL;
752 }
753 *cs_reloc = NULL;
754 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
755 r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
756 if (r)
757 return r;
758 p->idx += p3reloc.count + 2;
759 if (p3reloc.type != RADEON_PACKET_TYPE3 ||
760 p3reloc.opcode != RADEON_PACKET3_NOP) {
761 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
762 p3reloc.idx);
763 radeon_cs_dump_packet(p, &p3reloc);
764 return -EINVAL;
765 }
766 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
767 if (idx >= relocs_chunk->length_dw) {
768 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
769 idx, relocs_chunk->length_dw);
770 radeon_cs_dump_packet(p, &p3reloc);
771 return -EINVAL;
772 }
773 /* FIXME: we assume reloc size is 4 dwords */
774 if (nomm) {
775 *cs_reloc = p->relocs;
776 (*cs_reloc)->lobj.gpu_offset =
777 (u64)relocs_chunk->kdata[idx + 3] << 32;
778 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
779 } else
780 *cs_reloc = p->relocs_ptr[(idx / 4)];
781 return 0;
782}
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 0d6562bb0c93..8794de10a6c7 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -93,6 +93,7 @@ static const char radeon_family_name[][16] = {
93 "TAHITI", 93 "TAHITI",
94 "PITCAIRN", 94 "PITCAIRN",
95 "VERDE", 95 "VERDE",
96 "OLAND",
96 "LAST", 97 "LAST",
97}; 98};
98 99
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index d9bf96ee299a..833484da12d9 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -123,15 +123,25 @@ struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
123 int flags); 123 int flags);
124struct drm_gem_object *radeon_gem_prime_import(struct drm_device *dev, 124struct drm_gem_object *radeon_gem_prime_import(struct drm_device *dev,
125 struct dma_buf *dma_buf); 125 struct dma_buf *dma_buf);
126extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
127 unsigned long arg);
126 128
127#if defined(CONFIG_DEBUG_FS) 129#if defined(CONFIG_DEBUG_FS)
128int radeon_debugfs_init(struct drm_minor *minor); 130int radeon_debugfs_init(struct drm_minor *minor);
129void radeon_debugfs_cleanup(struct drm_minor *minor); 131void radeon_debugfs_cleanup(struct drm_minor *minor);
130#endif 132#endif
131 133
134/* atpx handler */
135#if defined(CONFIG_VGA_SWITCHEROO)
136void radeon_register_atpx_handler(void);
137void radeon_unregister_atpx_handler(void);
138#else
139static inline void radeon_register_atpx_handler(void) {}
140static inline void radeon_unregister_atpx_handler(void) {}
141#endif
132 142
133int radeon_no_wb; 143int radeon_no_wb;
134int radeon_modeset = -1; 144int radeon_modeset = 1;
135int radeon_dynclks = -1; 145int radeon_dynclks = -1;
136int radeon_r4xx_atom = 0; 146int radeon_r4xx_atom = 0;
137int radeon_agpmode = 0; 147int radeon_agpmode = 0;
@@ -199,6 +209,14 @@ module_param_named(msi, radeon_msi, int, 0444);
199MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)"); 209MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (defaul 10000 = 10 seconds, 0 = disable)");
200module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444); 210module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
201 211
212static struct pci_device_id pciidlist[] = {
213 radeon_PCI_IDS
214};
215
216MODULE_DEVICE_TABLE(pci, pciidlist);
217
218#ifdef CONFIG_DRM_RADEON_UMS
219
202static int radeon_suspend(struct drm_device *dev, pm_message_t state) 220static int radeon_suspend(struct drm_device *dev, pm_message_t state)
203{ 221{
204 drm_radeon_private_t *dev_priv = dev->dev_private; 222 drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -227,14 +245,6 @@ static int radeon_resume(struct drm_device *dev)
227 return 0; 245 return 0;
228} 246}
229 247
230static struct pci_device_id pciidlist[] = {
231 radeon_PCI_IDS
232};
233
234#if defined(CONFIG_DRM_RADEON_KMS)
235MODULE_DEVICE_TABLE(pci, pciidlist);
236#endif
237
238static const struct file_operations radeon_driver_old_fops = { 248static const struct file_operations radeon_driver_old_fops = {
239 .owner = THIS_MODULE, 249 .owner = THIS_MODULE,
240 .open = drm_open, 250 .open = drm_open,
@@ -284,6 +294,8 @@ static struct drm_driver driver_old = {
284 .patchlevel = DRIVER_PATCHLEVEL, 294 .patchlevel = DRIVER_PATCHLEVEL,
285}; 295};
286 296
297#endif
298
287static struct drm_driver kms_driver; 299static struct drm_driver kms_driver;
288 300
289static int radeon_kick_out_firmware_fb(struct pci_dev *pdev) 301static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
@@ -411,10 +423,12 @@ static struct drm_driver kms_driver = {
411static struct drm_driver *driver; 423static struct drm_driver *driver;
412static struct pci_driver *pdriver; 424static struct pci_driver *pdriver;
413 425
426#ifdef CONFIG_DRM_RADEON_UMS
414static struct pci_driver radeon_pci_driver = { 427static struct pci_driver radeon_pci_driver = {
415 .name = DRIVER_NAME, 428 .name = DRIVER_NAME,
416 .id_table = pciidlist, 429 .id_table = pciidlist,
417}; 430};
431#endif
418 432
419static struct pci_driver radeon_kms_pci_driver = { 433static struct pci_driver radeon_kms_pci_driver = {
420 .name = DRIVER_NAME, 434 .name = DRIVER_NAME,
@@ -427,28 +441,6 @@ static struct pci_driver radeon_kms_pci_driver = {
427 441
428static int __init radeon_init(void) 442static int __init radeon_init(void)
429{ 443{
430 driver = &driver_old;
431 pdriver = &radeon_pci_driver;
432 driver->num_ioctls = radeon_max_ioctl;
433#ifdef CONFIG_VGA_CONSOLE
434 if (vgacon_text_force() && radeon_modeset == -1) {
435 DRM_INFO("VGACON disable radeon kernel modesetting.\n");
436 driver = &driver_old;
437 pdriver = &radeon_pci_driver;
438 driver->driver_features &= ~DRIVER_MODESET;
439 radeon_modeset = 0;
440 }
441#endif
442 /* if enabled by default */
443 if (radeon_modeset == -1) {
444#ifdef CONFIG_DRM_RADEON_KMS
445 DRM_INFO("radeon defaulting to kernel modesetting.\n");
446 radeon_modeset = 1;
447#else
448 DRM_INFO("radeon defaulting to userspace modesetting.\n");
449 radeon_modeset = 0;
450#endif
451 }
452 if (radeon_modeset == 1) { 444 if (radeon_modeset == 1) {
453 DRM_INFO("radeon kernel modesetting enabled.\n"); 445 DRM_INFO("radeon kernel modesetting enabled.\n");
454 driver = &kms_driver; 446 driver = &kms_driver;
@@ -456,9 +448,21 @@ static int __init radeon_init(void)
456 driver->driver_features |= DRIVER_MODESET; 448 driver->driver_features |= DRIVER_MODESET;
457 driver->num_ioctls = radeon_max_kms_ioctl; 449 driver->num_ioctls = radeon_max_kms_ioctl;
458 radeon_register_atpx_handler(); 450 radeon_register_atpx_handler();
451
452 } else {
453#ifdef CONFIG_DRM_RADEON_UMS
454 DRM_INFO("radeon userspace modesetting enabled.\n");
455 driver = &driver_old;
456 pdriver = &radeon_pci_driver;
457 driver->driver_features &= ~DRIVER_MODESET;
458 driver->num_ioctls = radeon_max_ioctl;
459#else
460 DRM_ERROR("No UMS support in radeon module!\n");
461 return -EINVAL;
462#endif
459 } 463 }
460 /* if the vga console setting is enabled still 464
461 * let modprobe override it */ 465 /* let modprobe override vga console setting */
462 return drm_pci_init(driver, pdriver); 466 return drm_pci_init(driver, pdriver);
463} 467}
464 468
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index e7fdf163a8ca..b369d42f7de5 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -113,6 +113,9 @@
113#define DRIVER_MINOR 33 113#define DRIVER_MINOR 33
114#define DRIVER_PATCHLEVEL 0 114#define DRIVER_PATCHLEVEL 0
115 115
116/* The rest of the file is DEPRECATED! */
117#ifdef CONFIG_DRM_RADEON_UMS
118
116enum radeon_cp_microcode_version { 119enum radeon_cp_microcode_version {
117 UCODE_R100, 120 UCODE_R100,
118 UCODE_R200, 121 UCODE_R200,
@@ -418,8 +421,6 @@ extern int radeon_driver_open(struct drm_device *dev,
418 struct drm_file *file_priv); 421 struct drm_file *file_priv);
419extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd, 422extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
420 unsigned long arg); 423 unsigned long arg);
421extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
422 unsigned long arg);
423 424
424extern int radeon_master_create(struct drm_device *dev, struct drm_master *master); 425extern int radeon_master_create(struct drm_device *dev, struct drm_master *master);
425extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master); 426extern void radeon_master_destroy(struct drm_device *dev, struct drm_master *master);
@@ -462,15 +463,6 @@ extern void r600_blit_swap(struct drm_device *dev,
462 int sx, int sy, int dx, int dy, 463 int sx, int sy, int dx, int dy,
463 int w, int h, int src_pitch, int dst_pitch, int cpp); 464 int w, int h, int src_pitch, int dst_pitch, int cpp);
464 465
465/* atpx handler */
466#if defined(CONFIG_VGA_SWITCHEROO)
467void radeon_register_atpx_handler(void);
468void radeon_unregister_atpx_handler(void);
469#else
470static inline void radeon_register_atpx_handler(void) {}
471static inline void radeon_unregister_atpx_handler(void) {}
472#endif
473
474/* Flags for stats.boxes 466/* Flags for stats.boxes
475 */ 467 */
476#define RADEON_BOX_DMA_IDLE 0x1 468#define RADEON_BOX_DMA_IDLE 0x1
@@ -2167,4 +2159,6 @@ extern void radeon_commit_ring(drm_radeon_private_t *dev_priv);
2167} while (0) 2159} while (0)
2168 2160
2169 2161
2162#endif /* CONFIG_DRM_RADEON_UMS */
2163
2170#endif /* __RADEON_DRV_H__ */ 2164#endif /* __RADEON_DRV_H__ */
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index d1fafeabea09..2d91123f2759 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -91,6 +91,7 @@ enum radeon_family {
91 CHIP_TAHITI, 91 CHIP_TAHITI,
92 CHIP_PITCAIRN, 92 CHIP_PITCAIRN,
93 CHIP_VERDE, 93 CHIP_VERDE,
94 CHIP_OLAND,
94 CHIP_LAST, 95 CHIP_LAST,
95}; 96};
96 97
diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c
index 6e24f84755b5..2c1341f63dc5 100644
--- a/drivers/gpu/drm/radeon/radeon_gart.c
+++ b/drivers/gpu/drm/radeon/radeon_gart.c
@@ -929,6 +929,7 @@ uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr)
929 */ 929 */
930static int radeon_vm_update_pdes(struct radeon_device *rdev, 930static int radeon_vm_update_pdes(struct radeon_device *rdev,
931 struct radeon_vm *vm, 931 struct radeon_vm *vm,
932 struct radeon_ib *ib,
932 uint64_t start, uint64_t end) 933 uint64_t start, uint64_t end)
933{ 934{
934 static const uint32_t incr = RADEON_VM_PTE_COUNT * 8; 935 static const uint32_t incr = RADEON_VM_PTE_COUNT * 8;
@@ -971,7 +972,7 @@ retry:
971 ((last_pt + incr * count) != pt)) { 972 ((last_pt + incr * count) != pt)) {
972 973
973 if (count) { 974 if (count) {
974 radeon_asic_vm_set_page(rdev, last_pde, 975 radeon_asic_vm_set_page(rdev, ib, last_pde,
975 last_pt, count, incr, 976 last_pt, count, incr,
976 RADEON_VM_PAGE_VALID); 977 RADEON_VM_PAGE_VALID);
977 } 978 }
@@ -985,7 +986,7 @@ retry:
985 } 986 }
986 987
987 if (count) { 988 if (count) {
988 radeon_asic_vm_set_page(rdev, last_pde, last_pt, count, 989 radeon_asic_vm_set_page(rdev, ib, last_pde, last_pt, count,
989 incr, RADEON_VM_PAGE_VALID); 990 incr, RADEON_VM_PAGE_VALID);
990 991
991 } 992 }
@@ -1009,6 +1010,7 @@ retry:
1009 */ 1010 */
1010static void radeon_vm_update_ptes(struct radeon_device *rdev, 1011static void radeon_vm_update_ptes(struct radeon_device *rdev,
1011 struct radeon_vm *vm, 1012 struct radeon_vm *vm,
1013 struct radeon_ib *ib,
1012 uint64_t start, uint64_t end, 1014 uint64_t start, uint64_t end,
1013 uint64_t dst, uint32_t flags) 1015 uint64_t dst, uint32_t flags)
1014{ 1016{
@@ -1038,7 +1040,7 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
1038 if ((last_pte + 8 * count) != pte) { 1040 if ((last_pte + 8 * count) != pte) {
1039 1041
1040 if (count) { 1042 if (count) {
1041 radeon_asic_vm_set_page(rdev, last_pte, 1043 radeon_asic_vm_set_page(rdev, ib, last_pte,
1042 last_dst, count, 1044 last_dst, count,
1043 RADEON_GPU_PAGE_SIZE, 1045 RADEON_GPU_PAGE_SIZE,
1044 flags); 1046 flags);
@@ -1056,7 +1058,8 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev,
1056 } 1058 }
1057 1059
1058 if (count) { 1060 if (count) {
1059 radeon_asic_vm_set_page(rdev, last_pte, last_dst, count, 1061 radeon_asic_vm_set_page(rdev, ib, last_pte,
1062 last_dst, count,
1060 RADEON_GPU_PAGE_SIZE, flags); 1063 RADEON_GPU_PAGE_SIZE, flags);
1061 } 1064 }
1062} 1065}
@@ -1080,8 +1083,7 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1080 struct ttm_mem_reg *mem) 1083 struct ttm_mem_reg *mem)
1081{ 1084{
1082 unsigned ridx = rdev->asic->vm.pt_ring_index; 1085 unsigned ridx = rdev->asic->vm.pt_ring_index;
1083 struct radeon_ring *ring = &rdev->ring[ridx]; 1086 struct radeon_ib ib;
1084 struct radeon_semaphore *sem = NULL;
1085 struct radeon_bo_va *bo_va; 1087 struct radeon_bo_va *bo_va;
1086 unsigned nptes, npdes, ndw; 1088 unsigned nptes, npdes, ndw;
1087 uint64_t addr; 1089 uint64_t addr;
@@ -1124,25 +1126,13 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1124 bo_va->valid = false; 1126 bo_va->valid = false;
1125 } 1127 }
1126 1128
1127 if (vm->fence && radeon_fence_signaled(vm->fence)) {
1128 radeon_fence_unref(&vm->fence);
1129 }
1130
1131 if (vm->fence && vm->fence->ring != ridx) {
1132 r = radeon_semaphore_create(rdev, &sem);
1133 if (r) {
1134 return r;
1135 }
1136 }
1137
1138 nptes = radeon_bo_ngpu_pages(bo); 1129 nptes = radeon_bo_ngpu_pages(bo);
1139 1130
1140 /* assume two extra pdes in case the mapping overlaps the borders */ 1131 /* assume two extra pdes in case the mapping overlaps the borders */
1141 npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 2; 1132 npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 2;
1142 1133
1143 /* estimate number of dw needed */ 1134 /* padding, etc. */
1144 /* semaphore, fence and padding */ 1135 ndw = 64;
1145 ndw = 32;
1146 1136
1147 if (RADEON_VM_BLOCK_SIZE > 11) 1137 if (RADEON_VM_BLOCK_SIZE > 11)
1148 /* reserve space for one header for every 2k dwords */ 1138 /* reserve space for one header for every 2k dwords */
@@ -1161,33 +1151,31 @@ int radeon_vm_bo_update_pte(struct radeon_device *rdev,
1161 /* reserve space for pde addresses */ 1151 /* reserve space for pde addresses */
1162 ndw += npdes * 2; 1152 ndw += npdes * 2;
1163 1153
1164 r = radeon_ring_lock(rdev, ring, ndw); 1154 /* update too big for an IB */
1165 if (r) { 1155 if (ndw > 0xfffff)
1166 return r; 1156 return -ENOMEM;
1167 }
1168 1157
1169 if (sem && radeon_fence_need_sync(vm->fence, ridx)) { 1158 r = radeon_ib_get(rdev, ridx, &ib, NULL, ndw * 4);
1170 radeon_semaphore_sync_rings(rdev, sem, vm->fence->ring, ridx); 1159 ib.length_dw = 0;
1171 radeon_fence_note_sync(vm->fence, ridx);
1172 }
1173 1160
1174 r = radeon_vm_update_pdes(rdev, vm, bo_va->soffset, bo_va->eoffset); 1161 r = radeon_vm_update_pdes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset);
1175 if (r) { 1162 if (r) {
1176 radeon_ring_unlock_undo(rdev, ring); 1163 radeon_ib_free(rdev, &ib);
1177 return r; 1164 return r;
1178 } 1165 }
1179 1166
1180 radeon_vm_update_ptes(rdev, vm, bo_va->soffset, bo_va->eoffset, 1167 radeon_vm_update_ptes(rdev, vm, &ib, bo_va->soffset, bo_va->eoffset,
1181 addr, bo_va->flags); 1168 addr, bo_va->flags);
1182 1169
1183 radeon_fence_unref(&vm->fence); 1170 radeon_ib_sync_to(&ib, vm->fence);
1184 r = radeon_fence_emit(rdev, &vm->fence, ridx); 1171 r = radeon_ib_schedule(rdev, &ib, NULL);
1185 if (r) { 1172 if (r) {
1186 radeon_ring_unlock_undo(rdev, ring); 1173 radeon_ib_free(rdev, &ib);
1187 return r; 1174 return r;
1188 } 1175 }
1189 radeon_ring_unlock_commit(rdev, ring); 1176 radeon_fence_unref(&vm->fence);
1190 radeon_semaphore_free(rdev, &sem, vm->fence); 1177 vm->fence = radeon_fence_ref(ib.fence);
1178 radeon_ib_free(rdev, &ib);
1191 radeon_fence_unref(&vm->last_flush); 1179 radeon_fence_unref(&vm->last_flush);
1192 1180
1193 return 0; 1181 return 0;
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index e7710339a6a7..8d68e972789a 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
@@ -28,6 +28,8 @@
28 * Authors: 28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com> 29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net> 30 * Michel D�zer <michel@daenzer.net>
31 *
32 * ------------------------ This file is DEPRECATED! -------------------------
31 */ 33 */
32 34
33#include <drm/drmP.h> 35#include <drm/drmP.h>
diff --git a/drivers/gpu/drm/radeon/radeon_mem.c b/drivers/gpu/drm/radeon/radeon_mem.c
index b9f067241633..d54d2d7c9031 100644
--- a/drivers/gpu/drm/radeon/radeon_mem.c
+++ b/drivers/gpu/drm/radeon/radeon_mem.c
@@ -27,6 +27,8 @@
27 * 27 *
28 * Authors: 28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com> 29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * ------------------------ This file is DEPRECATED! -------------------------
30 */ 32 */
31 33
32#include <drm/drmP.h> 34#include <drm/drmP.h>
diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
index 5d8f735d6aaf..7e2c2b7cf188 100644
--- a/drivers/gpu/drm/radeon/radeon_reg.h
+++ b/drivers/gpu/drm/radeon/radeon_reg.h
@@ -3706,4 +3706,19 @@
3706 3706
3707#define RV530_GB_PIPE_SELECT2 0x4124 3707#define RV530_GB_PIPE_SELECT2 0x4124
3708 3708
3709#define RADEON_CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
3710#define RADEON_CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
3711#define RADEON_CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
3712#define RADEON_CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
3713#define R100_CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
3714#define R600_CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
3715#define RADEON_PACKET_TYPE0 0
3716#define RADEON_PACKET_TYPE1 1
3717#define RADEON_PACKET_TYPE2 2
3718#define RADEON_PACKET_TYPE3 3
3719
3720#define RADEON_PACKET3_NOP 0x10
3721
3722#define RADEON_VLINE_STAT (1 << 12)
3723
3709#endif 3724#endif
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index cd72062d5a91..8d58e268ff6d 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -109,6 +109,25 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
109} 109}
110 110
111/** 111/**
112 * radeon_ib_sync_to - sync to fence before executing the IB
113 *
114 * @ib: IB object to add fence to
115 * @fence: fence to sync to
116 *
117 * Sync to the fence before executing the IB
118 */
119void radeon_ib_sync_to(struct radeon_ib *ib, struct radeon_fence *fence)
120{
121 struct radeon_fence *other;
122
123 if (!fence)
124 return;
125
126 other = ib->sync_to[fence->ring];
127 ib->sync_to[fence->ring] = radeon_fence_later(fence, other);
128}
129
130/**
112 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring 131 * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
113 * 132 *
114 * @rdev: radeon_device pointer 133 * @rdev: radeon_device pointer
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
index 8e9057b6a365..4d20910899d4 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -25,6 +25,8 @@
25 * Authors: 25 * Authors:
26 * Gareth Hughes <gareth@valinux.com> 26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com> 27 * Kevin E. Martin <martin@valinux.com>
28 *
29 * ------------------------ This file is DEPRECATED! -------------------------
28 */ 30 */
29 31
30#include <drm/drmP.h> 32#include <drm/drmP.h>
diff --git a/drivers/gpu/drm/radeon/rv515d.h b/drivers/gpu/drm/radeon/rv515d.h
index 590309a710b1..6927a200daf4 100644
--- a/drivers/gpu/drm/radeon/rv515d.h
+++ b/drivers/gpu/drm/radeon/rv515d.h
@@ -205,17 +205,6 @@
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n))) 206 REG_SET(PACKET3_COUNT, (n)))
207 207
208#define PACKET_TYPE0 0
209#define PACKET_TYPE1 1
210#define PACKET_TYPE2 2
211#define PACKET_TYPE3 3
212
213#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
214#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
215#define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)
216#define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)
217#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
218
219/* Registers */ 208/* Registers */
220#define R_0000F0_RBBM_SOFT_RESET 0x0000F0 209#define R_0000F0_RBBM_SOFT_RESET 0x0000F0
221#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0) 210#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index ae8b48205a6c..719f03e061db 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -38,6 +38,7 @@
38#define SI_CE_UCODE_SIZE 2144 38#define SI_CE_UCODE_SIZE 2144
39#define SI_RLC_UCODE_SIZE 2048 39#define SI_RLC_UCODE_SIZE 2048
40#define SI_MC_UCODE_SIZE 7769 40#define SI_MC_UCODE_SIZE 7769
41#define OLAND_MC_UCODE_SIZE 7863
41 42
42MODULE_FIRMWARE("radeon/TAHITI_pfp.bin"); 43MODULE_FIRMWARE("radeon/TAHITI_pfp.bin");
43MODULE_FIRMWARE("radeon/TAHITI_me.bin"); 44MODULE_FIRMWARE("radeon/TAHITI_me.bin");
@@ -54,6 +55,11 @@ MODULE_FIRMWARE("radeon/VERDE_me.bin");
54MODULE_FIRMWARE("radeon/VERDE_ce.bin"); 55MODULE_FIRMWARE("radeon/VERDE_ce.bin");
55MODULE_FIRMWARE("radeon/VERDE_mc.bin"); 56MODULE_FIRMWARE("radeon/VERDE_mc.bin");
56MODULE_FIRMWARE("radeon/VERDE_rlc.bin"); 57MODULE_FIRMWARE("radeon/VERDE_rlc.bin");
58MODULE_FIRMWARE("radeon/OLAND_pfp.bin");
59MODULE_FIRMWARE("radeon/OLAND_me.bin");
60MODULE_FIRMWARE("radeon/OLAND_ce.bin");
61MODULE_FIRMWARE("radeon/OLAND_mc.bin");
62MODULE_FIRMWARE("radeon/OLAND_rlc.bin");
57 63
58extern int r600_ih_ring_alloc(struct radeon_device *rdev); 64extern int r600_ih_ring_alloc(struct radeon_device *rdev);
59extern void r600_ih_ring_fini(struct radeon_device *rdev); 65extern void r600_ih_ring_fini(struct radeon_device *rdev);
@@ -61,6 +67,8 @@ extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
61extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save); 67extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
62extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save); 68extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
63extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev); 69extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
70extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
71extern bool evergreen_is_display_hung(struct radeon_device *rdev);
64 72
65/* get temperature in millidegrees */ 73/* get temperature in millidegrees */
66int si_get_temp(struct radeon_device *rdev) 74int si_get_temp(struct radeon_device *rdev)
@@ -200,6 +208,45 @@ static const u32 verde_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
200 {0x0000009f, 0x00a37400} 208 {0x0000009f, 0x00a37400}
201}; 209};
202 210
211static const u32 oland_io_mc_regs[TAHITI_IO_MC_REGS_SIZE][2] = {
212 {0x0000006f, 0x03044000},
213 {0x00000070, 0x0480c018},
214 {0x00000071, 0x00000040},
215 {0x00000072, 0x01000000},
216 {0x00000074, 0x000000ff},
217 {0x00000075, 0x00143400},
218 {0x00000076, 0x08ec0800},
219 {0x00000077, 0x040000cc},
220 {0x00000079, 0x00000000},
221 {0x0000007a, 0x21000409},
222 {0x0000007c, 0x00000000},
223 {0x0000007d, 0xe8000000},
224 {0x0000007e, 0x044408a8},
225 {0x0000007f, 0x00000003},
226 {0x00000080, 0x00000000},
227 {0x00000081, 0x01000000},
228 {0x00000082, 0x02000000},
229 {0x00000083, 0x00000000},
230 {0x00000084, 0xe3f3e4f4},
231 {0x00000085, 0x00052024},
232 {0x00000087, 0x00000000},
233 {0x00000088, 0x66036603},
234 {0x00000089, 0x01000000},
235 {0x0000008b, 0x1c0a0000},
236 {0x0000008c, 0xff010000},
237 {0x0000008e, 0xffffefff},
238 {0x0000008f, 0xfff3efff},
239 {0x00000090, 0xfff3efbf},
240 {0x00000094, 0x00101101},
241 {0x00000095, 0x00000fff},
242 {0x00000096, 0x00116fff},
243 {0x00000097, 0x60010000},
244 {0x00000098, 0x10010000},
245 {0x00000099, 0x00006000},
246 {0x0000009a, 0x00001000},
247 {0x0000009f, 0x00a17730}
248};
249
203/* ucode loading */ 250/* ucode loading */
204static int si_mc_load_microcode(struct radeon_device *rdev) 251static int si_mc_load_microcode(struct radeon_device *rdev)
205{ 252{
@@ -228,6 +275,11 @@ static int si_mc_load_microcode(struct radeon_device *rdev)
228 ucode_size = SI_MC_UCODE_SIZE; 275 ucode_size = SI_MC_UCODE_SIZE;
229 regs_size = TAHITI_IO_MC_REGS_SIZE; 276 regs_size = TAHITI_IO_MC_REGS_SIZE;
230 break; 277 break;
278 case CHIP_OLAND:
279 io_mc_regs = (u32 *)&oland_io_mc_regs;
280 ucode_size = OLAND_MC_UCODE_SIZE;
281 regs_size = TAHITI_IO_MC_REGS_SIZE;
282 break;
231 } 283 }
232 284
233 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; 285 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
@@ -322,6 +374,15 @@ static int si_init_microcode(struct radeon_device *rdev)
322 rlc_req_size = SI_RLC_UCODE_SIZE * 4; 374 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
323 mc_req_size = SI_MC_UCODE_SIZE * 4; 375 mc_req_size = SI_MC_UCODE_SIZE * 4;
324 break; 376 break;
377 case CHIP_OLAND:
378 chip_name = "OLAND";
379 rlc_chip_name = "OLAND";
380 pfp_req_size = SI_PFP_UCODE_SIZE * 4;
381 me_req_size = SI_PM4_UCODE_SIZE * 4;
382 ce_req_size = SI_CE_UCODE_SIZE * 4;
383 rlc_req_size = SI_RLC_UCODE_SIZE * 4;
384 mc_req_size = OLAND_MC_UCODE_SIZE * 4;
385 break;
325 default: BUG(); 386 default: BUG();
326 } 387 }
327 388
@@ -1125,7 +1186,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
1125 } 1186 }
1126 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); 1187 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1127 } 1188 }
1128 } else if (rdev->family == CHIP_VERDE) { 1189 } else if ((rdev->family == CHIP_VERDE) ||
1190 (rdev->family == CHIP_OLAND)) {
1129 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { 1191 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1130 switch (reg_offset) { 1192 switch (reg_offset) {
1131 case 0: /* non-AA compressed depth or any compressed stencil */ 1193 case 0: /* non-AA compressed depth or any compressed stencil */
@@ -1570,6 +1632,23 @@ static void si_gpu_init(struct radeon_device *rdev)
1570 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; 1632 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1571 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN; 1633 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1572 break; 1634 break;
1635 case CHIP_OLAND:
1636 rdev->config.si.max_shader_engines = 1;
1637 rdev->config.si.max_tile_pipes = 4;
1638 rdev->config.si.max_cu_per_sh = 6;
1639 rdev->config.si.max_sh_per_se = 1;
1640 rdev->config.si.max_backends_per_se = 2;
1641 rdev->config.si.max_texture_channel_caches = 4;
1642 rdev->config.si.max_gprs = 256;
1643 rdev->config.si.max_gs_threads = 16;
1644 rdev->config.si.max_hw_contexts = 8;
1645
1646 rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
1647 rdev->config.si.sc_prim_fifo_size_backend = 0x40;
1648 rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
1649 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
1650 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1651 break;
1573 } 1652 }
1574 1653
1575 /* Initialize HDP */ 1654 /* Initialize HDP */
@@ -2106,154 +2185,275 @@ static int si_cp_resume(struct radeon_device *rdev)
2106 return 0; 2185 return 0;
2107} 2186}
2108 2187
2109bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) 2188static u32 si_gpu_check_soft_reset(struct radeon_device *rdev)
2110{ 2189{
2111 u32 srbm_status; 2190 u32 reset_mask = 0;
2112 u32 grbm_status, grbm_status2; 2191 u32 tmp;
2113 u32 grbm_status_se0, grbm_status_se1;
2114
2115 srbm_status = RREG32(SRBM_STATUS);
2116 grbm_status = RREG32(GRBM_STATUS);
2117 grbm_status2 = RREG32(GRBM_STATUS2);
2118 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2119 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2120 if (!(grbm_status & GUI_ACTIVE)) {
2121 radeon_ring_lockup_update(ring);
2122 return false;
2123 }
2124 /* force CP activities */
2125 radeon_ring_force_activity(rdev, ring);
2126 return radeon_ring_test_lockup(rdev, ring);
2127}
2128 2192
2129static void si_gpu_soft_reset_gfx(struct radeon_device *rdev) 2193 /* GRBM_STATUS */
2130{ 2194 tmp = RREG32(GRBM_STATUS);
2131 u32 grbm_reset = 0; 2195 if (tmp & (PA_BUSY | SC_BUSY |
2196 BCI_BUSY | SX_BUSY |
2197 TA_BUSY | VGT_BUSY |
2198 DB_BUSY | CB_BUSY |
2199 GDS_BUSY | SPI_BUSY |
2200 IA_BUSY | IA_BUSY_NO_DMA))
2201 reset_mask |= RADEON_RESET_GFX;
2132 2202
2133 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2203 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
2134 return; 2204 CP_BUSY | CP_COHERENCY_BUSY))
2205 reset_mask |= RADEON_RESET_CP;
2135 2206
2136 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", 2207 if (tmp & GRBM_EE_BUSY)
2137 RREG32(GRBM_STATUS)); 2208 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
2138 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2139 RREG32(GRBM_STATUS2));
2140 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2141 RREG32(GRBM_STATUS_SE0));
2142 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2143 RREG32(GRBM_STATUS_SE1));
2144 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2145 RREG32(SRBM_STATUS));
2146 2209
2147 /* Disable CP parsing/prefetching */ 2210 /* GRBM_STATUS2 */
2148 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); 2211 tmp = RREG32(GRBM_STATUS2);
2212 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
2213 reset_mask |= RADEON_RESET_RLC;
2149 2214
2150 /* reset all the gfx blocks */ 2215 /* DMA_STATUS_REG 0 */
2151 grbm_reset = (SOFT_RESET_CP | 2216 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
2152 SOFT_RESET_CB | 2217 if (!(tmp & DMA_IDLE))
2153 SOFT_RESET_DB | 2218 reset_mask |= RADEON_RESET_DMA;
2154 SOFT_RESET_GDS |
2155 SOFT_RESET_PA |
2156 SOFT_RESET_SC |
2157 SOFT_RESET_BCI |
2158 SOFT_RESET_SPI |
2159 SOFT_RESET_SX |
2160 SOFT_RESET_TC |
2161 SOFT_RESET_TA |
2162 SOFT_RESET_VGT |
2163 SOFT_RESET_IA);
2164
2165 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2166 WREG32(GRBM_SOFT_RESET, grbm_reset);
2167 (void)RREG32(GRBM_SOFT_RESET);
2168 udelay(50);
2169 WREG32(GRBM_SOFT_RESET, 0);
2170 (void)RREG32(GRBM_SOFT_RESET);
2171
2172 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2173 RREG32(GRBM_STATUS));
2174 dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
2175 RREG32(GRBM_STATUS2));
2176 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2177 RREG32(GRBM_STATUS_SE0));
2178 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2179 RREG32(GRBM_STATUS_SE1));
2180 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2181 RREG32(SRBM_STATUS));
2182}
2183 2219
2184static void si_gpu_soft_reset_dma(struct radeon_device *rdev) 2220 /* DMA_STATUS_REG 1 */
2185{ 2221 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
2186 u32 tmp; 2222 if (!(tmp & DMA_IDLE))
2223 reset_mask |= RADEON_RESET_DMA1;
2187 2224
2188 if (RREG32(DMA_STATUS_REG) & DMA_IDLE) 2225 /* SRBM_STATUS2 */
2189 return; 2226 tmp = RREG32(SRBM_STATUS2);
2227 if (tmp & DMA_BUSY)
2228 reset_mask |= RADEON_RESET_DMA;
2190 2229
2191 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2230 if (tmp & DMA1_BUSY)
2192 RREG32(DMA_STATUS_REG)); 2231 reset_mask |= RADEON_RESET_DMA1;
2193 2232
2194 /* dma0 */ 2233 /* SRBM_STATUS */
2195 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); 2234 tmp = RREG32(SRBM_STATUS);
2196 tmp &= ~DMA_RB_ENABLE;
2197 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
2198 2235
2199 /* dma1 */ 2236 if (tmp & IH_BUSY)
2200 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); 2237 reset_mask |= RADEON_RESET_IH;
2201 tmp &= ~DMA_RB_ENABLE;
2202 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2203 2238
2204 /* Reset dma */ 2239 if (tmp & SEM_BUSY)
2205 WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA | SOFT_RESET_DMA1); 2240 reset_mask |= RADEON_RESET_SEM;
2206 RREG32(SRBM_SOFT_RESET); 2241
2207 udelay(50); 2242 if (tmp & GRBM_RQ_PENDING)
2208 WREG32(SRBM_SOFT_RESET, 0); 2243 reset_mask |= RADEON_RESET_GRBM;
2244
2245 if (tmp & VMC_BUSY)
2246 reset_mask |= RADEON_RESET_VMC;
2247
2248 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
2249 MCC_BUSY | MCD_BUSY))
2250 reset_mask |= RADEON_RESET_MC;
2209 2251
2210 dev_info(rdev->dev, " DMA_STATUS_REG = 0x%08X\n", 2252 if (evergreen_is_display_hung(rdev))
2211 RREG32(DMA_STATUS_REG)); 2253 reset_mask |= RADEON_RESET_DISPLAY;
2254
2255 /* VM_L2_STATUS */
2256 tmp = RREG32(VM_L2_STATUS);
2257 if (tmp & L2_BUSY)
2258 reset_mask |= RADEON_RESET_VMC;
2259
2260 return reset_mask;
2212} 2261}
2213 2262
2214static int si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) 2263static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2215{ 2264{
2216 struct evergreen_mc_save save; 2265 struct evergreen_mc_save save;
2217 2266 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
2218 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE)) 2267 u32 tmp;
2219 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
2220
2221 if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2222 reset_mask &= ~RADEON_RESET_DMA;
2223 2268
2224 if (reset_mask == 0) 2269 if (reset_mask == 0)
2225 return 0; 2270 return;
2226 2271
2227 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); 2272 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2228 2273
2274 evergreen_print_gpu_status_regs(rdev);
2229 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 2275 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
2230 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); 2276 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
2231 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 2277 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
2232 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); 2278 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
2233 2279
2280 /* Disable CP parsing/prefetching */
2281 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2282
2283 if (reset_mask & RADEON_RESET_DMA) {
2284 /* dma0 */
2285 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
2286 tmp &= ~DMA_RB_ENABLE;
2287 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
2288 }
2289 if (reset_mask & RADEON_RESET_DMA1) {
2290 /* dma1 */
2291 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
2292 tmp &= ~DMA_RB_ENABLE;
2293 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
2294 }
2295
2296 udelay(50);
2297
2234 evergreen_mc_stop(rdev, &save); 2298 evergreen_mc_stop(rdev, &save);
2235 if (radeon_mc_wait_for_idle(rdev)) { 2299 if (evergreen_mc_wait_for_idle(rdev)) {
2236 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); 2300 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2237 } 2301 }
2238 2302
2239 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) 2303 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
2240 si_gpu_soft_reset_gfx(rdev); 2304 grbm_soft_reset = SOFT_RESET_CB |
2305 SOFT_RESET_DB |
2306 SOFT_RESET_GDS |
2307 SOFT_RESET_PA |
2308 SOFT_RESET_SC |
2309 SOFT_RESET_BCI |
2310 SOFT_RESET_SPI |
2311 SOFT_RESET_SX |
2312 SOFT_RESET_TC |
2313 SOFT_RESET_TA |
2314 SOFT_RESET_VGT |
2315 SOFT_RESET_IA;
2316 }
2317
2318 if (reset_mask & RADEON_RESET_CP) {
2319 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
2320
2321 srbm_soft_reset |= SOFT_RESET_GRBM;
2322 }
2241 2323
2242 if (reset_mask & RADEON_RESET_DMA) 2324 if (reset_mask & RADEON_RESET_DMA)
2243 si_gpu_soft_reset_dma(rdev); 2325 srbm_soft_reset |= SOFT_RESET_DMA;
2326
2327 if (reset_mask & RADEON_RESET_DMA1)
2328 srbm_soft_reset |= SOFT_RESET_DMA1;
2329
2330 if (reset_mask & RADEON_RESET_DISPLAY)
2331 srbm_soft_reset |= SOFT_RESET_DC;
2332
2333 if (reset_mask & RADEON_RESET_RLC)
2334 grbm_soft_reset |= SOFT_RESET_RLC;
2335
2336 if (reset_mask & RADEON_RESET_SEM)
2337 srbm_soft_reset |= SOFT_RESET_SEM;
2338
2339 if (reset_mask & RADEON_RESET_IH)
2340 srbm_soft_reset |= SOFT_RESET_IH;
2341
2342 if (reset_mask & RADEON_RESET_GRBM)
2343 srbm_soft_reset |= SOFT_RESET_GRBM;
2344
2345 if (reset_mask & RADEON_RESET_VMC)
2346 srbm_soft_reset |= SOFT_RESET_VMC;
2347
2348 if (reset_mask & RADEON_RESET_MC)
2349 srbm_soft_reset |= SOFT_RESET_MC;
2350
2351 if (grbm_soft_reset) {
2352 tmp = RREG32(GRBM_SOFT_RESET);
2353 tmp |= grbm_soft_reset;
2354 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
2355 WREG32(GRBM_SOFT_RESET, tmp);
2356 tmp = RREG32(GRBM_SOFT_RESET);
2357
2358 udelay(50);
2359
2360 tmp &= ~grbm_soft_reset;
2361 WREG32(GRBM_SOFT_RESET, tmp);
2362 tmp = RREG32(GRBM_SOFT_RESET);
2363 }
2364
2365 if (srbm_soft_reset) {
2366 tmp = RREG32(SRBM_SOFT_RESET);
2367 tmp |= srbm_soft_reset;
2368 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2369 WREG32(SRBM_SOFT_RESET, tmp);
2370 tmp = RREG32(SRBM_SOFT_RESET);
2371
2372 udelay(50);
2373
2374 tmp &= ~srbm_soft_reset;
2375 WREG32(SRBM_SOFT_RESET, tmp);
2376 tmp = RREG32(SRBM_SOFT_RESET);
2377 }
2244 2378
2245 /* Wait a little for things to settle down */ 2379 /* Wait a little for things to settle down */
2246 udelay(50); 2380 udelay(50);
2247 2381
2248 evergreen_mc_resume(rdev, &save); 2382 evergreen_mc_resume(rdev, &save);
2249 return 0; 2383 udelay(50);
2384
2385 evergreen_print_gpu_status_regs(rdev);
2250} 2386}
2251 2387
2252int si_asic_reset(struct radeon_device *rdev) 2388int si_asic_reset(struct radeon_device *rdev)
2253{ 2389{
2254 return si_gpu_soft_reset(rdev, (RADEON_RESET_GFX | 2390 u32 reset_mask;
2255 RADEON_RESET_COMPUTE | 2391
2256 RADEON_RESET_DMA)); 2392 reset_mask = si_gpu_check_soft_reset(rdev);
2393
2394 if (reset_mask)
2395 r600_set_bios_scratch_engine_hung(rdev, true);
2396
2397 si_gpu_soft_reset(rdev, reset_mask);
2398
2399 reset_mask = si_gpu_check_soft_reset(rdev);
2400
2401 if (!reset_mask)
2402 r600_set_bios_scratch_engine_hung(rdev, false);
2403
2404 return 0;
2405}
2406
2407/**
2408 * si_gfx_is_lockup - Check if the GFX engine is locked up
2409 *
2410 * @rdev: radeon_device pointer
2411 * @ring: radeon_ring structure holding ring information
2412 *
2413 * Check if the GFX engine is locked up.
2414 * Returns true if the engine appears to be locked up, false if not.
2415 */
2416bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2417{
2418 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2419
2420 if (!(reset_mask & (RADEON_RESET_GFX |
2421 RADEON_RESET_COMPUTE |
2422 RADEON_RESET_CP))) {
2423 radeon_ring_lockup_update(ring);
2424 return false;
2425 }
2426 /* force CP activities */
2427 radeon_ring_force_activity(rdev, ring);
2428 return radeon_ring_test_lockup(rdev, ring);
2429}
2430
2431/**
2432 * si_dma_is_lockup - Check if the DMA engine is locked up
2433 *
2434 * @rdev: radeon_device pointer
2435 * @ring: radeon_ring structure holding ring information
2436 *
2437 * Check if the async DMA engine is locked up.
2438 * Returns true if the engine appears to be locked up, false if not.
2439 */
2440bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2441{
2442 u32 reset_mask = si_gpu_check_soft_reset(rdev);
2443 u32 mask;
2444
2445 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
2446 mask = RADEON_RESET_DMA;
2447 else
2448 mask = RADEON_RESET_DMA1;
2449
2450 if (!(reset_mask & mask)) {
2451 radeon_ring_lockup_update(ring);
2452 return false;
2453 }
2454 /* force ring activities */
2455 radeon_ring_force_activity(rdev, ring);
2456 return radeon_ring_test_lockup(rdev, ring);
2257} 2457}
2258 2458
2259/* MC */ 2459/* MC */
@@ -2855,19 +3055,19 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2855 3055
2856 do { 3056 do {
2857 pkt.idx = idx; 3057 pkt.idx = idx;
2858 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 3058 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]);
2859 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 3059 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]);
2860 pkt.one_reg_wr = 0; 3060 pkt.one_reg_wr = 0;
2861 switch (pkt.type) { 3061 switch (pkt.type) {
2862 case PACKET_TYPE0: 3062 case RADEON_PACKET_TYPE0:
2863 dev_err(rdev->dev, "Packet0 not allowed!\n"); 3063 dev_err(rdev->dev, "Packet0 not allowed!\n");
2864 ret = -EINVAL; 3064 ret = -EINVAL;
2865 break; 3065 break;
2866 case PACKET_TYPE2: 3066 case RADEON_PACKET_TYPE2:
2867 idx += 1; 3067 idx += 1;
2868 break; 3068 break;
2869 case PACKET_TYPE3: 3069 case RADEON_PACKET_TYPE3:
2870 pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 3070 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2871 if (ib->is_const_ib) 3071 if (ib->is_const_ib)
2872 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); 3072 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt);
2873 else { 3073 else {
@@ -2920,19 +3120,21 @@ void si_vm_fini(struct radeon_device *rdev)
2920 * si_vm_set_page - update the page tables using the CP 3120 * si_vm_set_page - update the page tables using the CP
2921 * 3121 *
2922 * @rdev: radeon_device pointer 3122 * @rdev: radeon_device pointer
3123 * @ib: indirect buffer to fill with commands
2923 * @pe: addr of the page entry 3124 * @pe: addr of the page entry
2924 * @addr: dst addr to write into pe 3125 * @addr: dst addr to write into pe
2925 * @count: number of page entries to update 3126 * @count: number of page entries to update
2926 * @incr: increase next addr by incr bytes 3127 * @incr: increase next addr by incr bytes
2927 * @flags: access flags 3128 * @flags: access flags
2928 * 3129 *
2929 * Update the page tables using the CP (cayman-si). 3130 * Update the page tables using the CP (SI).
2930 */ 3131 */
2931void si_vm_set_page(struct radeon_device *rdev, uint64_t pe, 3132void si_vm_set_page(struct radeon_device *rdev,
3133 struct radeon_ib *ib,
3134 uint64_t pe,
2932 uint64_t addr, unsigned count, 3135 uint64_t addr, unsigned count,
2933 uint32_t incr, uint32_t flags) 3136 uint32_t incr, uint32_t flags)
2934{ 3137{
2935 struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
2936 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags); 3138 uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
2937 uint64_t value; 3139 uint64_t value;
2938 unsigned ndw; 3140 unsigned ndw;
@@ -2943,11 +3145,11 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
2943 if (ndw > 0x3FFE) 3145 if (ndw > 0x3FFE)
2944 ndw = 0x3FFE; 3146 ndw = 0x3FFE;
2945 3147
2946 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, ndw)); 3148 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_WRITE_DATA, ndw);
2947 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 3149 ib->ptr[ib->length_dw++] = (WRITE_DATA_ENGINE_SEL(0) |
2948 WRITE_DATA_DST_SEL(1))); 3150 WRITE_DATA_DST_SEL(1));
2949 radeon_ring_write(ring, pe); 3151 ib->ptr[ib->length_dw++] = pe;
2950 radeon_ring_write(ring, upper_32_bits(pe)); 3152 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
2951 for (; ndw > 2; ndw -= 2, --count, pe += 8) { 3153 for (; ndw > 2; ndw -= 2, --count, pe += 8) {
2952 if (flags & RADEON_VM_PAGE_SYSTEM) { 3154 if (flags & RADEON_VM_PAGE_SYSTEM) {
2953 value = radeon_vm_map_gart(rdev, addr); 3155 value = radeon_vm_map_gart(rdev, addr);
@@ -2959,8 +3161,8 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
2959 } 3161 }
2960 addr += incr; 3162 addr += incr;
2961 value |= r600_flags; 3163 value |= r600_flags;
2962 radeon_ring_write(ring, value); 3164 ib->ptr[ib->length_dw++] = value;
2963 radeon_ring_write(ring, upper_32_bits(value)); 3165 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2964 } 3166 }
2965 } 3167 }
2966 } else { 3168 } else {
@@ -2972,9 +3174,9 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
2972 ndw = 0xFFFFE; 3174 ndw = 0xFFFFE;
2973 3175
2974 /* for non-physically contiguous pages (system) */ 3176 /* for non-physically contiguous pages (system) */
2975 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw)); 3177 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 0, ndw);
2976 radeon_ring_write(ring, pe); 3178 ib->ptr[ib->length_dw++] = pe;
2977 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3179 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
2978 for (; ndw > 0; ndw -= 2, --count, pe += 8) { 3180 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
2979 if (flags & RADEON_VM_PAGE_SYSTEM) { 3181 if (flags & RADEON_VM_PAGE_SYSTEM) {
2980 value = radeon_vm_map_gart(rdev, addr); 3182 value = radeon_vm_map_gart(rdev, addr);
@@ -2986,8 +3188,8 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
2986 } 3188 }
2987 addr += incr; 3189 addr += incr;
2988 value |= r600_flags; 3190 value |= r600_flags;
2989 radeon_ring_write(ring, value); 3191 ib->ptr[ib->length_dw++] = value;
2990 radeon_ring_write(ring, upper_32_bits(value)); 3192 ib->ptr[ib->length_dw++] = upper_32_bits(value);
2991 } 3193 }
2992 } 3194 }
2993 } else { 3195 } else {
@@ -3001,20 +3203,22 @@ void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
3001 else 3203 else
3002 value = 0; 3204 value = 0;
3003 /* for physically contiguous pages (vram) */ 3205 /* for physically contiguous pages (vram) */
3004 radeon_ring_write(ring, DMA_PTE_PDE_PACKET(ndw)); 3206 ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
3005 radeon_ring_write(ring, pe); /* dst addr */ 3207 ib->ptr[ib->length_dw++] = pe; /* dst addr */
3006 radeon_ring_write(ring, upper_32_bits(pe) & 0xff); 3208 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
3007 radeon_ring_write(ring, r600_flags); /* mask */ 3209 ib->ptr[ib->length_dw++] = r600_flags; /* mask */
3008 radeon_ring_write(ring, 0); 3210 ib->ptr[ib->length_dw++] = 0;
3009 radeon_ring_write(ring, value); /* value */ 3211 ib->ptr[ib->length_dw++] = value; /* value */
3010 radeon_ring_write(ring, upper_32_bits(value)); 3212 ib->ptr[ib->length_dw++] = upper_32_bits(value);
3011 radeon_ring_write(ring, incr); /* increment size */ 3213 ib->ptr[ib->length_dw++] = incr; /* increment size */
3012 radeon_ring_write(ring, 0); 3214 ib->ptr[ib->length_dw++] = 0;
3013 pe += ndw * 4; 3215 pe += ndw * 4;
3014 addr += (ndw / 2) * incr; 3216 addr += (ndw / 2) * incr;
3015 count -= ndw / 2; 3217 count -= ndw / 2;
3016 } 3218 }
3017 } 3219 }
3220 while (ib->length_dw & 0x7)
3221 ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0);
3018 } 3222 }
3019} 3223}
3020 3224
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index c056aae814f0..07fc455e35ae 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -61,6 +61,14 @@
61#define DMIF_ADDR_CONFIG 0xBD4 61#define DMIF_ADDR_CONFIG 0xBD4
62 62
63#define SRBM_STATUS 0xE50 63#define SRBM_STATUS 0xE50
64#define GRBM_RQ_PENDING (1 << 5)
65#define VMC_BUSY (1 << 8)
66#define MCB_BUSY (1 << 9)
67#define MCB_NON_DISPLAY_BUSY (1 << 10)
68#define MCC_BUSY (1 << 11)
69#define MCD_BUSY (1 << 12)
70#define SEM_BUSY (1 << 14)
71#define IH_BUSY (1 << 17)
64 72
65#define SRBM_SOFT_RESET 0x0E60 73#define SRBM_SOFT_RESET 0x0E60
66#define SOFT_RESET_BIF (1 << 1) 74#define SOFT_RESET_BIF (1 << 1)
@@ -81,6 +89,10 @@
81#define CC_SYS_RB_BACKEND_DISABLE 0xe80 89#define CC_SYS_RB_BACKEND_DISABLE 0xe80
82#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 90#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
83 91
92#define SRBM_STATUS2 0x0EC4
93#define DMA_BUSY (1 << 5)
94#define DMA1_BUSY (1 << 6)
95
84#define VM_L2_CNTL 0x1400 96#define VM_L2_CNTL 0x1400
85#define ENABLE_L2_CACHE (1 << 0) 97#define ENABLE_L2_CACHE (1 << 0)
86#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 98#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
@@ -783,16 +795,7 @@
783/* 795/*
784 * PM4 796 * PM4
785 */ 797 */
786#define PACKET_TYPE0 0 798#define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \
787#define PACKET_TYPE1 1
788#define PACKET_TYPE2 2
789#define PACKET_TYPE3 3
790
791#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
792#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
793#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
794#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
795#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
796 (((reg) >> 2) & 0xFFFF) | \ 799 (((reg) >> 2) & 0xFFFF) | \
797 ((n) & 0x3FFF) << 16) 800 ((n) & 0x3FFF) << 16)
798#define CP_PACKET2 0x80000000 801#define CP_PACKET2 0x80000000
@@ -801,7 +804,7 @@
801 804
802#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 805#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
803 806
804#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 807#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
805 (((op) & 0xFF) << 8) | \ 808 (((op) & 0xFF) << 8) | \
806 ((n) & 0x3FFF) << 16) 809 ((n) & 0x3FFF) << 16)
807 810
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index c5c35e629426..a386b0b654cc 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -139,6 +139,19 @@
139 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 139 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
140 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 140 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
141 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 141 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
142 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
143 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
147 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
148 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
149 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
150 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
151 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
152 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
153 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
154 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|RADEON_NEW_MEMMAP}, \
142 {0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 155 {0x1002, 0x6700, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
143 {0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 156 {0x1002, 0x6701, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 157 {0x1002, 0x6702, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-14 14:34:05 -0400