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-rw-r--r--arch/arm/Kconfig10
-rw-r--r--arch/arm/mm/cache-v7.S3
2 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d97701..48c19d44be9a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1413,6 +1413,16 @@ config PL310_ERRATA_769419
1413 on systems with an outer cache, the store buffer is drained 1413 on systems with an outer cache, the store buffer is drained
1414 explicitly. 1414 explicitly.
1415 1415
1416config ARM_ERRATA_775420
1417 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1418 depends on CPU_V7
1419 help
1420 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1421 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1422 operation aborts with MMU exception, it might cause the processor
1423 to deadlock. This workaround puts DSB before executing ISB if
1424 an abort may occur on cache maintenance.
1425
1416endmenu 1426endmenu
1417 1427
1418source "arch/arm/common/Kconfig" 1428source "arch/arm/common/Kconfig"
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 39e3fb3db801..3b172275262e 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -211,6 +211,9 @@ ENTRY(v7_coherent_user_range)
211 * isn't mapped, fail with -EFAULT. 211 * isn't mapped, fail with -EFAULT.
212 */ 212 */
2139001: 2139001:
214#ifdef CONFIG_ARM_ERRATA_775420
215 dsb
216#endif
214 mov r0, #-EFAULT 217 mov r0, #-EFAULT
215 mov pc, lr 218 mov pc, lr
216 UNWIND(.fnend ) 219 UNWIND(.fnend )