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-rw-r--r--arch/arm/mach-omap2/cm2_7xx.h4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c57
-rw-r--r--arch/arm/mach-omap2/prm7xx.h4
3 files changed, 65 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594e7622..e966e3a3c931 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) 357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
360#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
361#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
362#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
363#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
360#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 364#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
361#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 365#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
362#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 366#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index c9daee46d980..b21647d7532c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1231,6 +1231,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1231}; 1231};
1232 1232
1233/* 1233/*
1234 * 'PCIE PHY' class
1235 *
1236 */
1237
1238static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
1239 .name = "pcie-phy",
1240};
1241
1242/* pcie1 phy */
1243static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
1244 .name = "pcie1-phy",
1245 .class = &dra7xx_pcie_phy_hwmod_class,
1246 .clkdm_name = "l3init_clkdm",
1247 .main_clk = "l4_root_clk_div",
1248 .prcm = {
1249 .omap4 = {
1250 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1252 .modulemode = MODULEMODE_SWCTRL,
1253 },
1254 },
1255};
1256
1257/* pcie2 phy */
1258static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
1259 .name = "pcie2-phy",
1260 .class = &dra7xx_pcie_phy_hwmod_class,
1261 .clkdm_name = "l3init_clkdm",
1262 .main_clk = "l4_root_clk_div",
1263 .prcm = {
1264 .omap4 = {
1265 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1266 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1267 .modulemode = MODULEMODE_SWCTRL,
1268 },
1269 },
1270};
1271
1272/*
1234 * 'qspi' class 1273 * 'qspi' class
1235 * 1274 *
1236 */ 1275 */
@@ -2349,6 +2388,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2349 .user = OCP_USER_MPU | OCP_USER_SDMA, 2388 .user = OCP_USER_MPU | OCP_USER_SDMA,
2350}; 2389};
2351 2390
2391/* l4_cfg -> pcie1 phy */
2392static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
2393 .master = &dra7xx_l4_cfg_hwmod,
2394 .slave = &dra7xx_pcie1_phy_hwmod,
2395 .clk = "l4_root_clk_div",
2396 .user = OCP_USER_MPU | OCP_USER_SDMA,
2397};
2398
2399/* l4_cfg -> pcie2 phy */
2400static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
2401 .master = &dra7xx_l4_cfg_hwmod,
2402 .slave = &dra7xx_pcie2_phy_hwmod,
2403 .clk = "l4_root_clk_div",
2404 .user = OCP_USER_MPU | OCP_USER_SDMA,
2405};
2406
2352static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { 2407static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2353 { 2408 {
2354 .pa_start = 0x4b300000, 2409 .pa_start = 0x4b300000,
@@ -2696,6 +2751,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2696 &dra7xx_l4_cfg__mpu, 2751 &dra7xx_l4_cfg__mpu,
2697 &dra7xx_l4_cfg__ocp2scp1, 2752 &dra7xx_l4_cfg__ocp2scp1,
2698 &dra7xx_l4_cfg__ocp2scp3, 2753 &dra7xx_l4_cfg__ocp2scp3,
2754 &dra7xx_l4_cfg__pcie1_phy,
2755 &dra7xx_l4_cfg__pcie2_phy,
2699 &dra7xx_l3_main_1__qspi, 2756 &dra7xx_l3_main_1__qspi,
2700 &dra7xx_l4_cfg__sata, 2757 &dra7xx_l4_cfg__sata,
2701 &dra7xx_l4_cfg__smartreflex_core, 2758 &dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a8404edc7..4bb50fbf29be 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c 374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c 376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
377#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
378#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4
379#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8
380#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc
377#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 381#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
378#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 382#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
379#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec 383#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec