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-rw-r--r--drivers/video/s3fb.c31
1 files changed, 21 insertions, 10 deletions
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c
index 2c80246b18b8..1d007366b917 100644
--- a/drivers/video/s3fb.c
+++ b/drivers/video/s3fb.c
@@ -84,7 +84,7 @@ static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64",
84 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX", 84 "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
85 "S3 Virge/GX2", "S3 Virge/GX2+", "", 85 "S3 Virge/GX2", "S3 Virge/GX2+", "",
86 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X", 86 "S3 Trio3D/1X", "S3 Trio3D/2X", "S3 Trio3D/2X",
87 "S3 Trio3D"}; 87 "S3 Trio3D", "S3 Virge/MX"};
88 88
89#define CHIP_UNKNOWN 0x00 89#define CHIP_UNKNOWN 0x00
90#define CHIP_732_TRIO32 0x01 90#define CHIP_732_TRIO32 0x01
@@ -105,6 +105,7 @@ static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64",
105#define CHIP_362_TRIO3D_2X 0x11 105#define CHIP_362_TRIO3D_2X 0x11
106#define CHIP_368_TRIO3D_2X 0x12 106#define CHIP_368_TRIO3D_2X 0x12
107#define CHIP_365_TRIO3D 0x13 107#define CHIP_365_TRIO3D 0x13
108#define CHIP_260_VIRGE_MX 0x14
108 109
109#define CHIP_XXX_TRIO 0x80 110#define CHIP_XXX_TRIO 0x80
110#define CHIP_XXX_TRIO64V2_DXGX 0x81 111#define CHIP_XXX_TRIO64V2_DXGX 0x81
@@ -280,7 +281,8 @@ static int __devinit s3fb_setup_ddc_bus(struct fb_info *info)
280 */ 281 */
281/* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */ 282/* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
282 if (par->chip == CHIP_357_VIRGE_GX2 || 283 if (par->chip == CHIP_357_VIRGE_GX2 ||
283 par->chip == CHIP_359_VIRGE_GX2P) 284 par->chip == CHIP_359_VIRGE_GX2P ||
285 par->chip == CHIP_260_VIRGE_MX)
284 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03); 286 svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
285 else 287 else
286 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03); 288 svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
@@ -487,7 +489,8 @@ static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
487 par->chip == CHIP_359_VIRGE_GX2P || 489 par->chip == CHIP_359_VIRGE_GX2P ||
488 par->chip == CHIP_360_TRIO3D_1X || 490 par->chip == CHIP_360_TRIO3D_1X ||
489 par->chip == CHIP_362_TRIO3D_2X || 491 par->chip == CHIP_362_TRIO3D_2X ||
490 par->chip == CHIP_368_TRIO3D_2X) { 492 par->chip == CHIP_368_TRIO3D_2X ||
493 par->chip == CHIP_260_VIRGE_MX) {
491 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */ 494 vga_wseq(par->state.vgabase, 0x12, (n - 2) | ((r & 3) << 6)); /* n and two bits of r */
492 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */ 495 vga_wseq(par->state.vgabase, 0x29, r >> 2); /* remaining highest bit of r */
493 } else 496 } else
@@ -690,7 +693,8 @@ static int s3fb_set_par(struct fb_info *info)
690 par->chip != CHIP_359_VIRGE_GX2P && 693 par->chip != CHIP_359_VIRGE_GX2P &&
691 par->chip != CHIP_360_TRIO3D_1X && 694 par->chip != CHIP_360_TRIO3D_1X &&
692 par->chip != CHIP_362_TRIO3D_2X && 695 par->chip != CHIP_362_TRIO3D_2X &&
693 par->chip != CHIP_368_TRIO3D_2X) { 696 par->chip != CHIP_368_TRIO3D_2X &&
697 par->chip != CHIP_260_VIRGE_MX) {
694 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */ 698 vga_wcrt(par->state.vgabase, 0x54, 0x18); /* M parameter */
695 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */ 699 vga_wcrt(par->state.vgabase, 0x60, 0xff); /* N parameter */
696 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */ 700 vga_wcrt(par->state.vgabase, 0x61, 0xff); /* L parameter */
@@ -739,7 +743,8 @@ static int s3fb_set_par(struct fb_info *info)
739 par->chip == CHIP_368_TRIO3D_2X || 743 par->chip == CHIP_368_TRIO3D_2X ||
740 par->chip == CHIP_365_TRIO3D || 744 par->chip == CHIP_365_TRIO3D ||
741 par->chip == CHIP_375_VIRGE_DX || 745 par->chip == CHIP_375_VIRGE_DX ||
742 par->chip == CHIP_385_VIRGE_GX) { 746 par->chip == CHIP_385_VIRGE_GX ||
747 par->chip == CHIP_260_VIRGE_MX) {
743 dbytes = info->var.xres * ((bpp+7)/8); 748 dbytes = info->var.xres * ((bpp+7)/8);
744 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8); 749 vga_wcrt(par->state.vgabase, 0x91, (dbytes + 7) / 8);
745 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80); 750 vga_wcrt(par->state.vgabase, 0x90, (((dbytes + 7) / 8) >> 8) | 0x80);
@@ -751,7 +756,8 @@ static int s3fb_set_par(struct fb_info *info)
751 par->chip == CHIP_359_VIRGE_GX2P || 756 par->chip == CHIP_359_VIRGE_GX2P ||
752 par->chip == CHIP_360_TRIO3D_1X || 757 par->chip == CHIP_360_TRIO3D_1X ||
753 par->chip == CHIP_362_TRIO3D_2X || 758 par->chip == CHIP_362_TRIO3D_2X ||
754 par->chip == CHIP_368_TRIO3D_2X) 759 par->chip == CHIP_368_TRIO3D_2X ||
760 par->chip == CHIP_260_VIRGE_MX)
755 vga_wcrt(par->state.vgabase, 0x34, 0x00); 761 vga_wcrt(par->state.vgabase, 0x34, 0x00);
756 else /* enable Data Transfer Position Control (DTPC) */ 762 else /* enable Data Transfer Position Control (DTPC) */
757 vga_wcrt(par->state.vgabase, 0x34, 0x10); 763 vga_wcrt(par->state.vgabase, 0x34, 0x10);
@@ -807,7 +813,8 @@ static int s3fb_set_par(struct fb_info *info)
807 par->chip == CHIP_359_VIRGE_GX2P || 813 par->chip == CHIP_359_VIRGE_GX2P ||
808 par->chip == CHIP_360_TRIO3D_1X || 814 par->chip == CHIP_360_TRIO3D_1X ||
809 par->chip == CHIP_362_TRIO3D_2X || 815 par->chip == CHIP_362_TRIO3D_2X ||
810 par->chip == CHIP_368_TRIO3D_2X) 816 par->chip == CHIP_368_TRIO3D_2X ||
817 par->chip == CHIP_260_VIRGE_MX)
811 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0); 818 svga_wcrt_mask(par->state.vgabase, 0x67, 0x00, 0xF0);
812 else { 819 else {
813 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0); 820 svga_wcrt_mask(par->state.vgabase, 0x67, 0x10, 0xF0);
@@ -837,7 +844,8 @@ static int s3fb_set_par(struct fb_info *info)
837 par->chip != CHIP_359_VIRGE_GX2P && 844 par->chip != CHIP_359_VIRGE_GX2P &&
838 par->chip != CHIP_360_TRIO3D_1X && 845 par->chip != CHIP_360_TRIO3D_1X &&
839 par->chip != CHIP_362_TRIO3D_2X && 846 par->chip != CHIP_362_TRIO3D_2X &&
840 par->chip != CHIP_368_TRIO3D_2X) 847 par->chip != CHIP_368_TRIO3D_2X &&
848 par->chip != CHIP_260_VIRGE_MX)
841 hmul = 2; 849 hmul = 2;
842 } 850 }
843 break; 851 break;
@@ -864,7 +872,8 @@ static int s3fb_set_par(struct fb_info *info)
864 par->chip != CHIP_359_VIRGE_GX2P && 872 par->chip != CHIP_359_VIRGE_GX2P &&
865 par->chip != CHIP_360_TRIO3D_1X && 873 par->chip != CHIP_360_TRIO3D_1X &&
866 par->chip != CHIP_362_TRIO3D_2X && 874 par->chip != CHIP_362_TRIO3D_2X &&
867 par->chip != CHIP_368_TRIO3D_2X) 875 par->chip != CHIP_368_TRIO3D_2X &&
876 par->chip != CHIP_260_VIRGE_MX)
868 hmul = 2; 877 hmul = 2;
869 } 878 }
870 break; 879 break;
@@ -1208,7 +1217,8 @@ static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_i
1208 break; 1217 break;
1209 } 1218 }
1210 } else if (par->chip == CHIP_357_VIRGE_GX2 || 1219 } else if (par->chip == CHIP_357_VIRGE_GX2 ||
1211 par->chip == CHIP_359_VIRGE_GX2P) { 1220 par->chip == CHIP_359_VIRGE_GX2P ||
1221 par->chip == CHIP_260_VIRGE_MX) {
1212 switch ((regval & 0xC0) >> 6) { 1222 switch ((regval & 0xC0) >> 6) {
1213 case 1: /* 4MB */ 1223 case 1: /* 4MB */
1214 info->screen_size = 4 << 20; 1224 info->screen_size = 4 << 20;
@@ -1515,6 +1525,7 @@ static struct pci_device_id s3_devices[] __devinitdata = {
1515 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P}, 1525 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
1516 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X}, 1526 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A13), .driver_data = CHIP_36X_TRIO3D_1X_2X},
1517 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D}, 1527 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8904), .driver_data = CHIP_365_TRIO3D},
1528 {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8C01), .driver_data = CHIP_260_VIRGE_MX},
1518 1529
1519 {0, 0, 0, 0, 0, 0, 0} 1530 {0, 0, 0, 0, 0, 0, 0}
1520}; 1531};