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-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/cpu.h1
2 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 3b9768e92e9e..eeb5400ed4ee 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -32,6 +32,9 @@
32#ifndef cpu_has_htw 32#ifndef cpu_has_htw
33#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW) 33#define cpu_has_htw (cpu_data[0].options & MIPS_CPU_HTW)
34#endif 34#endif
35#ifndef cpu_has_rixiex
36#define cpu_has_rixiex (cpu_data[0].options & MIPS_CPU_RIXIEX)
37#endif
35 38
36/* 39/*
37 * For the moment we don't consider R6000 and R8000 so we can assume that 40 * For the moment we don't consider R6000 and R8000 so we can assume that
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index ec6a0f964d6a..7ba2a035ad86 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -366,6 +366,7 @@ enum cpu_type_enum {
366#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */ 366#define MIPS_CPU_SEGMENTS 0x04000000ull /* CPU supports Segmentation Control registers */
367#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */ 367#define MIPS_CPU_EVA 0x80000000ull /* CPU supports Enhanced Virtual Addressing */
368#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */ 368#define MIPS_CPU_HTW 0x100000000ull /* CPU support Hardware Page Table Walker */
369#define MIPS_CPU_RIXIEX 0x200000000ull /* CPU has unique exception codes for {Read, Execute}-Inhibit exceptions */
369 370
370/* 371/*
371 * CPU ASE encodings 372 * CPU ASE encodings