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-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_crtc.c15
-rw-r--r--drivers/gpu/drm/tilcdc/tilcdc_regs.h1
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 4de3fb4246fc..5b68fe59e437 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -310,6 +310,21 @@ static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
310 ((vsw & 0x3f) << 10); 310 ((vsw & 0x3f) << 10);
311 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg); 311 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
312 312
313 /*
314 * be sure to set Bit 10 for the V2 LCDC controller,
315 * otherwise limited to 1024 pixels width, stopping
316 * 1920x1080 being suppoted.
317 */
318 if (priv->rev == 2) {
319 if ((mode->vdisplay - 1) & 0x400) {
320 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
321 LCDC_LPP_B10);
322 } else {
323 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
324 LCDC_LPP_B10);
325 }
326 }
327
313 /* Configure display type: */ 328 /* Configure display type: */
314 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & 329 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
315 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE | 330 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h b/drivers/gpu/drm/tilcdc/tilcdc_regs.h
index 17fd1b45428a..1bf5e2553acc 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_regs.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_regs.h
@@ -80,6 +80,7 @@
80#define LCDC_INVERT_PIXEL_CLOCK BIT(22) 80#define LCDC_INVERT_PIXEL_CLOCK BIT(22)
81#define LCDC_INVERT_HSYNC BIT(21) 81#define LCDC_INVERT_HSYNC BIT(21)
82#define LCDC_INVERT_VSYNC BIT(20) 82#define LCDC_INVERT_VSYNC BIT(20)
83#define LCDC_LPP_B10 BIT(26)
83 84
84/* LCDC Block */ 85/* LCDC Block */
85#define LCDC_PID_REG 0x0 86#define LCDC_PID_REG 0x0