aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/sh/include/asm/dma-register.h36
-rw-r--r--drivers/dma/sh/shdmac.c12
-rw-r--r--include/linux/sh_dma.h24
3 files changed, 38 insertions, 34 deletions
diff --git a/arch/sh/include/asm/dma-register.h b/arch/sh/include/asm/dma-register.h
index 51cd78feacff..c757b47e6b64 100644
--- a/arch/sh/include/asm/dma-register.h
+++ b/arch/sh/include/asm/dma-register.h
@@ -13,17 +13,17 @@
13#ifndef DMA_REGISTER_H 13#ifndef DMA_REGISTER_H
14#define DMA_REGISTER_H 14#define DMA_REGISTER_H
15 15
16/* DMA register */ 16/* DMA registers */
17#define SAR 0x00 17#define SAR 0x00 /* Source Address Register */
18#define DAR 0x04 18#define DAR 0x04 /* Destination Address Register */
19#define TCR 0x08 19#define TCR 0x08 /* Transfer Count Register */
20#define CHCR 0x0C 20#define CHCR 0x0C /* Channel Control Register */
21#define DMAOR 0x40 21#define DMAOR 0x40 /* DMA Operation Register */
22 22
23/* DMAOR definitions */ 23/* DMAOR definitions */
24#define DMAOR_AE 0x00000004 24#define DMAOR_AE 0x00000004 /* Address Error Flag */
25#define DMAOR_NMIF 0x00000002 25#define DMAOR_NMIF 0x00000002
26#define DMAOR_DME 0x00000001 26#define DMAOR_DME 0x00000001 /* DMA Master Enable */
27 27
28/* Definitions for the SuperH DMAC */ 28/* Definitions for the SuperH DMAC */
29#define REQ_L 0x00000000 29#define REQ_L 0x00000000
@@ -34,18 +34,20 @@
34#define ACK_W 0x00020000 34#define ACK_W 0x00020000
35#define ACK_H 0x00000000 35#define ACK_H 0x00000000
36#define ACK_L 0x00010000 36#define ACK_L 0x00010000
37#define DM_INC 0x00004000 37#define DM_INC 0x00004000 /* Destination addresses are incremented */
38#define DM_DEC 0x00008000 38#define DM_DEC 0x00008000 /* Destination addresses are decremented */
39#define DM_FIX 0x0000c000 39#define DM_FIX 0x0000c000 /* Destination address is fixed */
40#define SM_INC 0x00001000 40#define SM_INC 0x00001000 /* Source addresses are incremented */
41#define SM_DEC 0x00002000 41#define SM_DEC 0x00002000 /* Source addresses are decremented */
42#define SM_FIX 0x00003000 42#define SM_FIX 0x00003000 /* Source address is fixed */
43#define RS_IN 0x00000200 43#define RS_IN 0x00000200
44#define RS_OUT 0x00000300 44#define RS_OUT 0x00000300
45#define RS_AUTO 0x00000400 /* Auto Request */
46#define RS_ERS 0x00000800 /* DMA extended resource selector */
45#define TS_BLK 0x00000040 47#define TS_BLK 0x00000040
46#define TM_BUR 0x00000020 48#define TM_BUR 0x00000020
47#define CHCR_DE 0x00000001 49#define CHCR_DE 0x00000001 /* DMA Enable */
48#define CHCR_TE 0x00000002 50#define CHCR_TE 0x00000002 /* Transfer End Flag */
49#define CHCR_IE 0x00000004 51#define CHCR_IE 0x00000004 /* Interrupt Enable */
50 52
51#endif 53#endif
diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
index 146d5df926db..1a6f6595c6c1 100644
--- a/drivers/dma/sh/shdmac.c
+++ b/drivers/dma/sh/shdmac.c
@@ -38,12 +38,12 @@
38#include "../dmaengine.h" 38#include "../dmaengine.h"
39#include "shdma.h" 39#include "shdma.h"
40 40
41/* DMA register */ 41/* DMA registers */
42#define SAR 0x00 42#define SAR 0x00 /* Source Address Register */
43#define DAR 0x04 43#define DAR 0x04 /* Destination Address Register */
44#define TCR 0x08 44#define TCR 0x08 /* Transfer Count Register */
45#define CHCR 0x0C 45#define CHCR 0x0C /* Channel Control Register */
46#define DMAOR 0x40 46#define DMAOR 0x40 /* DMA Operation Register */
47 47
48#define TEND 0x18 /* USB-DMAC */ 48#define TEND 0x18 /* USB-DMAC */
49 49
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index b7b43b82231e..56b97eed28a4 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -95,19 +95,21 @@ struct sh_dmae_pdata {
95}; 95};
96 96
97/* DMAOR definitions */ 97/* DMAOR definitions */
98#define DMAOR_AE 0x00000004 98#define DMAOR_AE 0x00000004 /* Address Error Flag */
99#define DMAOR_NMIF 0x00000002 99#define DMAOR_NMIF 0x00000002
100#define DMAOR_DME 0x00000001 100#define DMAOR_DME 0x00000001 /* DMA Master Enable */
101 101
102/* Definitions for the SuperH DMAC */ 102/* Definitions for the SuperH DMAC */
103#define DM_INC 0x00004000 103#define DM_INC 0x00004000 /* Destination addresses are incremented */
104#define DM_DEC 0x00008000 104#define DM_DEC 0x00008000 /* Destination addresses are decremented */
105#define DM_FIX 0x0000c000 105#define DM_FIX 0x0000c000 /* Destination address is fixed */
106#define SM_INC 0x00001000 106#define SM_INC 0x00001000 /* Source addresses are incremented */
107#define SM_DEC 0x00002000 107#define SM_DEC 0x00002000 /* Source addresses are decremented */
108#define SM_FIX 0x00003000 108#define SM_FIX 0x00003000 /* Source address is fixed */
109#define CHCR_DE 0x00000001 109#define RS_AUTO 0x00000400 /* Auto Request */
110#define CHCR_TE 0x00000002 110#define RS_ERS 0x00000800 /* DMA extended resource selector */
111#define CHCR_IE 0x00000004 111#define CHCR_DE 0x00000001 /* DMA Enable */
112#define CHCR_TE 0x00000002 /* Transfer End Flag */
113#define CHCR_IE 0x00000004 /* Interrupt Enable */
112 114
113#endif 115#endif