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-rw-r--r--arch/powerpc/sysdev/qe_lib/qe.c36
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_ic.c2
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_io.c35
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc.c270
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_fast.c127
-rw-r--r--arch/powerpc/sysdev/qe_lib/ucc_slow.c48
-rw-r--r--drivers/net/ucc_geth.c2
-rw-r--r--drivers/net/ucc_geth.h1
-rw-r--r--include/asm-powerpc/immap_qe.h30
-rw-r--r--include/asm-powerpc/qe.h243
-rw-r--r--include/asm-powerpc/ucc.h40
-rw-r--r--include/asm-powerpc/ucc_slow.h9
12 files changed, 431 insertions, 412 deletions
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 90f87408b5d5..3d57d3835b04 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -141,7 +141,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
141 * 16 BRGs, which can be connected to the QE channels or output 141 * 16 BRGs, which can be connected to the QE channels or output
142 * as clocks. The BRGs are in two different block of internal 142 * as clocks. The BRGs are in two different block of internal
143 * memory mapped space. 143 * memory mapped space.
144 * The baud rate clock is the system clock divided by something. 144 * The BRG clock is the QE clock divided by 2.
145 * It was set up long ago during the initial boot phase and is 145 * It was set up long ago during the initial boot phase and is
146 * is given to us. 146 * is given to us.
147 * Baud rate clocks are zero-based in the driver code (as that maps 147 * Baud rate clocks are zero-based in the driver code (as that maps
@@ -165,28 +165,38 @@ unsigned int get_brg_clk(void)
165 return brg_clk; 165 return brg_clk;
166} 166}
167 167
168/* This function is used by UARTS, or anything else that uses a 16x 168/* Program the BRG to the given sampling rate and multiplier
169 * oversampled clock. 169 *
170 * @brg: the BRG, 1-16
171 * @rate: the desired sampling rate
172 * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
173 * GUMR_L[TDCR]. E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
174 * then 'multiplier' should be 8.
175 *
176 * Also note that the value programmed into the BRGC register must be even.
170 */ 177 */
171void qe_setbrg(u32 brg, u32 rate) 178void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier)
172{ 179{
173 volatile u32 *bp;
174 u32 divisor, tempval; 180 u32 divisor, tempval;
175 int div16 = 0; 181 u32 div16 = 0;
176 182
177 bp = &qe_immr->brg.brgc[brg]; 183 divisor = get_brg_clk() / (rate * multiplier);
178 184
179 divisor = (get_brg_clk() / rate);
180 if (divisor > QE_BRGC_DIVISOR_MAX + 1) { 185 if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
181 div16 = 1; 186 div16 = QE_BRGC_DIV16;
182 divisor /= 16; 187 divisor /= 16;
183 } 188 }
184 189
185 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) | QE_BRGC_ENABLE; 190 /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
186 if (div16) 191 that the BRG divisor must be even if you're not using divide-by-16
187 tempval |= QE_BRGC_DIV16; 192 mode. */
193 if (!div16 && (divisor & 1))
194 divisor++;
195
196 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
197 QE_BRGC_ENABLE | div16;
188 198
189 out_be32(bp, tempval); 199 out_be32(&qe_immr->brg.brgc[brg - 1], tempval);
190} 200}
191 201
192/* Initialize SNUMs (thread serial numbers) according to 202/* Initialize SNUMs (thread serial numbers) according to
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 55e6f394af82..9a2d1edd050e 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -405,8 +405,6 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags)
405 set_irq_data(qe_ic->virq_high, qe_ic); 405 set_irq_data(qe_ic->virq_high, qe_ic);
406 set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high); 406 set_irq_chained_handler(qe_ic->virq_high, qe_ic_cascade_high);
407 } 407 }
408
409 printk("QEIC (%d IRQ sources) at %p\n", NR_QE_IC_INTS, qe_ic->regs);
410} 408}
411 409
412void qe_ic_set_highest_priority(unsigned int virq, int high) 410void qe_ic_set_highest_priority(unsigned int virq, int high)
diff --git a/arch/powerpc/sysdev/qe_lib/qe_io.c b/arch/powerpc/sysdev/qe_lib/qe_io.c
index e32b45bf9ff5..a114cb0c572f 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_io.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_io.c
@@ -195,29 +195,22 @@ EXPORT_SYMBOL(par_io_of_config);
195#ifdef DEBUG 195#ifdef DEBUG
196static void dump_par_io(void) 196static void dump_par_io(void)
197{ 197{
198 int i; 198 unsigned int i;
199 199
200 printk(KERN_INFO "PAR IO registars:\n"); 200 printk(KERN_INFO "%s: par_io=%p\n", __FUNCTION__, par_io);
201 printk(KERN_INFO "Base address: 0x%08x\n", (u32) par_io);
202 for (i = 0; i < num_par_io_ports; i++) { 201 for (i = 0; i < num_par_io_ports; i++) {
203 printk(KERN_INFO "cpodr[%d] : addr - 0x%08x, val - 0x%08x\n", 202 printk(KERN_INFO " cpodr[%u]=%08x\n", i,
204 i, (u32) & par_io[i].cpodr, 203 in_be32(&par_io[i].cpodr));
205 in_be32(&par_io[i].cpodr)); 204 printk(KERN_INFO " cpdata[%u]=%08x\n", i,
206 printk(KERN_INFO "cpdata[%d]: addr - 0x%08x, val - 0x%08x\n", 205 in_be32(&par_io[i].cpdata));
207 i, (u32) & par_io[i].cpdata, 206 printk(KERN_INFO " cpdir1[%u]=%08x\n", i,
208 in_be32(&par_io[i].cpdata)); 207 in_be32(&par_io[i].cpdir1));
209 printk(KERN_INFO "cpdir1[%d]: addr - 0x%08x, val - 0x%08x\n", 208 printk(KERN_INFO " cpdir2[%u]=%08x\n", i,
210 i, (u32) & par_io[i].cpdir1, 209 in_be32(&par_io[i].cpdir2));
211 in_be32(&par_io[i].cpdir1)); 210 printk(KERN_INFO " cppar1[%u]=%08x\n", i,
212 printk(KERN_INFO "cpdir2[%d]: addr - 0x%08x, val - 0x%08x\n", 211 in_be32(&par_io[i].cppar1));
213 i, (u32) & par_io[i].cpdir2, 212 printk(KERN_INFO " cppar2[%u]=%08x\n", i,
214 in_be32(&par_io[i].cpdir2)); 213 in_be32(&par_io[i].cppar2));
215 printk(KERN_INFO "cppar1[%d]: addr - 0x%08x, val - 0x%08x\n",
216 i, (u32) & par_io[i].cppar1,
217 in_be32(&par_io[i].cppar1));
218 printk(KERN_INFO "cppar2[%d]: addr - 0x%08x, val - 0x%08x\n",
219 i, (u32) & par_io[i].cppar2,
220 in_be32(&par_io[i].cppar2));
221 } 214 }
222 215
223} 216}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c
index f970e5415ac0..0e348d9af8a6 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc.c
@@ -28,228 +28,188 @@
28 28
29static DEFINE_SPINLOCK(ucc_lock); 29static DEFINE_SPINLOCK(ucc_lock);
30 30
31int ucc_set_qe_mux_mii_mng(int ucc_num) 31int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
32{ 32{
33 unsigned long flags; 33 unsigned long flags;
34 34
35 if (ucc_num > UCC_MAX_NUM - 1)
36 return -EINVAL;
37
35 spin_lock_irqsave(&ucc_lock, flags); 38 spin_lock_irqsave(&ucc_lock, flags);
36 out_be32(&qe_immr->qmx.cmxgcr, 39 clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
37 ((in_be32(&qe_immr->qmx.cmxgcr) & 40 ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
38 ~QE_CMXGCR_MII_ENET_MNG) |
39 (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT)));
40 spin_unlock_irqrestore(&ucc_lock, flags); 41 spin_unlock_irqrestore(&ucc_lock, flags);
41 42
42 return 0; 43 return 0;
43} 44}
44EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng); 45EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng);
45 46
46int ucc_set_type(int ucc_num, struct ucc_common *regs, 47/* Configure the UCC to either Slow or Fast.
47 enum ucc_speed_type speed) 48 *
48{ 49 * A given UCC can be figured to support either "slow" devices (e.g. UART)
49 u8 guemr = 0; 50 * or "fast" devices (e.g. Ethernet).
50 51 *
51 /* check if the UCC number is in range. */ 52 * 'ucc_num' is the UCC number, from 0 - 7.
52 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) 53 *
53 return -EINVAL; 54 * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit
54 55 * must always be set to 1.
55 guemr = regs->guemr; 56 */
56 guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX); 57int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
57 switch (speed) {
58 case UCC_SPEED_TYPE_SLOW:
59 guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX);
60 break;
61 case UCC_SPEED_TYPE_FAST:
62 guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX);
63 break;
64 default:
65 return -EINVAL;
66 }
67 regs->guemr = guemr;
68
69 return 0;
70}
71
72int ucc_init_guemr(struct ucc_common *regs)
73{ 58{
74 u8 guemr = 0; 59 u8 __iomem *guemr;
75
76 if (!regs)
77 return -EINVAL;
78
79 /* Set bit 3 (which is reserved in the GUEMR register) to 1 */
80 guemr = UCC_GUEMR_SET_RESERVED3;
81
82 regs->guemr = guemr;
83
84 return 0;
85}
86 60
87static void get_cmxucr_reg(int ucc_num, volatile u32 ** p_cmxucr, u8 * reg_num, 61 /* The GUEMR register is at the same location for both slow and fast
88 u8 * shift) 62 devices, so we just use uccX.slow.guemr. */
89{
90 switch (ucc_num) { 63 switch (ucc_num) {
91 case 0: *p_cmxucr = &(qe_immr->qmx.cmxucr1); 64 case 0: guemr = &qe_immr->ucc1.slow.guemr;
92 *reg_num = 1;
93 *shift = 16;
94 break; 65 break;
95 case 2: *p_cmxucr = &(qe_immr->qmx.cmxucr1); 66 case 1: guemr = &qe_immr->ucc2.slow.guemr;
96 *reg_num = 1;
97 *shift = 0;
98 break; 67 break;
99 case 4: *p_cmxucr = &(qe_immr->qmx.cmxucr2); 68 case 2: guemr = &qe_immr->ucc3.slow.guemr;
100 *reg_num = 2;
101 *shift = 16;
102 break; 69 break;
103 case 6: *p_cmxucr = &(qe_immr->qmx.cmxucr2); 70 case 3: guemr = &qe_immr->ucc4.slow.guemr;
104 *reg_num = 2;
105 *shift = 0;
106 break; 71 break;
107 case 1: *p_cmxucr = &(qe_immr->qmx.cmxucr3); 72 case 4: guemr = &qe_immr->ucc5.slow.guemr;
108 *reg_num = 3;
109 *shift = 16;
110 break; 73 break;
111 case 3: *p_cmxucr = &(qe_immr->qmx.cmxucr3); 74 case 5: guemr = &qe_immr->ucc6.slow.guemr;
112 *reg_num = 3;
113 *shift = 0;
114 break; 75 break;
115 case 5: *p_cmxucr = &(qe_immr->qmx.cmxucr4); 76 case 6: guemr = &qe_immr->ucc7.slow.guemr;
116 *reg_num = 4;
117 *shift = 16;
118 break; 77 break;
119 case 7: *p_cmxucr = &(qe_immr->qmx.cmxucr4); 78 case 7: guemr = &qe_immr->ucc8.slow.guemr;
120 *reg_num = 4;
121 *shift = 0;
122 break; 79 break;
123 default: 80 default:
124 break; 81 return -EINVAL;
125 } 82 }
83
84 clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
85 UCC_GUEMR_SET_RESERVED3 | speed);
86
87 return 0;
88}
89
90static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr,
91 unsigned int *reg_num, unsigned int *shift)
92{
93 unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3);
94
95 *reg_num = cmx + 1;
96 *cmxucr = &qe_immr->qmx.cmxucr[cmx];
97 *shift = 16 - 8 * (ucc_num & 2);
126} 98}
127 99
128int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask) 100int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
129{ 101{
130 volatile u32 *p_cmxucr; 102 __be32 *cmxucr;
131 u8 reg_num; 103 unsigned int reg_num;
132 u8 shift; 104 unsigned int shift;
133 105
134 /* check if the UCC number is in range. */ 106 /* check if the UCC number is in range. */
135 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) 107 if (ucc_num > UCC_MAX_NUM - 1)
136 return -EINVAL; 108 return -EINVAL;
137 109
138 get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift); 110 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
139 111
140 if (set) 112 if (set)
141 out_be32(p_cmxucr, in_be32(p_cmxucr) | (mask << shift)); 113 setbits32(cmxucr, mask << shift);
142 else 114 else
143 out_be32(p_cmxucr, in_be32(p_cmxucr) & ~(mask << shift)); 115 clrbits32(cmxucr, mask << shift);
144 116
145 return 0; 117 return 0;
146} 118}
147 119
148int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode) 120int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
121 enum comm_dir mode)
149{ 122{
150 volatile u32 *p_cmxucr; 123 __be32 *cmxucr;
151 u8 reg_num; 124 unsigned int reg_num;
152 u8 shift; 125 unsigned int shift;
153 u32 clock_bits; 126 u32 clock_bits = 0;
154 u32 clock_mask;
155 int source = -1;
156 127
157 /* check if the UCC number is in range. */ 128 /* check if the UCC number is in range. */
158 if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) 129 if (ucc_num > UCC_MAX_NUM - 1)
159 return -EINVAL; 130 return -EINVAL;
160 131
161 if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) { 132 /* The communications direction must be RX or TX */
162 printk(KERN_ERR 133 if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX)))
163 "ucc_set_qe_mux_rxtx: bad comm mode type passed.");
164 return -EINVAL; 134 return -EINVAL;
165 }
166 135
167 get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift); 136 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
168 137
169 switch (reg_num) { 138 switch (reg_num) {
170 case 1: 139 case 1:
171 switch (clock) { 140 switch (clock) {
172 case QE_BRG1: source = 1; break; 141 case QE_BRG1: clock_bits = 1; break;
173 case QE_BRG2: source = 2; break; 142 case QE_BRG2: clock_bits = 2; break;
174 case QE_BRG7: source = 3; break; 143 case QE_BRG7: clock_bits = 3; break;
175 case QE_BRG8: source = 4; break; 144 case QE_BRG8: clock_bits = 4; break;
176 case QE_CLK9: source = 5; break; 145 case QE_CLK9: clock_bits = 5; break;
177 case QE_CLK10: source = 6; break; 146 case QE_CLK10: clock_bits = 6; break;
178 case QE_CLK11: source = 7; break; 147 case QE_CLK11: clock_bits = 7; break;
179 case QE_CLK12: source = 8; break; 148 case QE_CLK12: clock_bits = 8; break;
180 case QE_CLK15: source = 9; break; 149 case QE_CLK15: clock_bits = 9; break;
181 case QE_CLK16: source = 10; break; 150 case QE_CLK16: clock_bits = 10; break;
182 default: source = -1; break; 151 default: break;
183 } 152 }
184 break; 153 break;
185 case 2: 154 case 2:
186 switch (clock) { 155 switch (clock) {
187 case QE_BRG5: source = 1; break; 156 case QE_BRG5: clock_bits = 1; break;
188 case QE_BRG6: source = 2; break; 157 case QE_BRG6: clock_bits = 2; break;
189 case QE_BRG7: source = 3; break; 158 case QE_BRG7: clock_bits = 3; break;
190 case QE_BRG8: source = 4; break; 159 case QE_BRG8: clock_bits = 4; break;
191 case QE_CLK13: source = 5; break; 160 case QE_CLK13: clock_bits = 5; break;
192 case QE_CLK14: source = 6; break; 161 case QE_CLK14: clock_bits = 6; break;
193 case QE_CLK19: source = 7; break; 162 case QE_CLK19: clock_bits = 7; break;
194 case QE_CLK20: source = 8; break; 163 case QE_CLK20: clock_bits = 8; break;
195 case QE_CLK15: source = 9; break; 164 case QE_CLK15: clock_bits = 9; break;
196 case QE_CLK16: source = 10; break; 165 case QE_CLK16: clock_bits = 10; break;
197 default: source = -1; break; 166 default: break;
198 } 167 }
199 break; 168 break;
200 case 3: 169 case 3:
201 switch (clock) { 170 switch (clock) {
202 case QE_BRG9: source = 1; break; 171 case QE_BRG9: clock_bits = 1; break;
203 case QE_BRG10: source = 2; break; 172 case QE_BRG10: clock_bits = 2; break;
204 case QE_BRG15: source = 3; break; 173 case QE_BRG15: clock_bits = 3; break;
205 case QE_BRG16: source = 4; break; 174 case QE_BRG16: clock_bits = 4; break;
206 case QE_CLK3: source = 5; break; 175 case QE_CLK3: clock_bits = 5; break;
207 case QE_CLK4: source = 6; break; 176 case QE_CLK4: clock_bits = 6; break;
208 case QE_CLK17: source = 7; break; 177 case QE_CLK17: clock_bits = 7; break;
209 case QE_CLK18: source = 8; break; 178 case QE_CLK18: clock_bits = 8; break;
210 case QE_CLK7: source = 9; break; 179 case QE_CLK7: clock_bits = 9; break;
211 case QE_CLK8: source = 10; break; 180 case QE_CLK8: clock_bits = 10; break;
212 case QE_CLK16: source = 11; break; 181 case QE_CLK16: clock_bits = 11; break;
213 default: source = -1; break; 182 default: break;
214 } 183 }
215 break; 184 break;
216 case 4: 185 case 4:
217 switch (clock) { 186 switch (clock) {
218 case QE_BRG13: source = 1; break; 187 case QE_BRG13: clock_bits = 1; break;
219 case QE_BRG14: source = 2; break; 188 case QE_BRG14: clock_bits = 2; break;
220 case QE_BRG15: source = 3; break; 189 case QE_BRG15: clock_bits = 3; break;
221 case QE_BRG16: source = 4; break; 190 case QE_BRG16: clock_bits = 4; break;
222 case QE_CLK5: source = 5; break; 191 case QE_CLK5: clock_bits = 5; break;
223 case QE_CLK6: source = 6; break; 192 case QE_CLK6: clock_bits = 6; break;
224 case QE_CLK21: source = 7; break; 193 case QE_CLK21: clock_bits = 7; break;
225 case QE_CLK22: source = 8; break; 194 case QE_CLK22: clock_bits = 8; break;
226 case QE_CLK7: source = 9; break; 195 case QE_CLK7: clock_bits = 9; break;
227 case QE_CLK8: source = 10; break; 196 case QE_CLK8: clock_bits = 10; break;
228 case QE_CLK16: source = 11; break; 197 case QE_CLK16: clock_bits = 11; break;
229 default: source = -1; break; 198 default: break;
230 } 199 }
231 break; 200 break;
232 default: 201 default: break;
233 source = -1;
234 break;
235 } 202 }
236 203
237 if (source == -1) { 204 /* Check for invalid combination of clock and UCC number */
238 printk(KERN_ERR 205 if (!clock_bits)
239 "ucc_set_qe_mux_rxtx: Bad combination of clock and UCC.");
240 return -ENOENT; 206 return -ENOENT;
241 }
242 207
243 clock_bits = (u32) source; 208 if (mode == COMM_DIR_RX)
244 clock_mask = QE_CMXUCR_TX_CLK_SRC_MASK; 209 shift += 4;
245 if (mode == COMM_DIR_RX) {
246 clock_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
247 clock_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
248 }
249 clock_bits <<= shift;
250 clock_mask <<= shift;
251 210
252 out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clock_mask) | clock_bits); 211 clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
212 clock_bits << shift);
253 213
254 return 0; 214 return 0;
255} 215}
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_fast.c b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
index 3df202e8d332..3223acbc39e5 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_fast.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_fast.c
@@ -30,46 +30,45 @@
30 30
31void ucc_fast_dump_regs(struct ucc_fast_private * uccf) 31void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
32{ 32{
33 printk(KERN_INFO "UCC%d Fast registers:", uccf->uf_info->ucc_num); 33 printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num);
34 printk(KERN_INFO "Base address: 0x%08x", (u32) uccf->uf_regs); 34 printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
35 35
36 printk(KERN_INFO "gumr : addr - 0x%08x, val - 0x%08x", 36 printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
37 (u32) & uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr)); 37 &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
38 printk(KERN_INFO "upsmr : addr - 0x%08x, val - 0x%08x", 38 printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
39 (u32) & uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr)); 39 &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
40 printk(KERN_INFO "utodr : addr - 0x%08x, val - 0x%04x", 40 printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
41 (u32) & uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr)); 41 &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
42 printk(KERN_INFO "udsr : addr - 0x%08x, val - 0x%04x", 42 printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
43 (u32) & uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr)); 43 &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
44 printk(KERN_INFO "ucce : addr - 0x%08x, val - 0x%08x", 44 printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
45 (u32) & uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce)); 45 &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
46 printk(KERN_INFO "uccm : addr - 0x%08x, val - 0x%08x", 46 printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
47 (u32) & uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm)); 47 &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
48 printk(KERN_INFO "uccs : addr - 0x%08x, val - 0x%02x", 48 printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
49 (u32) & uccf->uf_regs->uccs, uccf->uf_regs->uccs); 49 &uccf->uf_regs->uccs, uccf->uf_regs->uccs);
50 printk(KERN_INFO "urfb : addr - 0x%08x, val - 0x%08x", 50 printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
51 (u32) & uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb)); 51 &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
52 printk(KERN_INFO "urfs : addr - 0x%08x, val - 0x%04x", 52 printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
53 (u32) & uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs)); 53 &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
54 printk(KERN_INFO "urfet : addr - 0x%08x, val - 0x%04x", 54 printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
55 (u32) & uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet)); 55 &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
56 printk(KERN_INFO "urfset: addr - 0x%08x, val - 0x%04x", 56 printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
57 (u32) & uccf->uf_regs->urfset, 57 &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
58 in_be16(&uccf->uf_regs->urfset)); 58 printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
59 printk(KERN_INFO "utfb : addr - 0x%08x, val - 0x%08x", 59 &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
60 (u32) & uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb)); 60 printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
61 printk(KERN_INFO "utfs : addr - 0x%08x, val - 0x%04x", 61 &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
62 (u32) & uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs)); 62 printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
63 printk(KERN_INFO "utfet : addr - 0x%08x, val - 0x%04x", 63 &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
64 (u32) & uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet)); 64 printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
65 printk(KERN_INFO "utftt : addr - 0x%08x, val - 0x%04x", 65 &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
66 (u32) & uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt)); 66 printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
67 printk(KERN_INFO "utpt : addr - 0x%08x, val - 0x%04x", 67 &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
68 (u32) & uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt)); 68 printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
69 printk(KERN_INFO "urtry : addr - 0x%08x, val - 0x%08x", 69 &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
70 (u32) & uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry)); 70 printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
71 printk(KERN_INFO "guemr : addr - 0x%08x, val - 0x%02x", 71 &uccf->uf_regs->guemr, uccf->uf_regs->guemr);
72 (u32) & uccf->uf_regs->guemr, uccf->uf_regs->guemr);
73} 72}
74EXPORT_SYMBOL(ucc_fast_dump_regs); 73EXPORT_SYMBOL(ucc_fast_dump_regs);
75 74
@@ -149,55 +148,57 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
149 148
150 /* check if the UCC port number is in range. */ 149 /* check if the UCC port number is in range. */
151 if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) { 150 if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
152 printk(KERN_ERR "%s: illegal UCC number", __FUNCTION__); 151 printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
153 return -EINVAL; 152 return -EINVAL;
154 } 153 }
155 154
156 /* Check that 'max_rx_buf_length' is properly aligned (4). */ 155 /* Check that 'max_rx_buf_length' is properly aligned (4). */
157 if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) { 156 if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
158 printk(KERN_ERR "%s: max_rx_buf_length not aligned", __FUNCTION__); 157 printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
158 __FUNCTION__);
159 return -EINVAL; 159 return -EINVAL;
160 } 160 }
161 161
162 /* Validate Virtual Fifo register values */ 162 /* Validate Virtual Fifo register values */
163 if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) { 163 if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
164 printk(KERN_ERR "%s: urfs is too small", __FUNCTION__); 164 printk(KERN_ERR "%s: urfs is too small\n", __FUNCTION__);
165 return -EINVAL; 165 return -EINVAL;
166 } 166 }
167 167
168 if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 168 if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
169 printk(KERN_ERR "%s: urfs is not aligned", __FUNCTION__); 169 printk(KERN_ERR "%s: urfs is not aligned\n", __FUNCTION__);
170 return -EINVAL; 170 return -EINVAL;
171 } 171 }
172 172
173 if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 173 if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
174 printk(KERN_ERR "%s: urfet is not aligned.", __FUNCTION__); 174 printk(KERN_ERR "%s: urfet is not aligned.\n", __FUNCTION__);
175 return -EINVAL; 175 return -EINVAL;
176 } 176 }
177 177
178 if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 178 if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
179 printk(KERN_ERR "%s: urfset is not aligned", __FUNCTION__); 179 printk(KERN_ERR "%s: urfset is not aligned\n", __FUNCTION__);
180 return -EINVAL; 180 return -EINVAL;
181 } 181 }
182 182
183 if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 183 if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
184 printk(KERN_ERR "%s: utfs is not aligned", __FUNCTION__); 184 printk(KERN_ERR "%s: utfs is not aligned\n", __FUNCTION__);
185 return -EINVAL; 185 return -EINVAL;
186 } 186 }
187 187
188 if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 188 if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
189 printk(KERN_ERR "%s: utfet is not aligned", __FUNCTION__); 189 printk(KERN_ERR "%s: utfet is not aligned\n", __FUNCTION__);
190 return -EINVAL; 190 return -EINVAL;
191 } 191 }
192 192
193 if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) { 193 if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
194 printk(KERN_ERR "%s: utftt is not aligned", __FUNCTION__); 194 printk(KERN_ERR "%s: utftt is not aligned\n", __FUNCTION__);
195 return -EINVAL; 195 return -EINVAL;
196 } 196 }
197 197
198 uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL); 198 uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
199 if (!uccf) { 199 if (!uccf) {
200 printk(KERN_ERR "%s: Cannot allocate private data", __FUNCTION__); 200 printk(KERN_ERR "%s: Cannot allocate private data\n",
201 __FUNCTION__);
201 return -ENOMEM; 202 return -ENOMEM;
202 } 203 }
203 204
@@ -206,7 +207,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
206 /* Set the PHY base address */ 207 /* Set the PHY base address */
207 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast)); 208 uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
208 if (uccf->uf_regs == NULL) { 209 if (uccf->uf_regs == NULL) {
209 printk(KERN_ERR "%s: Cannot map UCC registers", __FUNCTION__); 210 printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
210 return -ENOMEM; 211 return -ENOMEM;
211 } 212 }
212 213
@@ -226,18 +227,10 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
226 uccf->rx_discarded = 0; 227 uccf->rx_discarded = 0;
227#endif /* STATISTICS */ 228#endif /* STATISTICS */
228 229
229 /* Init Guemr register */
230 if ((ret = ucc_init_guemr((struct ucc_common *) (uf_regs)))) {
231 printk(KERN_ERR "%s: cannot init GUEMR", __FUNCTION__);
232 ucc_fast_free(uccf);
233 return ret;
234 }
235
236 /* Set UCC to fast type */ 230 /* Set UCC to fast type */
237 if ((ret = ucc_set_type(uf_info->ucc_num, 231 ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
238 (struct ucc_common *) (uf_regs), 232 if (ret) {
239 UCC_SPEED_TYPE_FAST))) { 233 printk(KERN_ERR "%s: cannot set UCC type\n", __FUNCTION__);
240 printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
241 ucc_fast_free(uccf); 234 ucc_fast_free(uccf);
242 return ret; 235 return ret;
243 } 236 }
@@ -276,7 +269,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
276 uccf->ucc_fast_tx_virtual_fifo_base_offset = 269 uccf->ucc_fast_tx_virtual_fifo_base_offset =
277 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 270 qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
278 if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) { 271 if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
279 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO", __FUNCTION__); 272 printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
273 __FUNCTION__);
280 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0; 274 uccf->ucc_fast_tx_virtual_fifo_base_offset = 0;
281 ucc_fast_free(uccf); 275 ucc_fast_free(uccf);
282 return -ENOMEM; 276 return -ENOMEM;
@@ -288,7 +282,8 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
288 UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR, 282 UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
289 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT); 283 UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
290 if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) { 284 if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
291 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO", __FUNCTION__); 285 printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
286 __FUNCTION__);
292 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0; 287 uccf->ucc_fast_rx_virtual_fifo_base_offset = 0;
293 ucc_fast_free(uccf); 288 ucc_fast_free(uccf);
294 return -ENOMEM; 289 return -ENOMEM;
@@ -318,7 +313,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
318 if ((uf_info->rx_clock != QE_CLK_NONE) && 313 if ((uf_info->rx_clock != QE_CLK_NONE) &&
319 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock, 314 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
320 COMM_DIR_RX)) { 315 COMM_DIR_RX)) {
321 printk(KERN_ERR "%s: illegal value for RX clock", 316 printk(KERN_ERR "%s: illegal value for RX clock\n",
322 __FUNCTION__); 317 __FUNCTION__);
323 ucc_fast_free(uccf); 318 ucc_fast_free(uccf);
324 return -EINVAL; 319 return -EINVAL;
@@ -327,7 +322,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
327 if ((uf_info->tx_clock != QE_CLK_NONE) && 322 if ((uf_info->tx_clock != QE_CLK_NONE) &&
328 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock, 323 ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
329 COMM_DIR_TX)) { 324 COMM_DIR_TX)) {
330 printk(KERN_ERR "%s: illegal value for TX clock", 325 printk(KERN_ERR "%s: illegal value for TX clock\n",
331 __FUNCTION__); 326 __FUNCTION__);
332 ucc_fast_free(uccf); 327 ucc_fast_free(uccf);
333 return -EINVAL; 328 return -EINVAL;
diff --git a/arch/powerpc/sysdev/qe_lib/ucc_slow.c b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
index 1f65c26ce63f..0174b3aeef8f 100644
--- a/arch/powerpc/sysdev/qe_lib/ucc_slow.c
+++ b/arch/powerpc/sysdev/qe_lib/ucc_slow.c
@@ -115,11 +115,15 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
115 out_be32(&us_regs->gumr_l, gumr_l); 115 out_be32(&us_regs->gumr_l, gumr_l);
116} 116}
117 117
118/* Initialize the UCC for Slow operations
119 *
120 * The caller should initialize the following us_info
121 */
118int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret) 122int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
119{ 123{
120 struct ucc_slow_private *uccs; 124 struct ucc_slow_private *uccs;
121 u32 i; 125 u32 i;
122 struct ucc_slow *us_regs; 126 struct ucc_slow __iomem *us_regs;
123 u32 gumr; 127 u32 gumr;
124 struct qe_bd *bd; 128 struct qe_bd *bd;
125 u32 id; 129 u32 id;
@@ -131,7 +135,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
131 135
132 /* check if the UCC port number is in range. */ 136 /* check if the UCC port number is in range. */
133 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) { 137 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
134 printk(KERN_ERR "%s: illegal UCC number", __FUNCTION__); 138 printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
135 return -EINVAL; 139 return -EINVAL;
136 } 140 }
137 141
@@ -143,13 +147,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
143 */ 147 */
144 if ((!us_info->rfw) && 148 if ((!us_info->rfw) &&
145 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) { 149 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
146 printk(KERN_ERR "max_rx_buf_length not aligned."); 150 printk(KERN_ERR "max_rx_buf_length not aligned.\n");
147 return -EINVAL; 151 return -EINVAL;
148 } 152 }
149 153
150 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL); 154 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
151 if (!uccs) { 155 if (!uccs) {
152 printk(KERN_ERR "%s: Cannot allocate private data", __FUNCTION__); 156 printk(KERN_ERR "%s: Cannot allocate private data\n",
157 __FUNCTION__);
153 return -ENOMEM; 158 return -ENOMEM;
154 } 159 }
155 160
@@ -158,7 +163,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
158 /* Set the PHY base address */ 163 /* Set the PHY base address */
159 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow)); 164 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
160 if (uccs->us_regs == NULL) { 165 if (uccs->us_regs == NULL) {
161 printk(KERN_ERR "%s: Cannot map UCC registers", __FUNCTION__); 166 printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
162 return -ENOMEM; 167 return -ENOMEM;
163 } 168 }
164 169
@@ -182,22 +187,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
182 return -ENOMEM; 187 return -ENOMEM;
183 } 188 }
184 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 189 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
185 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, QE_CR_PROTOCOL_UNSPECIFIED, 190 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
186 uccs->us_pram_offset); 191 uccs->us_pram_offset);
187 192
188 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset); 193 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
189 194
190 /* Init Guemr register */
191 if ((ret = ucc_init_guemr((struct ucc_common *) us_regs))) {
192 printk(KERN_ERR "%s: cannot init GUEMR", __FUNCTION__);
193 ucc_slow_free(uccs);
194 return ret;
195 }
196
197 /* Set UCC to slow type */ 195 /* Set UCC to slow type */
198 if ((ret = ucc_set_type(us_info->ucc_num, 196 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
199 (struct ucc_common *) us_regs, 197 if (ret) {
200 UCC_SPEED_TYPE_SLOW))) {
201 printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__); 198 printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
202 ucc_slow_free(uccs); 199 ucc_slow_free(uccs);
203 return ret; 200 return ret;
@@ -212,7 +209,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
212 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd), 209 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
213 QE_ALIGNMENT_OF_BD); 210 QE_ALIGNMENT_OF_BD);
214 if (IS_ERR_VALUE(uccs->rx_base_offset)) { 211 if (IS_ERR_VALUE(uccs->rx_base_offset)) {
215 printk(KERN_ERR "%s: cannot allocate RX BDs", __FUNCTION__); 212 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __FUNCTION__,
213 us_info->rx_bd_ring_len);
216 uccs->rx_base_offset = 0; 214 uccs->rx_base_offset = 0;
217 ucc_slow_free(uccs); 215 ucc_slow_free(uccs);
218 return -ENOMEM; 216 return -ENOMEM;
@@ -292,12 +290,12 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
292 290
293 /* if the data is in cachable memory, the 'global' */ 291 /* if the data is in cachable memory, the 'global' */
294 /* in the function code should be set. */ 292 /* in the function code should be set. */
295 uccs->us_pram->tfcr = uccs->us_pram->rfcr = 293 uccs->us_pram->tbmr = UCC_BMR_BO_BE;
296 us_info->data_mem_part | QE_BMR_BYTE_ORDER_BO_MOT; 294 uccs->us_pram->rbmr = UCC_BMR_BO_BE;
297 295
298 /* rbase, tbase are offsets from MURAM base */ 296 /* rbase, tbase are offsets from MURAM base */
299 out_be16(&uccs->us_pram->rbase, uccs->us_pram_offset); 297 out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
300 out_be16(&uccs->us_pram->tbase, uccs->us_pram_offset); 298 out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
301 299
302 /* Mux clocking */ 300 /* Mux clocking */
303 /* Grant Support */ 301 /* Grant Support */
@@ -311,7 +309,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
311 /* Rx clock routing */ 309 /* Rx clock routing */
312 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock, 310 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
313 COMM_DIR_RX)) { 311 COMM_DIR_RX)) {
314 printk(KERN_ERR "%s: illegal value for RX clock", 312 printk(KERN_ERR "%s: illegal value for RX clock\n",
315 __FUNCTION__); 313 __FUNCTION__);
316 ucc_slow_free(uccs); 314 ucc_slow_free(uccs);
317 return -EINVAL; 315 return -EINVAL;
@@ -319,7 +317,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
319 /* Tx clock routing */ 317 /* Tx clock routing */
320 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock, 318 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
321 COMM_DIR_TX)) { 319 COMM_DIR_TX)) {
322 printk(KERN_ERR "%s: illegal value for TX clock", 320 printk(KERN_ERR "%s: illegal value for TX clock\n",
323 __FUNCTION__); 321 __FUNCTION__);
324 ucc_slow_free(uccs); 322 ucc_slow_free(uccs);
325 return -EINVAL; 323 return -EINVAL;
@@ -343,8 +341,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
343 command = QE_INIT_TX; 341 command = QE_INIT_TX;
344 else 342 else
345 command = QE_INIT_RX; /* We know at least one is TRUE */ 343 command = QE_INIT_RX; /* We know at least one is TRUE */
346 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); 344
347 qe_issue_cmd(command, id, QE_CR_PROTOCOL_UNSPECIFIED, 0); 345 qe_issue_cmd(command, id, us_info->protocol, 0);
348 346
349 *uccs_ret = uccs; 347 *uccs_ret = uccs;
350 return 0; 348 return 0;
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 9a38dfe45f8f..7dedc9609603 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -2919,7 +2919,7 @@ static int ucc_geth_startup(struct ucc_geth_private *ugeth)
2919 test = in_be16(&ugeth->p_tx_glbl_pram->temoder); 2919 test = in_be16(&ugeth->p_tx_glbl_pram->temoder);
2920 2920
2921 /* Function code register value to be used later */ 2921 /* Function code register value to be used later */
2922 function_code = QE_BMR_BYTE_ORDER_BO_MOT | UCC_FAST_FUNCTION_CODE_GBL; 2922 function_code = UCC_BMR_BO_BE | UCC_BMR_GBL;
2923 /* Required for QE */ 2923 /* Required for QE */
2924 2924
2925 /* function code register */ 2925 /* function code register */
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h
index bb4dac8c0c65..1aa69023cde1 100644
--- a/drivers/net/ucc_geth.h
+++ b/drivers/net/ucc_geth.h
@@ -44,6 +44,7 @@
44 44
45struct ucc_geth { 45struct ucc_geth {
46 struct ucc_fast uccf; 46 struct ucc_fast uccf;
47 u8 res0[0x100 - sizeof(struct ucc_fast)];
47 48
48 u32 maccfg1; /* mac configuration reg. 1 */ 49 u32 maccfg1; /* mac configuration reg. 1 */
49 u32 maccfg2; /* mac configuration reg. 2 */ 50 u32 maccfg2; /* mac configuration reg. 2 */
diff --git a/include/asm-powerpc/immap_qe.h b/include/asm-powerpc/immap_qe.h
index 02548f74ccb7..aba9806b31c9 100644
--- a/include/asm-powerpc/immap_qe.h
+++ b/include/asm-powerpc/immap_qe.h
@@ -97,10 +97,7 @@ struct qe_mux {
97 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */ 97 __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */
98 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */ 98 __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */
99 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */ 99 __be32 cmxsi1syr; /* CMX SI1 SYNC route register */
100 __be32 cmxucr1; /* CMX UCC1, UCC3 clock route register */ 100 __be32 cmxucr[4]; /* CMX UCCx clock route registers */
101 __be32 cmxucr2; /* CMX UCC5, UCC7 clock route register */
102 __be32 cmxucr3; /* CMX UCC2, UCC4 clock route register */
103 __be32 cmxucr4; /* CMX UCC6, UCC8 clock route register */
104 __be32 cmxupcr; /* CMX UPC clock route register */ 101 __be32 cmxupcr; /* CMX UPC clock route register */
105 u8 res0[0x1C]; 102 u8 res0[0x1C];
106} __attribute__ ((packed)); 103} __attribute__ ((packed));
@@ -261,7 +258,6 @@ struct ucc_slow {
261 __be16 utpt; 258 __be16 utpt;
262 u8 res4[0x52]; 259 u8 res4[0x52];
263 u8 guemr; /* UCC general extended mode register */ 260 u8 guemr; /* UCC general extended mode register */
264 u8 res5[0x200 - 0x091];
265} __attribute__ ((packed)); 261} __attribute__ ((packed));
266 262
267/* QE UCC Fast */ 263/* QE UCC Fast */
@@ -294,21 +290,13 @@ struct ucc_fast {
294 __be32 urtry; /* UCC retry counter register */ 290 __be32 urtry; /* UCC retry counter register */
295 u8 res8[0x4C]; 291 u8 res8[0x4C];
296 u8 guemr; /* UCC general extended mode register */ 292 u8 guemr; /* UCC general extended mode register */
297 u8 res9[0x100 - 0x091];
298} __attribute__ ((packed));
299
300/* QE UCC */
301struct ucc_common {
302 u8 res1[0x90];
303 u8 guemr;
304 u8 res2[0x200 - 0x091];
305} __attribute__ ((packed)); 293} __attribute__ ((packed));
306 294
307struct ucc { 295struct ucc {
308 union { 296 union {
309 struct ucc_slow slow; 297 struct ucc_slow slow;
310 struct ucc_fast fast; 298 struct ucc_fast fast;
311 struct ucc_common common; 299 u8 res[0x200]; /* UCC blocks are 512 bytes each */
312 }; 300 };
313} __attribute__ ((packed)); 301} __attribute__ ((packed));
314 302
@@ -407,7 +395,7 @@ struct dbg {
407 395
408/* RISC Special Registers (Trap and Breakpoint) */ 396/* RISC Special Registers (Trap and Breakpoint) */
409struct rsp { 397struct rsp {
410 u8 fixme[0x100]; 398 u32 reg[0x40]; /* 64 32-bit registers */
411} __attribute__ ((packed)); 399} __attribute__ ((packed));
412 400
413struct qe_immap { 401struct qe_immap {
@@ -436,11 +424,13 @@ struct qe_immap {
436 u8 res13[0x600]; 424 u8 res13[0x600];
437 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/ 425 struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/
438 struct sdma sdma; /* SDMA */ 426 struct sdma sdma; /* SDMA */
439 struct dbg dbg; /* Debug Space */ 427 struct dbg dbg; /* 0x104080 - 0x1040FF
440 struct rsp rsp[0x2]; /* RISC Special Registers 428 Debug Space */
429 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
430 RISC Special Registers
441 (Trap and Breakpoint) */ 431 (Trap and Breakpoint) */
442 u8 res14[0x300]; 432 u8 res14[0x300]; /* 0x104300 - 0x1045FF */
443 u8 res15[0x3A00]; 433 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
444 u8 res16[0x8000]; /* 0x108000 - 0x110000 */ 434 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
445 u8 muram[0xC000]; /* 0x110000 - 0x11C000 435 u8 muram[0xC000]; /* 0x110000 - 0x11C000
446 Multi-user RAM */ 436 Multi-user RAM */
@@ -451,7 +441,7 @@ struct qe_immap {
451extern struct qe_immap *qe_immr; 441extern struct qe_immap *qe_immr;
452extern phys_addr_t get_qe_base(void); 442extern phys_addr_t get_qe_base(void);
453 443
454static inline unsigned long immrbar_virt_to_phys(volatile void * address) 444static inline unsigned long immrbar_virt_to_phys(void *address)
455{ 445{
456 if ( ((u32)address >= (u32)qe_immr) && 446 if ( ((u32)address >= (u32)qe_immr) &&
457 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) ) 447 ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index ad23c580631c..0dabe46a29d2 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -38,7 +38,7 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
38 38
39/* QE internal API */ 39/* QE internal API */
40int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 40int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
41void qe_setbrg(u32 brg, u32 rate); 41void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier);
42int qe_get_snum(void); 42int qe_get_snum(void);
43void qe_put_snum(u8 snum); 43void qe_put_snum(u8 snum);
44unsigned long qe_muram_alloc(int size, int align); 44unsigned long qe_muram_alloc(int size, int align);
@@ -49,14 +49,28 @@ void *qe_muram_addr(unsigned long offset);
49 49
50/* Buffer descriptors */ 50/* Buffer descriptors */
51struct qe_bd { 51struct qe_bd {
52 u16 status; 52 __be16 status;
53 u16 length; 53 __be16 length;
54 u32 buf; 54 __be32 buf;
55} __attribute__ ((packed)); 55} __attribute__ ((packed));
56 56
57#define BD_STATUS_MASK 0xffff0000 57#define BD_STATUS_MASK 0xffff0000
58#define BD_LENGTH_MASK 0x0000ffff 58#define BD_LENGTH_MASK 0x0000ffff
59 59
60#define BD_SC_EMPTY 0x8000 /* Receive is empty */
61#define BD_SC_READY 0x8000 /* Transmit is ready */
62#define BD_SC_WRAP 0x2000 /* Last buffer descriptor */
63#define BD_SC_INTRPT 0x1000 /* Interrupt on change */
64#define BD_SC_LAST 0x0800 /* Last buffer in frame */
65#define BD_SC_CM 0x0200 /* Continous mode */
66#define BD_SC_ID 0x0100 /* Rec'd too many idles */
67#define BD_SC_P 0x0100 /* xmt preamble */
68#define BD_SC_BR 0x0020 /* Break received */
69#define BD_SC_FR 0x0010 /* Framing error */
70#define BD_SC_PR 0x0008 /* Parity error */
71#define BD_SC_OV 0x0002 /* Overrun */
72#define BD_SC_CD 0x0001 /* ?? */
73
60/* Alignment */ 74/* Alignment */
61#define QE_INTR_TABLE_ALIGN 16 /* ??? */ 75#define QE_INTR_TABLE_ALIGN 16 /* ??? */
62#define QE_ALIGNMENT_OF_BD 8 76#define QE_ALIGNMENT_OF_BD 8
@@ -269,15 +283,12 @@ enum qe_clock {
269/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ 283/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
270#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ 284#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
271#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 285#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
286#define QE_CR_PROTOCOL_QMC 0x02
287#define QE_CR_PROTOCOL_UART 0x04
272#define QE_CR_PROTOCOL_ATM_POS 0x0A 288#define QE_CR_PROTOCOL_ATM_POS 0x0A
273#define QE_CR_PROTOCOL_ETHERNET 0x0C 289#define QE_CR_PROTOCOL_ETHERNET 0x0C
274#define QE_CR_PROTOCOL_L2_SWITCH 0x0D 290#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
275 291
276/* BMR byte order */
277#define QE_BMR_BYTE_ORDER_BO_PPC 0x08 /* powerpc little endian */
278#define QE_BMR_BYTE_ORDER_BO_MOT 0x10 /* motorola big endian */
279#define QE_BMR_BYTE_ORDER_BO_MAX 0x18
280
281/* BRG configuration register */ 292/* BRG configuration register */
282#define QE_BRGC_ENABLE 0x00010000 293#define QE_BRGC_ENABLE 0x00010000
283#define QE_BRGC_DIVISOR_SHIFT 1 294#define QE_BRGC_DIVISOR_SHIFT 1
@@ -324,41 +335,41 @@ enum qe_clock {
324#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ 335#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
325#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ 336#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
326 337
327/* UCC */ 338/* UCC GUEMR register */
328#define UCC_GUEMR_MODE_MASK_RX 0x02 339#define UCC_GUEMR_MODE_MASK_RX 0x02
329#define UCC_GUEMR_MODE_MASK_TX 0x01
330#define UCC_GUEMR_MODE_FAST_RX 0x02 340#define UCC_GUEMR_MODE_FAST_RX 0x02
331#define UCC_GUEMR_MODE_FAST_TX 0x01
332#define UCC_GUEMR_MODE_SLOW_RX 0x00 341#define UCC_GUEMR_MODE_SLOW_RX 0x00
342#define UCC_GUEMR_MODE_MASK_TX 0x01
343#define UCC_GUEMR_MODE_FAST_TX 0x01
333#define UCC_GUEMR_MODE_SLOW_TX 0x00 344#define UCC_GUEMR_MODE_SLOW_TX 0x00
345#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
334#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but 346#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
335 must be set 1 */ 347 must be set 1 */
336 348
337/* structure representing UCC SLOW parameter RAM */ 349/* structure representing UCC SLOW parameter RAM */
338struct ucc_slow_pram { 350struct ucc_slow_pram {
339 u16 rbase; /* RX BD base address */ 351 __be16 rbase; /* RX BD base address */
340 u16 tbase; /* TX BD base address */ 352 __be16 tbase; /* TX BD base address */
341 u8 rfcr; /* Rx function code */ 353 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
342 u8 tfcr; /* Tx function code */ 354 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
343 u16 mrblr; /* Rx buffer length */ 355 __be16 mrblr; /* Rx buffer length */
344 u32 rstate; /* Rx internal state */ 356 __be32 rstate; /* Rx internal state */
345 u32 rptr; /* Rx internal data pointer */ 357 __be32 rptr; /* Rx internal data pointer */
346 u16 rbptr; /* rb BD Pointer */ 358 __be16 rbptr; /* rb BD Pointer */
347 u16 rcount; /* Rx internal byte count */ 359 __be16 rcount; /* Rx internal byte count */
348 u32 rtemp; /* Rx temp */ 360 __be32 rtemp; /* Rx temp */
349 u32 tstate; /* Tx internal state */ 361 __be32 tstate; /* Tx internal state */
350 u32 tptr; /* Tx internal data pointer */ 362 __be32 tptr; /* Tx internal data pointer */
351 u16 tbptr; /* Tx BD pointer */ 363 __be16 tbptr; /* Tx BD pointer */
352 u16 tcount; /* Tx byte count */ 364 __be16 tcount; /* Tx byte count */
353 u32 ttemp; /* Tx temp */ 365 __be32 ttemp; /* Tx temp */
354 u32 rcrc; /* temp receive CRC */ 366 __be32 rcrc; /* temp receive CRC */
355 u32 tcrc; /* temp transmit CRC */ 367 __be32 tcrc; /* temp transmit CRC */
356} __attribute__ ((packed)); 368} __attribute__ ((packed));
357 369
358/* General UCC SLOW Mode Register (GUMRH & GUMRL) */ 370/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
359#define UCC_SLOW_GUMR_H_CRC16 0x00004000 371#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
360#define UCC_SLOW_GUMR_H_CRC16CCITT 0x00000000 372#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
361#define UCC_SLOW_GUMR_H_CRC32CCITT 0x00008000
362#define UCC_SLOW_GUMR_H_REVD 0x00002000 373#define UCC_SLOW_GUMR_H_REVD 0x00002000
363#define UCC_SLOW_GUMR_H_TRX 0x00001000 374#define UCC_SLOW_GUMR_H_TRX 0x00001000
364#define UCC_SLOW_GUMR_H_TTX 0x00000800 375#define UCC_SLOW_GUMR_H_TTX 0x00000800
@@ -378,9 +389,33 @@ struct ucc_slow_pram {
378#define UCC_SLOW_GUMR_L_TCI 0x10000000 389#define UCC_SLOW_GUMR_L_TCI 0x10000000
379#define UCC_SLOW_GUMR_L_RINV 0x02000000 390#define UCC_SLOW_GUMR_L_RINV 0x02000000
380#define UCC_SLOW_GUMR_L_TINV 0x01000000 391#define UCC_SLOW_GUMR_L_TINV 0x01000000
381#define UCC_SLOW_GUMR_L_TEND 0x00020000 392#define UCC_SLOW_GUMR_L_TEND 0x00040000
393#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
394#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
395#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
396#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
397#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
398#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
399#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
400#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
401#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
402#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
403#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
404#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
405#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
406#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
407#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
408#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
409#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
410#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
411#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
382#define UCC_SLOW_GUMR_L_ENR 0x00000020 412#define UCC_SLOW_GUMR_L_ENR 0x00000020
383#define UCC_SLOW_GUMR_L_ENT 0x00000010 413#define UCC_SLOW_GUMR_L_ENT 0x00000010
414#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
415#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
416#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
417#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
418#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
384 419
385/* General UCC FAST Mode Register */ 420/* General UCC FAST Mode Register */
386#define UCC_FAST_GUMR_TCI 0x20000000 421#define UCC_FAST_GUMR_TCI 0x20000000
@@ -397,53 +432,111 @@ struct ucc_slow_pram {
397#define UCC_FAST_GUMR_ENR 0x00000020 432#define UCC_FAST_GUMR_ENR 0x00000020
398#define UCC_FAST_GUMR_ENT 0x00000010 433#define UCC_FAST_GUMR_ENT 0x00000010
399 434
400/* Slow UCC Event Register (UCCE) */ 435/* UART Slow UCC Event Register (UCCE) */
401#define UCC_SLOW_UCCE_GLR 0x1000 436#define UCC_UART_UCCE_AB 0x0200
402#define UCC_SLOW_UCCE_GLT 0x0800 437#define UCC_UART_UCCE_IDLE 0x0100
403#define UCC_SLOW_UCCE_DCC 0x0400 438#define UCC_UART_UCCE_GRA 0x0080
404#define UCC_SLOW_UCCE_FLG 0x0200 439#define UCC_UART_UCCE_BRKE 0x0040
405#define UCC_SLOW_UCCE_AB 0x0200 440#define UCC_UART_UCCE_BRKS 0x0020
406#define UCC_SLOW_UCCE_IDLE 0x0100 441#define UCC_UART_UCCE_CCR 0x0008
407#define UCC_SLOW_UCCE_GRA 0x0080 442#define UCC_UART_UCCE_BSY 0x0004
408#define UCC_SLOW_UCCE_TXE 0x0010 443#define UCC_UART_UCCE_TX 0x0002
409#define UCC_SLOW_UCCE_RXF 0x0008 444#define UCC_UART_UCCE_RX 0x0001
410#define UCC_SLOW_UCCE_CCR 0x0008 445
411#define UCC_SLOW_UCCE_RCH 0x0008 446/* HDLC Slow UCC Event Register (UCCE) */
412#define UCC_SLOW_UCCE_BSY 0x0004 447#define UCC_HDLC_UCCE_GLR 0x1000
413#define UCC_SLOW_UCCE_TXB 0x0002 448#define UCC_HDLC_UCCE_GLT 0x0800
414#define UCC_SLOW_UCCE_TX 0x0002 449#define UCC_HDLC_UCCE_IDLE 0x0100
415#define UCC_SLOW_UCCE_RX 0x0001 450#define UCC_HDLC_UCCE_BRKE 0x0040
416#define UCC_SLOW_UCCE_GOV 0x0001 451#define UCC_HDLC_UCCE_BRKS 0x0020
417#define UCC_SLOW_UCCE_GUN 0x0002 452#define UCC_HDLC_UCCE_TXE 0x0010
418#define UCC_SLOW_UCCE_GINT 0x0004 453#define UCC_HDLC_UCCE_RXF 0x0008
419#define UCC_SLOW_UCCE_IQOV 0x0008 454#define UCC_HDLC_UCCE_BSY 0x0004
420 455#define UCC_HDLC_UCCE_TXB 0x0002
421#define UCC_SLOW_UCCE_HDLC_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 456#define UCC_HDLC_UCCE_RXB 0x0001
422 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF | \ 457
423 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) 458/* BISYNC Slow UCC Event Register (UCCE) */
424#define UCC_SLOW_UCCE_ENET_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 459#define UCC_BISYNC_UCCE_GRA 0x0080
425 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_RXF) 460#define UCC_BISYNC_UCCE_TXE 0x0010
426#define UCC_SLOW_UCCE_TRANS_SET (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 461#define UCC_BISYNC_UCCE_RCH 0x0008
427 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \ 462#define UCC_BISYNC_UCCE_BSY 0x0004
428 UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) 463#define UCC_BISYNC_UCCE_TXB 0x0002
429#define UCC_SLOW_UCCE_UART_SET (UCC_SLOW_UCCE_BSY | UCC_SLOW_UCCE_GRA | \ 464#define UCC_BISYNC_UCCE_RXB 0x0001
430 UCC_SLOW_UCCE_TXB | UCC_SLOW_UCCE_TX | UCC_SLOW_UCCE_RX | \ 465
431 UCC_SLOW_UCCE_GLT | UCC_SLOW_UCCE_GLR) 466/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
432#define UCC_SLOW_UCCE_QMC_SET (UCC_SLOW_UCCE_IQOV | UCC_SLOW_UCCE_GINT | \ 467#define UCC_GETH_UCCE_MPD 0x80000000
433 UCC_SLOW_UCCE_GUN | UCC_SLOW_UCCE_GOV) 468#define UCC_GETH_UCCE_SCAR 0x40000000
434 469#define UCC_GETH_UCCE_GRA 0x20000000
435#define UCC_SLOW_UCCE_OTHER (UCC_SLOW_UCCE_TXE | UCC_SLOW_UCCE_BSY | \ 470#define UCC_GETH_UCCE_CBPR 0x10000000
436 UCC_SLOW_UCCE_GRA | UCC_SLOW_UCCE_DCC | UCC_SLOW_UCCE_GLT | \ 471#define UCC_GETH_UCCE_BSY 0x08000000
437 UCC_SLOW_UCCE_GLR) 472#define UCC_GETH_UCCE_RXC 0x04000000
438 473#define UCC_GETH_UCCE_TXC 0x02000000
439#define UCC_SLOW_INTR_TX UCC_SLOW_UCCE_TXB 474#define UCC_GETH_UCCE_TXE 0x01000000
440#define UCC_SLOW_INTR_RX (UCC_SLOW_UCCE_RXF | UCC_SLOW_UCCE_RX) 475#define UCC_GETH_UCCE_TXB7 0x00800000
441#define UCC_SLOW_INTR (UCC_SLOW_INTR_TX | UCC_SLOW_INTR_RX) 476#define UCC_GETH_UCCE_TXB6 0x00400000
477#define UCC_GETH_UCCE_TXB5 0x00200000
478#define UCC_GETH_UCCE_TXB4 0x00100000
479#define UCC_GETH_UCCE_TXB3 0x00080000
480#define UCC_GETH_UCCE_TXB2 0x00040000
481#define UCC_GETH_UCCE_TXB1 0x00020000
482#define UCC_GETH_UCCE_TXB0 0x00010000
483#define UCC_GETH_UCCE_RXB7 0x00008000
484#define UCC_GETH_UCCE_RXB6 0x00004000
485#define UCC_GETH_UCCE_RXB5 0x00002000
486#define UCC_GETH_UCCE_RXB4 0x00001000
487#define UCC_GETH_UCCE_RXB3 0x00000800
488#define UCC_GETH_UCCE_RXB2 0x00000400
489#define UCC_GETH_UCCE_RXB1 0x00000200
490#define UCC_GETH_UCCE_RXB0 0x00000100
491#define UCC_GETH_UCCE_RXF7 0x00000080
492#define UCC_GETH_UCCE_RXF6 0x00000040
493#define UCC_GETH_UCCE_RXF5 0x00000020
494#define UCC_GETH_UCCE_RXF4 0x00000010
495#define UCC_GETH_UCCE_RXF3 0x00000008
496#define UCC_GETH_UCCE_RXF2 0x00000004
497#define UCC_GETH_UCCE_RXF1 0x00000002
498#define UCC_GETH_UCCE_RXF0 0x00000001
499
500/* UPSMR, when used as a UART */
501#define UCC_UART_UPSMR_FLC 0x8000
502#define UCC_UART_UPSMR_SL 0x4000
503#define UCC_UART_UPSMR_CL_MASK 0x3000
504#define UCC_UART_UPSMR_CL_8 0x3000
505#define UCC_UART_UPSMR_CL_7 0x2000
506#define UCC_UART_UPSMR_CL_6 0x1000
507#define UCC_UART_UPSMR_CL_5 0x0000
508#define UCC_UART_UPSMR_UM_MASK 0x0c00
509#define UCC_UART_UPSMR_UM_NORMAL 0x0000
510#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
511#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
512#define UCC_UART_UPSMR_FRZ 0x0200
513#define UCC_UART_UPSMR_RZS 0x0100
514#define UCC_UART_UPSMR_SYN 0x0080
515#define UCC_UART_UPSMR_DRT 0x0040
516#define UCC_UART_UPSMR_PEN 0x0010
517#define UCC_UART_UPSMR_RPM_MASK 0x000c
518#define UCC_UART_UPSMR_RPM_ODD 0x0000
519#define UCC_UART_UPSMR_RPM_LOW 0x0004
520#define UCC_UART_UPSMR_RPM_EVEN 0x0008
521#define UCC_UART_UPSMR_RPM_HIGH 0x000C
522#define UCC_UART_UPSMR_TPM_MASK 0x0003
523#define UCC_UART_UPSMR_TPM_ODD 0x0000
524#define UCC_UART_UPSMR_TPM_LOW 0x0001
525#define UCC_UART_UPSMR_TPM_EVEN 0x0002
526#define UCC_UART_UPSMR_TPM_HIGH 0x0003
442 527
443/* UCC Transmit On Demand Register (UTODR) */ 528/* UCC Transmit On Demand Register (UTODR) */
444#define UCC_SLOW_TOD 0x8000 529#define UCC_SLOW_TOD 0x8000
445#define UCC_FAST_TOD 0x8000 530#define UCC_FAST_TOD 0x8000
446 531
532/* UCC Bus Mode Register masks */
533/* Not to be confused with the Bundle Mode Register */
534#define UCC_BMR_GBL 0x20
535#define UCC_BMR_BO_BE 0x10
536#define UCC_BMR_CETM 0x04
537#define UCC_BMR_DTB 0x02
538#define UCC_BMR_BDB 0x01
539
447/* Function code masks */ 540/* Function code masks */
448#define FC_GBL 0x20 541#define FC_GBL 0x20
449#define FC_DTB_LCL 0x02 542#define FC_DTB_LCL 0x02
diff --git a/include/asm-powerpc/ucc.h b/include/asm-powerpc/ucc.h
index afe3076bdc03..46b09ba6bead 100644
--- a/include/asm-powerpc/ucc.h
+++ b/include/asm-powerpc/ucc.h
@@ -25,58 +25,38 @@
25/* Slow or fast type for UCCs. 25/* Slow or fast type for UCCs.
26*/ 26*/
27enum ucc_speed_type { 27enum ucc_speed_type {
28 UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW 28 UCC_SPEED_TYPE_FAST = UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX,
29}; 29 UCC_SPEED_TYPE_SLOW = UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX
30
31/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
32*/
33enum ucc_pram_initial_offset {
34 UCC_PRAM_OFFSET_UCC1 = 0x8400,
35 UCC_PRAM_OFFSET_UCC2 = 0x8500,
36 UCC_PRAM_OFFSET_UCC3 = 0x8600,
37 UCC_PRAM_OFFSET_UCC4 = 0x9000,
38 UCC_PRAM_OFFSET_UCC5 = 0x8000,
39 UCC_PRAM_OFFSET_UCC6 = 0x8100,
40 UCC_PRAM_OFFSET_UCC7 = 0x8200,
41 UCC_PRAM_OFFSET_UCC8 = 0x8300
42}; 30};
43 31
44/* ucc_set_type 32/* ucc_set_type
45 * Sets UCC to slow or fast mode. 33 * Sets UCC to slow or fast mode.
46 * 34 *
47 * ucc_num - (In) number of UCC (0-7). 35 * ucc_num - (In) number of UCC (0-7).
48 * regs - (In) pointer to registers base for the UCC.
49 * speed - (In) slow or fast mode for UCC. 36 * speed - (In) slow or fast mode for UCC.
50 */ 37 */
51int ucc_set_type(int ucc_num, struct ucc_common *regs, 38int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed);
52 enum ucc_speed_type speed);
53
54/* ucc_init_guemr
55 * Init the Guemr register.
56 *
57 * regs - (In) pointer to registers base for the UCC.
58 */
59int ucc_init_guemr(struct ucc_common *regs);
60 39
61int ucc_set_qe_mux_mii_mng(int ucc_num); 40int ucc_set_qe_mux_mii_mng(unsigned int ucc_num);
62 41
63int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode); 42int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
43 enum comm_dir mode);
64 44
65int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask); 45int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask);
66 46
67/* QE MUX clock routing for UCC 47/* QE MUX clock routing for UCC
68*/ 48*/
69static inline int ucc_set_qe_mux_grant(int ucc_num, int set) 49static inline int ucc_set_qe_mux_grant(unsigned int ucc_num, int set)
70{ 50{
71 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT); 51 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
72} 52}
73 53
74static inline int ucc_set_qe_mux_tsa(int ucc_num, int set) 54static inline int ucc_set_qe_mux_tsa(unsigned int ucc_num, int set)
75{ 55{
76 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA); 56 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
77} 57}
78 58
79static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set) 59static inline int ucc_set_qe_mux_bkpt(unsigned int ucc_num, int set)
80{ 60{
81 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT); 61 return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
82} 62}
diff --git a/include/asm-powerpc/ucc_slow.h b/include/asm-powerpc/ucc_slow.h
index fdaac9d762bb..0980e6ad335b 100644
--- a/include/asm-powerpc/ucc_slow.h
+++ b/include/asm-powerpc/ucc_slow.h
@@ -148,9 +148,10 @@ enum ucc_slow_diag_mode {
148 148
149struct ucc_slow_info { 149struct ucc_slow_info {
150 int ucc_num; 150 int ucc_num;
151 int protocol; /* QE_CR_PROTOCOL_xxx */
151 enum qe_clock rx_clock; 152 enum qe_clock rx_clock;
152 enum qe_clock tx_clock; 153 enum qe_clock tx_clock;
153 u32 regs; 154 phys_addr_t regs;
154 int irq; 155 int irq;
155 u16 uccm_mask; 156 u16 uccm_mask;
156 int data_mem_part; 157 int data_mem_part;
@@ -186,7 +187,7 @@ struct ucc_slow_info {
186 187
187struct ucc_slow_private { 188struct ucc_slow_private {
188 struct ucc_slow_info *us_info; 189 struct ucc_slow_info *us_info;
189 struct ucc_slow *us_regs; /* a pointer to memory map of UCC regs */ 190 struct ucc_slow __iomem *us_regs; /* Ptr to memory map of UCC regs */
190 struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */ 191 struct ucc_slow_pram *us_pram; /* a pointer to the parameter RAM */
191 u32 us_pram_offset; 192 u32 us_pram_offset;
192 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */ 193 int enabled_tx; /* Whether channel is enabled for Tx (ENT) */
@@ -277,12 +278,12 @@ void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs);
277 */ 278 */
278void ucc_slow_stop_tx(struct ucc_slow_private * uccs); 279void ucc_slow_stop_tx(struct ucc_slow_private * uccs);
279 280
280/* ucc_slow_restart_x 281/* ucc_slow_restart_tx
281 * Restarts transmitting on a specified slow UCC. 282 * Restarts transmitting on a specified slow UCC.
282 * 283 *
283 * uccs - (In) pointer to the slow UCC structure. 284 * uccs - (In) pointer to the slow UCC structure.
284 */ 285 */
285void ucc_slow_restart_x(struct ucc_slow_private * uccs); 286void ucc_slow_restart_tx(struct ucc_slow_private *uccs);
286 287
287u32 ucc_slow_get_qe_cr_subblock(int uccs_num); 288u32 ucc_slow_get_qe_cr_subblock(int uccs_num);
288 289
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 03:18:44 -0500