7 files changed, 327 insertions, 169 deletions

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b9b4b593b9af..deeee9cf09aa 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -217,7 +217,9 @@ dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
         r8a73a4-ape6evm-reference.dtb \
         sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb
-dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
+        socfpga_cyclone5_socdk.dtb \
+        socfpga_cyclone5_sockit.dtb \
         socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
         spear1340-evb.dtb
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index e273fa993b8c..6d09b8d42fdd 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -147,7 +147,7 @@
                                                         reg = <0x58>;
                                                 };
 
-                                                cfg_s2f_usr0_clk: cfg_s2f_usr0_clk {
+                                                cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&main_pll>;
@@ -198,7 +198,7 @@
                                                         reg = <0x98>;
                                                 };
 
-                                                s2f_usr1_clk: s2f_usr1_clk {
+                                                h2f_usr1_clk: h2f_usr1_clk {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&periph_pll>;
@@ -235,7 +235,7 @@
                                                         reg = <0xD0>;
                                                 };
 
-                                                s2f_usr2_clk: s2f_usr2_clk {
+                                                h2f_usr2_clk: h2f_usr2_clk {
                                                         #clock-cells = <0>;
                                                         compatible = "altr,socfpga-perip-clk";
                                                         clocks = <&sdram_pll>;
@@ -243,197 +243,197 @@
                                                 };
                                         };
 
-                                mpu_periph_clk: mpu_periph_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mpuclk>;
-                                        fixed-divider = <4>;
+                                        mpu_periph_clk: mpu_periph_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mpuclk>;
+                                                fixed-divider = <4>;
                                         };
 
-                                mpu_l2_ram_clk: mpu_l2_ram_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mpuclk>;
-                                        fixed-divider = <2>;
+                                        mpu_l2_ram_clk: mpu_l2_ram_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mpuclk>;
+                                                fixed-divider = <2>;
                                         };
 
-                                l4_main_clk: l4_main_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mainclk>;
-                                        clk-gate = <0x60 0>;
+                                        l4_main_clk: l4_main_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mainclk>;
+                                                clk-gate = <0x60 0>;
                                         };
 
-                                l3_main_clk: l3_main_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mainclk>;
+                                        l3_main_clk: l3_main_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mainclk>;
                                         };
 
-                                l3_mp_clk: l3_mp_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mainclk>;
-                                        div-reg = <0x64 0 2>;
-                                        clk-gate = <0x60 1>;
+                                        l3_mp_clk: l3_mp_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mainclk>;
+                                                div-reg = <0x64 0 2>;
+                                                clk-gate = <0x60 1>;
                                         };
 
-                                l3_sp_clk: l3_sp_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mainclk>;
-                                        div-reg = <0x64 2 2>;
-                                };
+                                        l3_sp_clk: l3_sp_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mainclk>;
+                                                div-reg = <0x64 2 2>;
+                                        };
 
-                                l4_mp_clk: l4_mp_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mainclk>, <&per_base_clk>;
-                                        div-reg = <0x64 4 3>;
-                                        clk-gate = <0x60 2>;
+                                        l4_mp_clk: l4_mp_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mainclk>, <&per_base_clk>;
+                                                div-reg = <0x64 4 3>;
+                                                clk-gate = <0x60 2>;
                                         };
 
-                                l4_sp_clk: l4_sp_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&mainclk>, <&per_base_clk>;
-                                        div-reg = <0x64 7 3>;
-                                        clk-gate = <0x60 3>;
+                                        l4_sp_clk: l4_sp_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&mainclk>, <&per_base_clk>;
+                                                div-reg = <0x64 7 3>;
+                                                clk-gate = <0x60 3>;
                                         };
 
-                                dbg_at_clk: dbg_at_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&dbg_base_clk>;
-                                        div-reg = <0x68 0 2>;
-                                        clk-gate = <0x60 4>;
+                                        dbg_at_clk: dbg_at_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&dbg_base_clk>;
+                                                div-reg = <0x68 0 2>;
+                                                clk-gate = <0x60 4>;
                                         };
 
-                                dbg_clk: dbg_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&dbg_base_clk>;
-                                        div-reg = <0x68 2 2>;
-                                        clk-gate = <0x60 5>;
+                                        dbg_clk: dbg_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&dbg_base_clk>;
+                                                div-reg = <0x68 2 2>;
+                                                clk-gate = <0x60 5>;
                                         };
 
-                                dbg_trace_clk: dbg_trace_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&dbg_base_clk>;
-                                        div-reg = <0x6C 0 3>;
-                                        clk-gate = <0x60 6>;
+                                        dbg_trace_clk: dbg_trace_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&dbg_base_clk>;
+                                                div-reg = <0x6C 0 3>;
+                                                clk-gate = <0x60 6>;
                                         };
 
-                                dbg_timer_clk: dbg_timer_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&dbg_base_clk>;
-                                        clk-gate = <0x60 7>;
+                                        dbg_timer_clk: dbg_timer_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&dbg_base_clk>;
+                                                clk-gate = <0x60 7>;
                                         };
 
-                                cfg_clk: cfg_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&cfg_s2f_usr0_clk>;
-                                        clk-gate = <0x60 8>;
+                                        cfg_clk: cfg_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&cfg_h2f_usr0_clk>;
+                                                clk-gate = <0x60 8>;
                                         };
 
-                                s2f_user0_clk: s2f_user0_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&cfg_s2f_usr0_clk>;
-                                        clk-gate = <0x60 9>;
+                                        h2f_user0_clk: h2f_user0_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&cfg_h2f_usr0_clk>;
+                                                clk-gate = <0x60 9>;
                                         };
 
-                                emac_0_clk: emac_0_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&emac0_clk>;
-                                        clk-gate = <0xa0 0>;
+                                        emac_0_clk: emac_0_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&emac0_clk>;
+                                                clk-gate = <0xa0 0>;
                                         };
 
-                                emac_1_clk: emac_1_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&emac1_clk>;
-                                        clk-gate = <0xa0 1>;
+                                        emac_1_clk: emac_1_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&emac1_clk>;
+                                                clk-gate = <0xa0 1>;
                                         };
 
-                                usb_mp_clk: usb_mp_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&per_base_clk>;
-                                        clk-gate = <0xa0 2>;
-                                        div-reg = <0xa4 0 3>;
+                                        usb_mp_clk: usb_mp_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&per_base_clk>;
+                                                clk-gate = <0xa0 2>;
+                                                div-reg = <0xa4 0 3>;
                                         };
 
-                                spi_m_clk: spi_m_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&per_base_clk>;
-                                        clk-gate = <0xa0 3>;
-                                        div-reg = <0xa4 3 3>;
+                                        spi_m_clk: spi_m_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&per_base_clk>;
+                                                clk-gate = <0xa0 3>;
+                                                div-reg = <0xa4 3 3>;
                                         };
 
-                                can0_clk: can0_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&per_base_clk>;
-                                        clk-gate = <0xa0 4>;
-                                        div-reg = <0xa4 6 3>;
+                                        can0_clk: can0_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&per_base_clk>;
+                                                clk-gate = <0xa0 4>;
+                                                div-reg = <0xa4 6 3>;
                                         };
 
-                                can1_clk: can1_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&per_base_clk>;
-                                        clk-gate = <0xa0 5>;
-                                        div-reg = <0xa4 9 3>;
+                                        can1_clk: can1_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&per_base_clk>;
+                                                clk-gate = <0xa0 5>;
+                                                div-reg = <0xa4 9 3>;
                                         };
 
-                                gpio_db_clk: gpio_db_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&per_base_clk>;
-                                        clk-gate = <0xa0 6>;
-                                        div-reg = <0xa8 0 24>;
+                                        gpio_db_clk: gpio_db_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&per_base_clk>;
+                                                clk-gate = <0xa0 6>;
+                                                div-reg = <0xa8 0 24>;
                                         };
 
-                                s2f_user1_clk: s2f_user1_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&s2f_usr1_clk>;
-                                        clk-gate = <0xa0 7>;
+                                        h2f_user1_clk: h2f_user1_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&h2f_usr1_clk>;
+                                                clk-gate = <0xa0 7>;
                                         };
 
-                                sdmmc_clk: sdmmc_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
-                                        clk-gate = <0xa0 8>;
+                                        sdmmc_clk: sdmmc_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                                clk-gate = <0xa0 8>;
                                         };
 
-                                nand_x_clk: nand_x_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
-                                        clk-gate = <0xa0 9>;
+                                        nand_x_clk: nand_x_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                                clk-gate = <0xa0 9>;
                                         };
 
-                                nand_clk: nand_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
-                                        clk-gate = <0xa0 10>;
-                                        fixed-divider = <4>;
+                                        nand_clk: nand_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+                                                clk-gate = <0xa0 10>;
+                                                fixed-divider = <4>;
                                         };
 
-                                qspi_clk: qspi_clk {
-                                        #clock-cells = <0>;
-                                        compatible = "altr,socfpga-gate-clk";
-                                        clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
-                                        clk-gate = <0xa0 11>;
+                                        qspi_clk: qspi_clk {
+                                                #clock-cells = <0>;
+                                                compatible = "altr,socfpga-gate-clk";
+                                                clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
+                                                clk-gate = <0xa0 11>;
                                         };
                                 };
                         };
@@ -473,6 +473,7 @@
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0xfffec600 0x100>;
                         interrupts = <1 13 0xf04>;
+                        clocks = <&mpu_periph_clk>;
                 };
 
                 timer0: timer0@ffc08000 {
@@ -516,9 +517,9 @@
                 };
 
                 rstmgr@ffd05000 {
-                                compatible = "altr,rst-mgr";
-                                reg = <0xffd05000 0x1000>;
-                        };
+                        compatible = "altr,rst-mgr";
+                        reg = <0xffd05000 0x1000>;
+                };
 
                 sysmgr@ffd08000 {
                                 compatible = "altr,sys-mgr";
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
new file mode 100644
index 000000000000..a85b4043f888
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -0,0 +1,58 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+/include/ "socfpga.dtsi"
+
+/ {
+        soc {
+                clkmgr@ffd04000 {
+                        clocks {
+                                osc1 {
+                                        clock-frequency = <25000000>;
+                                };
+                        };
+                };
+
+                serial0@ffc02000 {
+                        clock-frequency = <100000000>;
+                };
+
+                serial1@ffc03000 {
+                        clock-frequency = <100000000>;
+                };
+
+                sysmgr@ffd08000 {
+                        cpu1-start-addr = <0xffd080c4>;
+                };
+
+                timer0@ffc08000 {
+                        clock-frequency = <100000000>;
+                };
+
+                timer1@ffc09000 {
+                        clock-frequency = <100000000>;
+                };
+
+                timer2@ffd00000 {
+                        clock-frequency = <25000000>;
+                };
+
+                timer3@ffd01000 {
+                        clock-frequency = <25000000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
new file mode 100644
index 000000000000..5beffb2265f4
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -0,0 +1,40 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "socfpga_arria5.dtsi"
+
+/ {
+        model = "Altera SOCFPGA Arria V SoC Development Kit";
+        compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x40000000>; /* 1GB */
+        };
+
+        aliases {
+                /* this allow the ethaddr uboot environmnet variable contents
+                * to be added to the gmac1 device tree blob.
+                */
+                ethernet0 = &gmac1;
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dts b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 973999d2c697..a8716f6dbe2e 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -19,26 +19,6 @@
 /include/ "socfpga.dtsi"
 
 / {
-        model = "Altera SOCFPGA Cyclone V";
-        compatible = "altr,socfpga-cyclone5", "altr,socfpga";
-
-        chosen {
-                bootargs = "console=ttyS0,57600";
-        };
-
-        memory {
-                name = "memory";
-                device_type = "memory";
-                reg = <0x0 0x40000000>; /* 1GB */
-        };
-
-        aliases {
-                /* this allow the ethaddr uboot environmnet variable contents
-                 * to be added to the gmac1 device tree blob.
-                 */
-                ethernet0 = &gmac1;
-        };
-
         soc {
                 clkmgr@ffd04000 {
                         clocks {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
new file mode 100644
index 000000000000..2ee52ab8cabb
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -0,0 +1,40 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "socfpga_cyclone5.dtsi"
+
+/ {
+        model = "Altera SOCFPGA Cyclone V SoC Development Kit";
+        compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x40000000>; /* 1GB */
+        };
+
+        aliases {
+                /* this allow the ethaddr uboot environmnet variable contents
+                 * to be added to the gmac1 device tree blob.
+                 */
+                ethernet0 = &gmac1;
+        };
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
new file mode 100644
index 000000000000..50b99a2c12ae
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "socfpga_cyclone5.dtsi"
+
+/ {
+        model = "Terasic SoCkit";
+        compatible = "altr,socfpga-cyclone5", "altr,socfpga";
+
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x40000000>; /* 1GB */
+        };
+};
+
+&gmac1 {
+        status = "okay";
+};