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-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts4
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts9
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts4
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts4
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi154
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi128
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts4
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi128
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts18
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi212
10 files changed, 622 insertions, 43 deletions
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index eb4d73b6a090..d4b081d6a167 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -18,10 +18,6 @@
18 model = "Mele A1000"; 18 model = "Mele A1000";
19 compatible = "mele,a1000", "allwinner,sun4i-a10"; 19 compatible = "mele,a1000", "allwinner,sun4i-a10";
20 20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 soc@01c00000 { 21 soc@01c00000 {
26 emac: ethernet@01c0b000 { 22 emac: ethernet@01c0b000 {
27 pinctrl-names = "default"; 23 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 425a7db898c5..b139ee6bcf99 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -17,15 +17,6 @@
17 model = "Cubietech Cubieboard"; 17 model = "Cubietech Cubieboard";
18 compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10"; 18 compatible = "cubietech,a10-cubieboard", "allwinner,sun4i-a10";
19 19
20 aliases {
21 serial0 = &uart0;
22 serial1 = &uart1;
23 };
24
25 chosen {
26 bootargs = "earlyprintk console=ttyS0,115200";
27 };
28
29 soc@01c00000 { 20 soc@01c00000 {
30 emac: ethernet@01c0b000 { 21 emac: ethernet@01c0b000 {
31 pinctrl-names = "default"; 22 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index b3ae51fa9372..3a1595f67823 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -18,10 +18,6 @@
18 model = "Miniand Hackberry"; 18 model = "Miniand Hackberry";
19 compatible = "miniand,hackberry", "allwinner,sun4i-a10"; 19 compatible = "miniand,hackberry", "allwinner,sun4i-a10";
20 20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc@01c00000 { 21 soc@01c00000 {
26 emac: ethernet@01c0b000 { 22 emac: ethernet@01c0b000 {
27 pinctrl-names = "default"; 23 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 0c1447c68059..70b3323caf1a 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -18,10 +18,6 @@
18 model = "PineRiver Mini X-Plus"; 18 model = "PineRiver Mini X-Plus";
19 compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10"; 19 compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
20 20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc@01c00000 { 21 soc@01c00000 {
26 uart0: serial@01c28000 { 22 uart0: serial@01c28000 {
27 pinctrl-names = "default"; 23 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 0bf70ee041ed..040bb0eba152 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -17,6 +17,8 @@
17 17
18 aliases { 18 aliases {
19 ethernet0 = &emac; 19 ethernet0 = &emac;
20 serial0 = &uart0;
21 serial1 = &uart1;
20 }; 22 };
21 23
22 cpus { 24 cpus {
@@ -70,6 +72,29 @@
70 clocks = <&osc24M>; 72 clocks = <&osc24M>;
71 }; 73 };
72 74
75 pll4: pll4@01c20018 {
76 #clock-cells = <0>;
77 compatible = "allwinner,sun4i-pll1-clk";
78 reg = <0x01c20018 0x4>;
79 clocks = <&osc24M>;
80 };
81
82 pll5: pll5@01c20020 {
83 #clock-cells = <1>;
84 compatible = "allwinner,sun4i-pll5-clk";
85 reg = <0x01c20020 0x4>;
86 clocks = <&osc24M>;
87 clock-output-names = "pll5_ddr", "pll5_other";
88 };
89
90 pll6: pll6@01c20028 {
91 #clock-cells = <1>;
92 compatible = "allwinner,sun4i-pll6-clk";
93 reg = <0x01c20028 0x4>;
94 clocks = <&osc24M>;
95 clock-output-names = "pll6_sata", "pll6_other", "pll6";
96 };
97
73 /* dummy is 200M */ 98 /* dummy is 200M */
74 cpu: cpu@01c20054 { 99 cpu: cpu@01c20054 {
75 #clock-cells = <0>; 100 #clock-cells = <0>;
@@ -135,12 +160,11 @@
135 "apb0_ir1", "apb0_keypad"; 160 "apb0_ir1", "apb0_keypad";
136 }; 161 };
137 162
138 /* dummy is pll62 */
139 apb1_mux: apb1_mux@01c20058 { 163 apb1_mux: apb1_mux@01c20058 {
140 #clock-cells = <0>; 164 #clock-cells = <0>;
141 compatible = "allwinner,sun4i-apb1-mux-clk"; 165 compatible = "allwinner,sun4i-apb1-mux-clk";
142 reg = <0x01c20058 0x4>; 166 reg = <0x01c20058 0x4>;
143 clocks = <&osc24M>, <&dummy>, <&osc32k>; 167 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
144 }; 168 };
145 169
146 apb1: apb1@01c20058 { 170 apb1: apb1@01c20058 {
@@ -162,6 +186,126 @@
162 "apb1_uart4", "apb1_uart5", "apb1_uart6", 186 "apb1_uart4", "apb1_uart5", "apb1_uart6",
163 "apb1_uart7"; 187 "apb1_uart7";
164 }; 188 };
189
190 nand_clk: clk@01c20080 {
191 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk";
193 reg = <0x01c20080 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "nand";
196 };
197
198 ms_clk: clk@01c20084 {
199 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk";
201 reg = <0x01c20084 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "ms";
204 };
205
206 mmc0_clk: clk@01c20088 {
207 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk";
209 reg = <0x01c20088 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc0";
212 };
213
214 mmc1_clk: clk@01c2008c {
215 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk";
217 reg = <0x01c2008c 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "mmc1";
220 };
221
222 mmc2_clk: clk@01c20090 {
223 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk";
225 reg = <0x01c20090 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "mmc2";
228 };
229
230 mmc3_clk: clk@01c20094 {
231 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk";
233 reg = <0x01c20094 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "mmc3";
236 };
237
238 ts_clk: clk@01c20098 {
239 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk";
241 reg = <0x01c20098 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "ts";
244 };
245
246 ss_clk: clk@01c2009c {
247 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk";
249 reg = <0x01c2009c 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "ss";
252 };
253
254 spi0_clk: clk@01c200a0 {
255 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk";
257 reg = <0x01c200a0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "spi0";
260 };
261
262 spi1_clk: clk@01c200a4 {
263 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk";
265 reg = <0x01c200a4 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "spi1";
268 };
269
270 spi2_clk: clk@01c200a8 {
271 #clock-cells = <0>;
272 compatible = "allwinner,sun4i-mod0-clk";
273 reg = <0x01c200a8 0x4>;
274 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
275 clock-output-names = "spi2";
276 };
277
278 pata_clk: clk@01c200ac {
279 #clock-cells = <0>;
280 compatible = "allwinner,sun4i-mod0-clk";
281 reg = <0x01c200ac 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "pata";
284 };
285
286 ir0_clk: clk@01c200b0 {
287 #clock-cells = <0>;
288 compatible = "allwinner,sun4i-mod0-clk";
289 reg = <0x01c200b0 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "ir0";
292 };
293
294 ir1_clk: clk@01c200b4 {
295 #clock-cells = <0>;
296 compatible = "allwinner,sun4i-mod0-clk";
297 reg = <0x01c200b4 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
299 clock-output-names = "ir1";
300 };
301
302 spi3_clk: clk@01c200d4 {
303 #clock-cells = <0>;
304 compatible = "allwinner,sun4i-mod0-clk";
305 reg = <0x01c200d4 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "spi3";
308 };
165 }; 309 };
166 310
167 soc@01c00000 { 311 soc@01c00000 {
@@ -281,6 +425,12 @@
281 reg = <0x01c23800 0x10>; 425 reg = <0x01c23800 0x10>;
282 }; 426 };
283 427
428 rtp: rtp@01c25000 {
429 compatible = "allwinner,sun4i-ts";
430 reg = <0x01c25000 0x100>;
431 interrupts = <29>;
432 };
433
284 uart0: serial@01c28000 { 434 uart0: serial@01c28000 {
285 compatible = "snps,dw-apb-uart"; 435 compatible = "snps,dw-apb-uart";
286 reg = <0x01c28000 0x400>; 436 reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index b4764be10a60..9bb3a0d493de 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -67,6 +67,29 @@
67 clocks = <&osc24M>; 67 clocks = <&osc24M>;
68 }; 68 };
69 69
70 pll4: pll4@01c20018 {
71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk";
73 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>;
75 };
76
77 pll5: pll5@01c20020 {
78 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk";
80 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other";
83 };
84
85 pll6: pll6@01c20028 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk";
88 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6";
91 };
92
70 /* dummy is 200M */ 93 /* dummy is 200M */
71 cpu: cpu@01c20054 { 94 cpu: cpu@01c20054 {
72 #clock-cells = <0>; 95 #clock-cells = <0>;
@@ -127,12 +150,11 @@
127 "apb0_ir", "apb0_keypad"; 150 "apb0_ir", "apb0_keypad";
128 }; 151 };
129 152
130 /* dummy is pll62 */
131 apb1_mux: apb1_mux@01c20058 { 153 apb1_mux: apb1_mux@01c20058 {
132 #clock-cells = <0>; 154 #clock-cells = <0>;
133 compatible = "allwinner,sun4i-apb1-mux-clk"; 155 compatible = "allwinner,sun4i-apb1-mux-clk";
134 reg = <0x01c20058 0x4>; 156 reg = <0x01c20058 0x4>;
135 clocks = <&osc24M>, <&dummy>, <&osc32k>; 157 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
136 }; 158 };
137 159
138 apb1: apb1@01c20058 { 160 apb1: apb1@01c20058 {
@@ -151,6 +173,102 @@
151 "apb1_i2c2", "apb1_uart0", "apb1_uart1", 173 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
152 "apb1_uart2", "apb1_uart3"; 174 "apb1_uart2", "apb1_uart3";
153 }; 175 };
176
177 nand_clk: clk@01c20080 {
178 #clock-cells = <0>;
179 compatible = "allwinner,sun4i-mod0-clk";
180 reg = <0x01c20080 0x4>;
181 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
182 clock-output-names = "nand";
183 };
184
185 ms_clk: clk@01c20084 {
186 #clock-cells = <0>;
187 compatible = "allwinner,sun4i-mod0-clk";
188 reg = <0x01c20084 0x4>;
189 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 clock-output-names = "ms";
191 };
192
193 mmc0_clk: clk@01c20088 {
194 #clock-cells = <0>;
195 compatible = "allwinner,sun4i-mod0-clk";
196 reg = <0x01c20088 0x4>;
197 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
198 clock-output-names = "mmc0";
199 };
200
201 mmc1_clk: clk@01c2008c {
202 #clock-cells = <0>;
203 compatible = "allwinner,sun4i-mod0-clk";
204 reg = <0x01c2008c 0x4>;
205 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
206 clock-output-names = "mmc1";
207 };
208
209 mmc2_clk: clk@01c20090 {
210 #clock-cells = <0>;
211 compatible = "allwinner,sun4i-mod0-clk";
212 reg = <0x01c20090 0x4>;
213 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
214 clock-output-names = "mmc2";
215 };
216
217 ts_clk: clk@01c20098 {
218 #clock-cells = <0>;
219 compatible = "allwinner,sun4i-mod0-clk";
220 reg = <0x01c20098 0x4>;
221 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
222 clock-output-names = "ts";
223 };
224
225 ss_clk: clk@01c2009c {
226 #clock-cells = <0>;
227 compatible = "allwinner,sun4i-mod0-clk";
228 reg = <0x01c2009c 0x4>;
229 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
230 clock-output-names = "ss";
231 };
232
233 spi0_clk: clk@01c200a0 {
234 #clock-cells = <0>;
235 compatible = "allwinner,sun4i-mod0-clk";
236 reg = <0x01c200a0 0x4>;
237 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
238 clock-output-names = "spi0";
239 };
240
241 spi1_clk: clk@01c200a4 {
242 #clock-cells = <0>;
243 compatible = "allwinner,sun4i-mod0-clk";
244 reg = <0x01c200a4 0x4>;
245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
246 clock-output-names = "spi1";
247 };
248
249 spi2_clk: clk@01c200a8 {
250 #clock-cells = <0>;
251 compatible = "allwinner,sun4i-mod0-clk";
252 reg = <0x01c200a8 0x4>;
253 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
254 clock-output-names = "spi2";
255 };
256
257 ir0_clk: clk@01c200b0 {
258 #clock-cells = <0>;
259 compatible = "allwinner,sun4i-mod0-clk";
260 reg = <0x01c200b0 0x4>;
261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
262 clock-output-names = "ir0";
263 };
264
265 mbus_clk: clk@01c2015c {
266 #clock-cells = <0>;
267 compatible = "allwinner,sun4i-mod0-clk";
268 reg = <0x01c2015c 0x4>;
269 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
270 clock-output-names = "mbus";
271 };
154 }; 272 };
155 273
156 soc@01c00000 { 274 soc@01c00000 {
@@ -264,6 +382,12 @@
264 reg = <0x01c23800 0x10>; 382 reg = <0x01c23800 0x10>;
265 }; 383 };
266 384
385 rtp: rtp@01c25000 {
386 compatible = "allwinner,sun4i-ts";
387 reg = <0x01c25000 0x100>;
388 interrupts = <29>;
389 };
390
267 uart0: serial@01c28000 { 391 uart0: serial@01c28000 {
268 compatible = "snps,dw-apb-uart"; 392 compatible = "snps,dw-apb-uart";
269 reg = <0x01c28000 0x400>; 393 reg = <0x01c28000 0x400>;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 9e508dcc4245..a4ba5ff010cf 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -18,10 +18,6 @@
18 model = "Olimex A13-Olinuxino"; 18 model = "Olimex A13-Olinuxino";
19 compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13"; 19 compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
20 20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc@01c00000 { 21 soc@01c00000 {
26 pinctrl@01c20800 { 22 pinctrl@01c20800 {
27 led_pins_olinuxino: led_pins@0 { 23 led_pins_olinuxino: led_pins@0 {
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index ce8ef2a45be0..4dee9716deb4 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -67,6 +67,29 @@
67 clocks = <&osc24M>; 67 clocks = <&osc24M>;
68 }; 68 };
69 69
70 pll4: pll4@01c20018 {
71 #clock-cells = <0>;
72 compatible = "allwinner,sun4i-pll1-clk";
73 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>;
75 };
76
77 pll5: pll5@01c20020 {
78 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk";
80 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other";
83 };
84
85 pll6: pll6@01c20028 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk";
88 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6";
91 };
92
70 /* dummy is 200M */ 93 /* dummy is 200M */
71 cpu: cpu@01c20054 { 94 cpu: cpu@01c20054 {
72 #clock-cells = <0>; 95 #clock-cells = <0>;
@@ -125,12 +148,11 @@
125 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; 148 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
126 }; 149 };
127 150
128 /* dummy is pll6 */
129 apb1_mux: apb1_mux@01c20058 { 151 apb1_mux: apb1_mux@01c20058 {
130 #clock-cells = <0>; 152 #clock-cells = <0>;
131 compatible = "allwinner,sun4i-apb1-mux-clk"; 153 compatible = "allwinner,sun4i-apb1-mux-clk";
132 reg = <0x01c20058 0x4>; 154 reg = <0x01c20058 0x4>;
133 clocks = <&osc24M>, <&dummy>, <&osc32k>; 155 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
134 }; 156 };
135 157
136 apb1: apb1@01c20058 { 158 apb1: apb1@01c20058 {
@@ -148,6 +170,102 @@
148 clock-output-names = "apb1_i2c0", "apb1_i2c1", 170 clock-output-names = "apb1_i2c0", "apb1_i2c1",
149 "apb1_i2c2", "apb1_uart1", "apb1_uart3"; 171 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
150 }; 172 };
173
174 nand_clk: clk@01c20080 {
175 #clock-cells = <0>;
176 compatible = "allwinner,sun4i-mod0-clk";
177 reg = <0x01c20080 0x4>;
178 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
179 clock-output-names = "nand";
180 };
181
182 ms_clk: clk@01c20084 {
183 #clock-cells = <0>;
184 compatible = "allwinner,sun4i-mod0-clk";
185 reg = <0x01c20084 0x4>;
186 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
187 clock-output-names = "ms";
188 };
189
190 mmc0_clk: clk@01c20088 {
191 #clock-cells = <0>;
192 compatible = "allwinner,sun4i-mod0-clk";
193 reg = <0x01c20088 0x4>;
194 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
195 clock-output-names = "mmc0";
196 };
197
198 mmc1_clk: clk@01c2008c {
199 #clock-cells = <0>;
200 compatible = "allwinner,sun4i-mod0-clk";
201 reg = <0x01c2008c 0x4>;
202 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
203 clock-output-names = "mmc1";
204 };
205
206 mmc2_clk: clk@01c20090 {
207 #clock-cells = <0>;
208 compatible = "allwinner,sun4i-mod0-clk";
209 reg = <0x01c20090 0x4>;
210 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
211 clock-output-names = "mmc2";
212 };
213
214 ts_clk: clk@01c20098 {
215 #clock-cells = <0>;
216 compatible = "allwinner,sun4i-mod0-clk";
217 reg = <0x01c20098 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ts";
220 };
221
222 ss_clk: clk@01c2009c {
223 #clock-cells = <0>;
224 compatible = "allwinner,sun4i-mod0-clk";
225 reg = <0x01c2009c 0x4>;
226 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
227 clock-output-names = "ss";
228 };
229
230 spi0_clk: clk@01c200a0 {
231 #clock-cells = <0>;
232 compatible = "allwinner,sun4i-mod0-clk";
233 reg = <0x01c200a0 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "spi0";
236 };
237
238 spi1_clk: clk@01c200a4 {
239 #clock-cells = <0>;
240 compatible = "allwinner,sun4i-mod0-clk";
241 reg = <0x01c200a4 0x4>;
242 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
243 clock-output-names = "spi1";
244 };
245
246 spi2_clk: clk@01c200a8 {
247 #clock-cells = <0>;
248 compatible = "allwinner,sun4i-mod0-clk";
249 reg = <0x01c200a8 0x4>;
250 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
251 clock-output-names = "spi2";
252 };
253
254 ir0_clk: clk@01c200b0 {
255 #clock-cells = <0>;
256 compatible = "allwinner,sun4i-mod0-clk";
257 reg = <0x01c200b0 0x4>;
258 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
259 clock-output-names = "ir0";
260 };
261
262 mbus_clk: clk@01c2015c {
263 #clock-cells = <0>;
264 compatible = "allwinner,sun4i-mod0-clk";
265 reg = <0x01c2015c 0x4>;
266 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
267 clock-output-names = "mbus";
268 };
151 }; 269 };
152 270
153 soc@01c00000 { 271 soc@01c00000 {
@@ -227,6 +345,12 @@
227 reg = <0x01c23800 0x10>; 345 reg = <0x01c23800 0x10>;
228 }; 346 };
229 347
348 rtp: rtp@01c25000 {
349 compatible = "allwinner,sun4i-ts";
350 reg = <0x01c25000 0x100>;
351 interrupts = <29>;
352 };
353
230 uart1: serial@01c28400 { 354 uart1: serial@01c28400 {
231 compatible = "snps,dw-apb-uart"; 355 compatible = "snps,dw-apb-uart";
232 reg = <0x01c28400 0x400>; 356 reg = <0x01c28400 0x400>;
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index 8a1009d6c829..f9dcb61a5305 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -33,6 +33,24 @@
33 pinctrl-0 = <&uart0_pins_a>; 33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay"; 34 status = "okay";
35 }; 35 };
36
37 i2c0: i2c@01c2ac00 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&i2c0_pins_a>;
40 status = "okay";
41 };
42
43 i2c1: i2c@01c2b000 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&i2c1_pins_a>;
46 status = "okay";
47 };
48
49 i2c2: i2c@01c2b400 {
50 pinctrl-names = "default";
51 pinctrl-0 = <&i2c2_pins_a>;
52 status = "okay";
53 };
36 }; 54 };
37 55
38 leds { 56 leds {
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 74bf906ef786..0d5499808b3a 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -53,10 +53,11 @@
53 clock-frequency = <24000000>; 53 clock-frequency = <24000000>;
54 }; 54 };
55 55
56 osc32k: osc32k { 56 osc32k: clk@0 {
57 #clock-cells = <0>; 57 #clock-cells = <0>;
58 compatible = "fixed-clock"; 58 compatible = "fixed-clock";
59 clock-frequency = <32768>; 59 clock-frequency = <32768>;
60 clock-output-names = "osc32k";
60 }; 61 };
61 62
62 pll1: pll1@01c20000 { 63 pll1: pll1@01c20000 {
@@ -66,23 +67,34 @@
66 clocks = <&osc24M>; 67 clocks = <&osc24M>;
67 }; 68 };
68 69
69 /* 70 pll4: pll4@01c20018 {
70 * This is a dummy clock, to be used as placeholder on
71 * other mux clocks when a specific parent clock is not
72 * yet implemented. It should be dropped when the driver
73 * is complete.
74 */
75 pll6: pll6 {
76 #clock-cells = <0>; 71 #clock-cells = <0>;
77 compatible = "fixed-clock"; 72 compatible = "allwinner,sun4i-pll1-clk";
78 clock-frequency = <0>; 73 reg = <0x01c20018 0x4>;
74 clocks = <&osc24M>;
75 };
76
77 pll5: pll5@01c20020 {
78 #clock-cells = <1>;
79 compatible = "allwinner,sun4i-pll5-clk";
80 reg = <0x01c20020 0x4>;
81 clocks = <&osc24M>;
82 clock-output-names = "pll5_ddr", "pll5_other";
83 };
84
85 pll6: pll6@01c20028 {
86 #clock-cells = <1>;
87 compatible = "allwinner,sun4i-pll6-clk";
88 reg = <0x01c20028 0x4>;
89 clocks = <&osc24M>;
90 clock-output-names = "pll6_sata", "pll6_other", "pll6";
79 }; 91 };
80 92
81 cpu: cpu@01c20054 { 93 cpu: cpu@01c20054 {
82 #clock-cells = <0>; 94 #clock-cells = <0>;
83 compatible = "allwinner,sun4i-cpu-clk"; 95 compatible = "allwinner,sun4i-cpu-clk";
84 reg = <0x01c20054 0x4>; 96 reg = <0x01c20054 0x4>;
85 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>; 97 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
86 }; 98 };
87 99
88 axi: axi@01c20054 { 100 axi: axi@01c20054 {
@@ -141,7 +153,7 @@
141 #clock-cells = <0>; 153 #clock-cells = <0>;
142 compatible = "allwinner,sun4i-apb1-mux-clk"; 154 compatible = "allwinner,sun4i-apb1-mux-clk";
143 reg = <0x01c20058 0x4>; 155 reg = <0x01c20058 0x4>;
144 clocks = <&osc24M>, <&pll6>, <&osc32k>; 156 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
145 }; 157 };
146 158
147 apb1: apb1@01c20058 { 159 apb1: apb1@01c20058 {
@@ -163,6 +175,162 @@
163 "apb1_uart2", "apb1_uart3", "apb1_uart4", 175 "apb1_uart2", "apb1_uart3", "apb1_uart4",
164 "apb1_uart5", "apb1_uart6", "apb1_uart7"; 176 "apb1_uart5", "apb1_uart6", "apb1_uart7";
165 }; 177 };
178
179 nand_clk: clk@01c20080 {
180 #clock-cells = <0>;
181 compatible = "allwinner,sun4i-mod0-clk";
182 reg = <0x01c20080 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
184 clock-output-names = "nand";
185 };
186
187 ms_clk: clk@01c20084 {
188 #clock-cells = <0>;
189 compatible = "allwinner,sun4i-mod0-clk";
190 reg = <0x01c20084 0x4>;
191 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
192 clock-output-names = "ms";
193 };
194
195 mmc0_clk: clk@01c20088 {
196 #clock-cells = <0>;
197 compatible = "allwinner,sun4i-mod0-clk";
198 reg = <0x01c20088 0x4>;
199 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
200 clock-output-names = "mmc0";
201 };
202
203 mmc1_clk: clk@01c2008c {
204 #clock-cells = <0>;
205 compatible = "allwinner,sun4i-mod0-clk";
206 reg = <0x01c2008c 0x4>;
207 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
208 clock-output-names = "mmc1";
209 };
210
211 mmc2_clk: clk@01c20090 {
212 #clock-cells = <0>;
213 compatible = "allwinner,sun4i-mod0-clk";
214 reg = <0x01c20090 0x4>;
215 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
216 clock-output-names = "mmc2";
217 };
218
219 mmc3_clk: clk@01c20094 {
220 #clock-cells = <0>;
221 compatible = "allwinner,sun4i-mod0-clk";
222 reg = <0x01c20094 0x4>;
223 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
224 clock-output-names = "mmc3";
225 };
226
227 ts_clk: clk@01c20098 {
228 #clock-cells = <0>;
229 compatible = "allwinner,sun4i-mod0-clk";
230 reg = <0x01c20098 0x4>;
231 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
232 clock-output-names = "ts";
233 };
234
235 ss_clk: clk@01c2009c {
236 #clock-cells = <0>;
237 compatible = "allwinner,sun4i-mod0-clk";
238 reg = <0x01c2009c 0x4>;
239 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
240 clock-output-names = "ss";
241 };
242
243 spi0_clk: clk@01c200a0 {
244 #clock-cells = <0>;
245 compatible = "allwinner,sun4i-mod0-clk";
246 reg = <0x01c200a0 0x4>;
247 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248 clock-output-names = "spi0";
249 };
250
251 spi1_clk: clk@01c200a4 {
252 #clock-cells = <0>;
253 compatible = "allwinner,sun4i-mod0-clk";
254 reg = <0x01c200a4 0x4>;
255 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256 clock-output-names = "spi1";
257 };
258
259 spi2_clk: clk@01c200a8 {
260 #clock-cells = <0>;
261 compatible = "allwinner,sun4i-mod0-clk";
262 reg = <0x01c200a8 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "spi2";
265 };
266
267 pata_clk: clk@01c200ac {
268 #clock-cells = <0>;
269 compatible = "allwinner,sun4i-mod0-clk";
270 reg = <0x01c200ac 0x4>;
271 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
272 clock-output-names = "pata";
273 };
274
275 ir0_clk: clk@01c200b0 {
276 #clock-cells = <0>;
277 compatible = "allwinner,sun4i-mod0-clk";
278 reg = <0x01c200b0 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "ir0";
281 };
282
283 ir1_clk: clk@01c200b4 {
284 #clock-cells = <0>;
285 compatible = "allwinner,sun4i-mod0-clk";
286 reg = <0x01c200b4 0x4>;
287 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
288 clock-output-names = "ir1";
289 };
290
291 spi3_clk: clk@01c200d4 {
292 #clock-cells = <0>;
293 compatible = "allwinner,sun4i-mod0-clk";
294 reg = <0x01c200d4 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
296 clock-output-names = "spi3";
297 };
298
299 mbus_clk: clk@01c2015c {
300 #clock-cells = <0>;
301 compatible = "allwinner,sun4i-mod0-clk";
302 reg = <0x01c2015c 0x4>;
303 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
304 clock-output-names = "mbus";
305 };
306
307 /*
308 * Dummy clock used by output clocks
309 */
310 osc24M_32k: clk@1 {
311 #clock-cells = <0>;
312 compatible = "fixed-factor-clock";
313 clock-div = <750>;
314 clock-mult = <1>;
315 clocks = <&osc24M>;
316 clock-output-names = "osc24M_32k";
317 };
318
319 clk_out_a: clk@01c201f0 {
320 #clock-cells = <0>;
321 compatible = "allwinner,sun7i-a20-out-clk";
322 reg = <0x01c201f0 0x4>;
323 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
324 clock-output-names = "clk_out_a";
325 };
326
327 clk_out_b: clk@01c201f4 {
328 #clock-cells = <0>;
329 compatible = "allwinner,sun7i-a20-out-clk";
330 reg = <0x01c201f4 0x4>;
331 clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
332 clock-output-names = "clk_out_b";
333 };
166 }; 334 };
167 335
168 soc@01c00000 { 336 soc@01c00000 {
@@ -250,6 +418,20 @@
250 allwinner,drive = <0>; 418 allwinner,drive = <0>;
251 allwinner,pull = <0>; 419 allwinner,pull = <0>;
252 }; 420 };
421
422 clk_out_a_pins_a: clk_out_a@0 {
423 allwinner,pins = "PI12";
424 allwinner,function = "clk_out_a";
425 allwinner,drive = <0>;
426 allwinner,pull = <0>;
427 };
428
429 clk_out_b_pins_a: clk_out_b@0 {
430 allwinner,pins = "PI13";
431 allwinner,function = "clk_out_b";
432 allwinner,drive = <0>;
433 allwinner,pull = <0>;
434 };
253 }; 435 };
254 436
255 timer@01c20c00 { 437 timer@01c20c00 {
@@ -280,6 +462,12 @@
280 reg = <0x01c23800 0x200>; 462 reg = <0x01c23800 0x200>;
281 }; 463 };
282 464
465 rtp: rtp@01c25000 {
466 compatible = "allwinner,sun4i-ts";
467 reg = <0x01c25000 0x100>;
468 interrupts = <0 29 4>;
469 };
470
283 uart0: serial@01c28000 { 471 uart0: serial@01c28000 {
284 compatible = "snps,dw-apb-uart"; 472 compatible = "snps,dw-apb-uart";
285 reg = <0x01c28000 0x400>; 473 reg = <0x01c28000 0x400>;
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-04 20:55:48 -0400