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-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c21
1 files changed, 7 insertions, 14 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index 3961c8778780..f041b197dd77 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -36,25 +36,22 @@ nv50_fifo_playlist_update(struct drm_device *dev)
36 struct drm_nouveau_private *dev_priv = dev->dev_private; 36 struct drm_nouveau_private *dev_priv = dev->dev_private;
37 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 37 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
38 struct nouveau_gpuobj *cur; 38 struct nouveau_gpuobj *cur;
39 int i, nr; 39 int i, p;
40 40
41 NV_DEBUG(dev, "\n"); 41 NV_DEBUG(dev, "\n");
42 42
43 cur = pfifo->playlist[pfifo->cur_playlist]; 43 cur = pfifo->playlist[pfifo->cur_playlist];
44 pfifo->cur_playlist = !pfifo->cur_playlist; 44 pfifo->cur_playlist = !pfifo->cur_playlist;
45 45
46 /* We never schedule channel 0 or 127 */ 46 for (i = 0, p = 0; i < pfifo->channels; i++) {
47 for (i = 1, nr = 0; i < 127; i++) { 47 if (nv_rd32(dev, 0x002600 + (i * 4)) & 0x80000000)
48 if (dev_priv->channels.ptr[i] && 48 nv_wo32(cur, p++ * 4, i);
49 dev_priv->channels.ptr[i]->ramfc) {
50 nv_wo32(cur, (nr * 4), i);
51 nr++;
52 }
53 } 49 }
50
54 dev_priv->engine.instmem.flush(dev); 51 dev_priv->engine.instmem.flush(dev);
55 52
56 nv_wr32(dev, 0x32f4, cur->vinst >> 12); 53 nv_wr32(dev, 0x32f4, cur->vinst >> 12);
57 nv_wr32(dev, 0x32ec, nr); 54 nv_wr32(dev, 0x32ec, p);
58 nv_wr32(dev, 0x2500, 0x101); 55 nv_wr32(dev, 0x2500, 0x101);
59} 56}
60 57
@@ -301,7 +298,6 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
301 struct drm_device *dev = chan->dev; 298 struct drm_device *dev = chan->dev;
302 struct drm_nouveau_private *dev_priv = dev->dev_private; 299 struct drm_nouveau_private *dev_priv = dev->dev_private;
303 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; 300 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
304 struct nouveau_gpuobj *ramfc = NULL;
305 unsigned long flags; 301 unsigned long flags;
306 302
307 NV_DEBUG(dev, "ch%d\n", chan->id); 303 NV_DEBUG(dev, "ch%d\n", chan->id);
@@ -319,9 +315,6 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
319 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1); 315 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
320 } 316 }
321 317
322 /* This will ensure the channel is seen as disabled. */
323 nouveau_gpuobj_ref(chan->ramfc, &ramfc);
324 nouveau_gpuobj_ref(NULL, &chan->ramfc);
325 nv50_fifo_channel_disable(dev, chan->id); 318 nv50_fifo_channel_disable(dev, chan->id);
326 319
327 /* Dummy channel, also used on ch 127 */ 320 /* Dummy channel, also used on ch 127 */
@@ -337,7 +330,7 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
337 iounmap(chan->user); 330 iounmap(chan->user);
338 chan->user = NULL; 331 chan->user = NULL;
339 } 332 }
340 nouveau_gpuobj_ref(NULL, &ramfc); 333 nouveau_gpuobj_ref(NULL, &chan->ramfc);
341 nouveau_gpuobj_ref(NULL, &chan->cache); 334 nouveau_gpuobj_ref(NULL, &chan->cache);
342} 335}
343 336