aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c74
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_43xx_data.c619
4 files changed, 695 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index d02acf9308d3..0f97d635ff90 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -752,6 +752,7 @@ extern int omap44xx_hwmod_init(void);
752extern int omap54xx_hwmod_init(void); 752extern int omap54xx_hwmod_init(void);
753extern int am33xx_hwmod_init(void); 753extern int am33xx_hwmod_init(void);
754extern int dra7xx_hwmod_init(void); 754extern int dra7xx_hwmod_init(void);
755int am43xx_hwmod_init(void);
755 756
756extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 757extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
757 758
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
index a9a790297f68..130332c0534d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_common_data.h
@@ -158,5 +158,6 @@ extern struct omap_gpio_dev_attr gpio_dev_attr;
158extern struct omap2_mcspi_dev_attr mcspi_attrib; 158extern struct omap2_mcspi_dev_attr mcspi_attrib;
159 159
160void omap_hwmod_am33xx_reg(void); 160void omap_hwmod_am33xx_reg(void);
161void omap_hwmod_am43xx_reg(void);
161 162
162#endif 163#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index ffb371ff42dc..0f178623e7da 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -23,6 +23,7 @@
23#include "cm33xx.h" 23#include "cm33xx.h"
24#include "prm33xx.h" 24#include "prm33xx.h"
25#include "omap_hwmod_33xx_43xx_common_data.h" 25#include "omap_hwmod_33xx_43xx_common_data.h"
26#include "prcm43xx.h"
26 27
27#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl)) 28#define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
28#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl)) 29#define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
@@ -1393,3 +1394,76 @@ void omap_hwmod_am33xx_reg(void)
1393 omap_hwmod_am33xx_clkctrl(); 1394 omap_hwmod_am33xx_clkctrl();
1394 omap_hwmod_am33xx_rst(); 1395 omap_hwmod_am33xx_rst();
1395} 1396}
1397
1398static void omap_hwmod_am43xx_clkctrl(void)
1399{
1400 CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1401 CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1402 CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1403 CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1404 CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1405 CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1406 CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1407 CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1408 CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1409 CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1410 CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1411 CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1412 CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1413 CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1414 CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1415 CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1416 CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1417 CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1418 CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1419 CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1420 CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1421 CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1422 CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1423 CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1424 CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1425 CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1426 CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1427 CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1428 CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1429 CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1430 CLKCTRL(am33xx_smartreflex0_hwmod,
1431 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1432 CLKCTRL(am33xx_smartreflex1_hwmod,
1433 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1434 CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1435 CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1436 CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1437 CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1438 CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1439 CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1440 CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1441 CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1442 CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1443 CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1444 CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1445 CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1446 CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1447 CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1448 CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1449 CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1450 CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1451 CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1452 CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1453 CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1454 CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1455 CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1456}
1457
1458static void omap_hwmod_am43xx_rst(void)
1459{
1460 RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1461 RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1462 RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1463}
1464
1465void omap_hwmod_am43xx_reg(void)
1466{
1467 omap_hwmod_am43xx_clkctrl();
1468 omap_hwmod_am43xx_rst();
1469}
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
new file mode 100644
index 000000000000..6500d43defc5
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c
@@ -0,0 +1,619 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated
3 *
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/platform_data/gpio-omap.h>
18#include <linux/platform_data/spi-omap2-mcspi.h>
19#include "omap_hwmod.h"
20#include "omap_hwmod_33xx_43xx_common_data.h"
21#include "prcm43xx.h"
22
23/* IP blocks */
24static struct omap_hwmod am43xx_l4_hs_hwmod = {
25 .name = "l4_hs",
26 .class = &am33xx_l4_hwmod_class,
27 .clkdm_name = "l3_clkdm",
28 .flags = HWMOD_INIT_NO_IDLE,
29 .main_clk = "l4hs_gclk",
30 .prcm = {
31 .omap4 = {
32 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
33 .modulemode = MODULEMODE_SWCTRL,
34 },
35 },
36};
37
38static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
39 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
40};
41
42static struct omap_hwmod am43xx_wkup_m3_hwmod = {
43 .name = "wkup_m3",
44 .class = &am33xx_wkup_m3_hwmod_class,
45 .clkdm_name = "l4_wkup_aon_clkdm",
46 /* Keep hardreset asserted */
47 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
48 .main_clk = "sys_clkin_ck",
49 .prcm = {
50 .omap4 = {
51 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
52 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
53 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
55 },
56 },
57 .rst_lines = am33xx_wkup_m3_resets,
58 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
59};
60
61static struct omap_hwmod am43xx_control_hwmod = {
62 .name = "control",
63 .class = &am33xx_control_hwmod_class,
64 .clkdm_name = "l4_wkup_clkdm",
65 .flags = HWMOD_INIT_NO_IDLE,
66 .main_clk = "sys_clkin_ck",
67 .prcm = {
68 .omap4 = {
69 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
70 .modulemode = MODULEMODE_SWCTRL,
71 },
72 },
73};
74
75static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
76 { .role = "dbclk", .clk = "gpio0_dbclk" },
77};
78
79static struct omap_hwmod am43xx_gpio0_hwmod = {
80 .name = "gpio1",
81 .class = &am33xx_gpio_hwmod_class,
82 .clkdm_name = "l4_wkup_clkdm",
83 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
84 .main_clk = "sys_clkin_ck",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
89 },
90 },
91 .opt_clks = gpio0_opt_clks,
92 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
93 .dev_attr = &gpio_dev_attr,
94};
95
96static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
97 .rev_offs = 0x0,
98 .sysc_offs = 0x4,
99 .sysc_flags = SYSC_HAS_SIDLEMODE,
100 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
101 .sysc_fields = &omap_hwmod_sysc_type1,
102};
103
104static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
105 .name = "synctimer",
106 .sysc = &am43xx_synctimer_sysc,
107};
108
109static struct omap_hwmod am43xx_synctimer_hwmod = {
110 .name = "counter_32k",
111 .class = &am43xx_synctimer_hwmod_class,
112 .clkdm_name = "l4_wkup_aon_clkdm",
113 .flags = HWMOD_SWSUP_SIDLE,
114 .main_clk = "synctimer_32kclk",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
119 },
120 },
121};
122
123static struct omap_hwmod am43xx_timer8_hwmod = {
124 .name = "timer8",
125 .class = &am33xx_timer_hwmod_class,
126 .clkdm_name = "l4ls_clkdm",
127 .main_clk = "timer8_fck",
128 .prcm = {
129 .omap4 = {
130 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
131 .modulemode = MODULEMODE_SWCTRL,
132 },
133 },
134};
135
136static struct omap_hwmod am43xx_timer9_hwmod = {
137 .name = "timer9",
138 .class = &am33xx_timer_hwmod_class,
139 .clkdm_name = "l4ls_clkdm",
140 .main_clk = "timer9_fck",
141 .prcm = {
142 .omap4 = {
143 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
144 .modulemode = MODULEMODE_SWCTRL,
145 },
146 },
147};
148
149static struct omap_hwmod am43xx_timer10_hwmod = {
150 .name = "timer10",
151 .class = &am33xx_timer_hwmod_class,
152 .clkdm_name = "l4ls_clkdm",
153 .main_clk = "timer10_fck",
154 .prcm = {
155 .omap4 = {
156 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
157 .modulemode = MODULEMODE_SWCTRL,
158 },
159 },
160};
161
162static struct omap_hwmod am43xx_timer11_hwmod = {
163 .name = "timer11",
164 .class = &am33xx_timer_hwmod_class,
165 .clkdm_name = "l4ls_clkdm",
166 .main_clk = "timer11_fck",
167 .prcm = {
168 .omap4 = {
169 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
170 .modulemode = MODULEMODE_SWCTRL,
171 },
172 },
173};
174
175static struct omap_hwmod am43xx_epwmss3_hwmod = {
176 .name = "epwmss3",
177 .class = &am33xx_epwmss_hwmod_class,
178 .clkdm_name = "l4ls_clkdm",
179 .main_clk = "l4ls_gclk",
180 .prcm = {
181 .omap4 = {
182 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
183 .modulemode = MODULEMODE_SWCTRL,
184 },
185 },
186};
187
188static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
189 .name = "ehrpwm3",
190 .class = &am33xx_ehrpwm_hwmod_class,
191 .clkdm_name = "l4ls_clkdm",
192 .main_clk = "l4ls_gclk",
193};
194
195static struct omap_hwmod am43xx_epwmss4_hwmod = {
196 .name = "epwmss4",
197 .class = &am33xx_epwmss_hwmod_class,
198 .clkdm_name = "l4ls_clkdm",
199 .main_clk = "l4ls_gclk",
200 .prcm = {
201 .omap4 = {
202 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
203 .modulemode = MODULEMODE_SWCTRL,
204 },
205 },
206};
207
208static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
209 .name = "ehrpwm4",
210 .class = &am33xx_ehrpwm_hwmod_class,
211 .clkdm_name = "l4ls_clkdm",
212 .main_clk = "l4ls_gclk",
213};
214
215static struct omap_hwmod am43xx_epwmss5_hwmod = {
216 .name = "epwmss5",
217 .class = &am33xx_epwmss_hwmod_class,
218 .clkdm_name = "l4ls_clkdm",
219 .main_clk = "l4ls_gclk",
220 .prcm = {
221 .omap4 = {
222 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
223 .modulemode = MODULEMODE_SWCTRL,
224 },
225 },
226};
227
228static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
229 .name = "ehrpwm5",
230 .class = &am33xx_ehrpwm_hwmod_class,
231 .clkdm_name = "l4ls_clkdm",
232 .main_clk = "l4ls_gclk",
233};
234
235static struct omap_hwmod am43xx_spi2_hwmod = {
236 .name = "spi2",
237 .class = &am33xx_spi_hwmod_class,
238 .clkdm_name = "l4ls_clkdm",
239 .main_clk = "dpll_per_m2_div4_ck",
240 .prcm = {
241 .omap4 = {
242 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
243 .modulemode = MODULEMODE_SWCTRL,
244 },
245 },
246 .dev_attr = &mcspi_attrib,
247};
248
249static struct omap_hwmod am43xx_spi3_hwmod = {
250 .name = "spi3",
251 .class = &am33xx_spi_hwmod_class,
252 .clkdm_name = "l4ls_clkdm",
253 .main_clk = "dpll_per_m2_div4_ck",
254 .prcm = {
255 .omap4 = {
256 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
257 .modulemode = MODULEMODE_SWCTRL,
258 },
259 },
260 .dev_attr = &mcspi_attrib,
261};
262
263static struct omap_hwmod am43xx_spi4_hwmod = {
264 .name = "spi4",
265 .class = &am33xx_spi_hwmod_class,
266 .clkdm_name = "l4ls_clkdm",
267 .main_clk = "dpll_per_m2_div4_ck",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
271 .modulemode = MODULEMODE_SWCTRL,
272 },
273 },
274 .dev_attr = &mcspi_attrib,
275};
276
277static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
278 { .role = "dbclk", .clk = "gpio4_dbclk" },
279};
280
281static struct omap_hwmod am43xx_gpio4_hwmod = {
282 .name = "gpio5",
283 .class = &am33xx_gpio_hwmod_class,
284 .clkdm_name = "l4ls_clkdm",
285 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
286 .main_clk = "l4ls_gclk",
287 .prcm = {
288 .omap4 = {
289 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
290 .modulemode = MODULEMODE_SWCTRL,
291 },
292 },
293 .opt_clks = gpio4_opt_clks,
294 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
295 .dev_attr = &gpio_dev_attr,
296};
297
298static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
299 { .role = "dbclk", .clk = "gpio5_dbclk" },
300};
301
302static struct omap_hwmod am43xx_gpio5_hwmod = {
303 .name = "gpio6",
304 .class = &am33xx_gpio_hwmod_class,
305 .clkdm_name = "l4ls_clkdm",
306 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
307 .main_clk = "l4ls_gclk",
308 .prcm = {
309 .omap4 = {
310 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
311 .modulemode = MODULEMODE_SWCTRL,
312 },
313 },
314 .opt_clks = gpio5_opt_clks,
315 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
316 .dev_attr = &gpio_dev_attr,
317};
318
319/* Interfaces */
320static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
321 .master = &am33xx_l3_main_hwmod,
322 .slave = &am43xx_l4_hs_hwmod,
323 .clk = "l3s_gclk",
324 .user = OCP_USER_MPU | OCP_USER_SDMA,
325};
326
327static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
328 .master = &am43xx_wkup_m3_hwmod,
329 .slave = &am33xx_l4_wkup_hwmod,
330 .clk = "sys_clkin_ck",
331 .user = OCP_USER_MPU | OCP_USER_SDMA,
332};
333
334static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
335 .master = &am33xx_l4_wkup_hwmod,
336 .slave = &am43xx_wkup_m3_hwmod,
337 .clk = "sys_clkin_ck",
338 .user = OCP_USER_MPU | OCP_USER_SDMA,
339};
340
341static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
342 .master = &am33xx_l3_main_hwmod,
343 .slave = &am33xx_pruss_hwmod,
344 .clk = "dpll_core_m4_ck",
345 .user = OCP_USER_MPU,
346};
347
348static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
349 .master = &am33xx_l4_wkup_hwmod,
350 .slave = &am33xx_smartreflex0_hwmod,
351 .clk = "sys_clkin_ck",
352 .user = OCP_USER_MPU,
353};
354
355static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
356 .master = &am33xx_l4_wkup_hwmod,
357 .slave = &am33xx_smartreflex1_hwmod,
358 .clk = "sys_clkin_ck",
359 .user = OCP_USER_MPU,
360};
361
362static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
363 .master = &am33xx_l4_wkup_hwmod,
364 .slave = &am43xx_control_hwmod,
365 .clk = "sys_clkin_ck",
366 .user = OCP_USER_MPU,
367};
368
369static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
370 .master = &am33xx_l4_wkup_hwmod,
371 .slave = &am33xx_i2c1_hwmod,
372 .clk = "sys_clkin_ck",
373 .user = OCP_USER_MPU,
374};
375
376static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
377 .master = &am33xx_l4_wkup_hwmod,
378 .slave = &am43xx_gpio0_hwmod,
379 .clk = "sys_clkin_ck",
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
381};
382
383static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
384 .master = &am43xx_l4_hs_hwmod,
385 .slave = &am33xx_cpgmac0_hwmod,
386 .clk = "cpsw_125mhz_gclk",
387 .user = OCP_USER_MPU,
388};
389
390static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
391 .master = &am33xx_l4_wkup_hwmod,
392 .slave = &am33xx_timer1_hwmod,
393 .clk = "sys_clkin_ck",
394 .user = OCP_USER_MPU,
395};
396
397static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
398 .master = &am33xx_l4_wkup_hwmod,
399 .slave = &am33xx_uart1_hwmod,
400 .clk = "sys_clkin_ck",
401 .user = OCP_USER_MPU,
402};
403
404static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
405 .master = &am33xx_l4_wkup_hwmod,
406 .slave = &am33xx_wd_timer1_hwmod,
407 .clk = "sys_clkin_ck",
408 .user = OCP_USER_MPU,
409};
410
411static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
412 .master = &am33xx_l4_wkup_hwmod,
413 .slave = &am43xx_synctimer_hwmod,
414 .clk = "sys_clkin_ck",
415 .user = OCP_USER_MPU,
416};
417
418static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
419 .master = &am33xx_l4_ls_hwmod,
420 .slave = &am43xx_timer8_hwmod,
421 .clk = "l4ls_gclk",
422 .user = OCP_USER_MPU,
423};
424
425static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
426 .master = &am33xx_l4_ls_hwmod,
427 .slave = &am43xx_timer9_hwmod,
428 .clk = "l4ls_gclk",
429 .user = OCP_USER_MPU,
430};
431
432static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
433 .master = &am33xx_l4_ls_hwmod,
434 .slave = &am43xx_timer10_hwmod,
435 .clk = "l4ls_gclk",
436 .user = OCP_USER_MPU,
437};
438
439static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
440 .master = &am33xx_l4_ls_hwmod,
441 .slave = &am43xx_timer11_hwmod,
442 .clk = "l4ls_gclk",
443 .user = OCP_USER_MPU,
444};
445
446static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
447 .master = &am33xx_l4_ls_hwmod,
448 .slave = &am43xx_epwmss3_hwmod,
449 .clk = "l4ls_gclk",
450 .user = OCP_USER_MPU,
451};
452
453static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
454 .master = &am43xx_epwmss3_hwmod,
455 .slave = &am43xx_ehrpwm3_hwmod,
456 .clk = "l4ls_gclk",
457 .user = OCP_USER_MPU,
458};
459
460static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
461 .master = &am33xx_l4_ls_hwmod,
462 .slave = &am43xx_epwmss4_hwmod,
463 .clk = "l4ls_gclk",
464 .user = OCP_USER_MPU,
465};
466
467static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
468 .master = &am43xx_epwmss4_hwmod,
469 .slave = &am43xx_ehrpwm4_hwmod,
470 .clk = "l4ls_gclk",
471 .user = OCP_USER_MPU,
472};
473
474static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
475 .master = &am33xx_l4_ls_hwmod,
476 .slave = &am43xx_epwmss5_hwmod,
477 .clk = "l4ls_gclk",
478 .user = OCP_USER_MPU,
479};
480
481static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
482 .master = &am43xx_epwmss5_hwmod,
483 .slave = &am43xx_ehrpwm5_hwmod,
484 .clk = "l4ls_gclk",
485 .user = OCP_USER_MPU,
486};
487
488static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
489 .master = &am33xx_l4_ls_hwmod,
490 .slave = &am43xx_spi2_hwmod,
491 .clk = "l4ls_gclk",
492 .user = OCP_USER_MPU,
493};
494
495static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
496 .master = &am33xx_l4_ls_hwmod,
497 .slave = &am43xx_spi3_hwmod,
498 .clk = "l4ls_gclk",
499 .user = OCP_USER_MPU,
500};
501
502static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
503 .master = &am33xx_l4_ls_hwmod,
504 .slave = &am43xx_spi4_hwmod,
505 .clk = "l4ls_gclk",
506 .user = OCP_USER_MPU,
507};
508
509static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
510 .master = &am33xx_l4_ls_hwmod,
511 .slave = &am43xx_gpio4_hwmod,
512 .clk = "l4ls_gclk",
513 .user = OCP_USER_MPU | OCP_USER_SDMA,
514};
515
516static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
517 .master = &am33xx_l4_ls_hwmod,
518 .slave = &am43xx_gpio5_hwmod,
519 .clk = "l4ls_gclk",
520 .user = OCP_USER_MPU | OCP_USER_SDMA,
521};
522
523static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
524 &am33xx_l4_wkup__synctimer,
525 &am43xx_l4_ls__timer8,
526 &am43xx_l4_ls__timer9,
527 &am43xx_l4_ls__timer10,
528 &am43xx_l4_ls__timer11,
529 &am43xx_l4_ls__epwmss3,
530 &am43xx_epwmss3__ehrpwm3,
531 &am43xx_l4_ls__epwmss4,
532 &am43xx_epwmss4__ehrpwm4,
533 &am43xx_l4_ls__epwmss5,
534 &am43xx_epwmss5__ehrpwm5,
535 &am43xx_l4_ls__mcspi2,
536 &am43xx_l4_ls__mcspi3,
537 &am43xx_l4_ls__mcspi4,
538 &am43xx_l4_ls__gpio4,
539 &am43xx_l4_ls__gpio5,
540 &am43xx_l3_main__pruss,
541 &am33xx_mpu__l3_main,
542 &am33xx_mpu__prcm,
543 &am33xx_l3_s__l4_ls,
544 &am33xx_l3_s__l4_wkup,
545 &am43xx_l3_main__l4_hs,
546 &am33xx_l3_main__l3_s,
547 &am33xx_l3_main__l3_instr,
548 &am33xx_l3_main__gfx,
549 &am33xx_l3_s__l3_main,
550 &am33xx_pruss__l3_main,
551 &am43xx_wkup_m3__l4_wkup,
552 &am33xx_gfx__l3_main,
553 &am43xx_l4_wkup__wkup_m3,
554 &am43xx_l4_wkup__control,
555 &am43xx_l4_wkup__smartreflex0,
556 &am43xx_l4_wkup__smartreflex1,
557 &am43xx_l4_wkup__uart1,
558 &am43xx_l4_wkup__timer1,
559 &am43xx_l4_wkup__i2c1,
560 &am43xx_l4_wkup__gpio0,
561 &am43xx_l4_wkup__wd_timer1,
562 &am33xx_l4_per__dcan0,
563 &am33xx_l4_per__dcan1,
564 &am33xx_l4_per__gpio1,
565 &am33xx_l4_per__gpio2,
566 &am33xx_l4_per__gpio3,
567 &am33xx_l4_per__i2c2,
568 &am33xx_l4_per__i2c3,
569 &am33xx_l4_per__mailbox,
570 &am33xx_l4_ls__mcasp0,
571 &am33xx_l4_ls__mcasp1,
572 &am33xx_l4_ls__mmc0,
573 &am33xx_l4_ls__mmc1,
574 &am33xx_l3_s__mmc2,
575 &am33xx_l4_ls__timer2,
576 &am33xx_l4_ls__timer3,
577 &am33xx_l4_ls__timer4,
578 &am33xx_l4_ls__timer5,
579 &am33xx_l4_ls__timer6,
580 &am33xx_l4_ls__timer7,
581 &am33xx_l3_main__tpcc,
582 &am33xx_l4_ls__uart2,
583 &am33xx_l4_ls__uart3,
584 &am33xx_l4_ls__uart4,
585 &am33xx_l4_ls__uart5,
586 &am33xx_l4_ls__uart6,
587 &am33xx_l4_ls__elm,
588 &am33xx_l4_ls__epwmss0,
589 &am33xx_epwmss0__ecap0,
590 &am33xx_epwmss0__eqep0,
591 &am33xx_epwmss0__ehrpwm0,
592 &am33xx_l4_ls__epwmss1,
593 &am33xx_epwmss1__ecap1,
594 &am33xx_epwmss1__eqep1,
595 &am33xx_epwmss1__ehrpwm1,
596 &am33xx_l4_ls__epwmss2,
597 &am33xx_epwmss2__ecap2,
598 &am33xx_epwmss2__eqep2,
599 &am33xx_epwmss2__ehrpwm2,
600 &am33xx_l3_s__gpmc,
601 &am33xx_l4_ls__mcspi0,
602 &am33xx_l4_ls__mcspi1,
603 &am33xx_l3_main__tptc0,
604 &am33xx_l3_main__tptc1,
605 &am33xx_l3_main__tptc2,
606 &am33xx_l3_main__ocmc,
607 &am43xx_l4_hs__cpgmac0,
608 &am33xx_cpgmac0__mdio,
609 &am33xx_l3_main__sha0,
610 &am33xx_l3_main__aes0,
611 NULL,
612};
613
614int __init am43xx_hwmod_init(void)
615{
616 omap_hwmod_am43xx_reg();
617 omap_hwmod_init();
618 return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);
619}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 18:03:33 -0400