diff options
| -rw-r--r-- | drivers/video/sis/sis_main.c | 66 |
1 files changed, 33 insertions, 33 deletions
diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index 0b10f12c4707..65bf57f86a36 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c | |||
| @@ -2200,14 +2200,14 @@ sisfb_sense_crt1(struct sis_video_info *ivideo) | |||
| 2200 | 2200 | ||
| 2201 | sr1F = SiS_GetReg(SISSR, 0x1F); | 2201 | sr1F = SiS_GetReg(SISSR, 0x1F); |
| 2202 | SiS_SetRegOR(SISSR, 0x1F, 0x04); | 2202 | SiS_SetRegOR(SISSR, 0x1F, 0x04); |
| 2203 | andSISIDXREG(SISSR,0x1F,0x3F); | 2203 | SiS_SetRegAND(SISSR, 0x1F, 0x3F); |
| 2204 | if(sr1F & 0xc0) mustwait = true; | 2204 | if(sr1F & 0xc0) mustwait = true; |
| 2205 | 2205 | ||
| 2206 | #ifdef CONFIG_FB_SIS_315 | 2206 | #ifdef CONFIG_FB_SIS_315 |
| 2207 | if(ivideo->sisvga_engine == SIS_315_VGA) { | 2207 | if(ivideo->sisvga_engine == SIS_315_VGA) { |
| 2208 | cr63 = SiS_GetReg(SISCR, ivideo->SiS_Pr.SiS_MyCR63); | 2208 | cr63 = SiS_GetReg(SISCR, ivideo->SiS_Pr.SiS_MyCR63); |
| 2209 | cr63 &= 0x40; | 2209 | cr63 &= 0x40; |
| 2210 | andSISIDXREG(SISCR,ivideo->SiS_Pr.SiS_MyCR63,0xBF); | 2210 | SiS_SetRegAND(SISCR, ivideo->SiS_Pr.SiS_MyCR63, 0xBF); |
| 2211 | } | 2211 | } |
| 2212 | #endif | 2212 | #endif |
| 2213 | 2213 | ||
| @@ -2226,7 +2226,7 @@ sisfb_sense_crt1(struct sis_video_info *ivideo) | |||
| 2226 | 2226 | ||
| 2227 | #ifdef CONFIG_FB_SIS_315 | 2227 | #ifdef CONFIG_FB_SIS_315 |
| 2228 | if(ivideo->chip >= SIS_330) { | 2228 | if(ivideo->chip >= SIS_330) { |
| 2229 | andSISIDXREG(SISCR,0x32,~0x20); | 2229 | SiS_SetRegAND(SISCR, 0x32, ~0x20); |
| 2230 | if(ivideo->chip >= SIS_340) { | 2230 | if(ivideo->chip >= SIS_340) { |
| 2231 | SiS_SetReg(SISCR, 0x57, 0x4a); | 2231 | SiS_SetReg(SISCR, 0x57, 0x4a); |
| 2232 | } else { | 2232 | } else { |
| @@ -2236,8 +2236,8 @@ sisfb_sense_crt1(struct sis_video_info *ivideo) | |||
| 2236 | while ((SiS_GetRegByte(SISINPSTAT)) & 0x01) break; | 2236 | while ((SiS_GetRegByte(SISINPSTAT)) & 0x01) break; |
| 2237 | while (!((SiS_GetRegByte(SISINPSTAT)) & 0x01)) break; | 2237 | while (!((SiS_GetRegByte(SISINPSTAT)) & 0x01)) break; |
| 2238 | if ((SiS_GetRegByte(SISMISCW)) & 0x10) temp = 1; | 2238 | if ((SiS_GetRegByte(SISMISCW)) & 0x10) temp = 1; |
| 2239 | andSISIDXREG(SISCR, 0x53, 0xfd); | 2239 | SiS_SetRegAND(SISCR, 0x53, 0xfd); |
| 2240 | andSISIDXREG(SISCR, 0x57, 0x00); | 2240 | SiS_SetRegAND(SISCR, 0x57, 0x00); |
| 2241 | } | 2241 | } |
| 2242 | #endif | 2242 | #endif |
| 2243 | 2243 | ||
| @@ -2378,7 +2378,7 @@ SISDoSense(struct sis_video_info *ivideo, u16 type, u16 test) | |||
| 2378 | if(temp == mytest) result++; | 2378 | if(temp == mytest) result++; |
| 2379 | #if 1 | 2379 | #if 1 |
| 2380 | SiS_SetReg(SISPART4, 0x11, 0x00); | 2380 | SiS_SetReg(SISPART4, 0x11, 0x00); |
| 2381 | andSISIDXREG(SISPART4,0x10,0xe0); | 2381 | SiS_SetRegAND(SISPART4, 0x10, 0xe0); |
| 2382 | SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000); | 2382 | SiS_DDC2Delay(&ivideo->SiS_Pr, 0x1000); |
| 2383 | #endif | 2383 | #endif |
| 2384 | } | 2384 | } |
| @@ -2461,7 +2461,7 @@ SiS_Sense30x(struct sis_video_info *ivideo) | |||
| 2461 | SISDoSense(ivideo, 0, 0); | 2461 | SISDoSense(ivideo, 0, 0); |
| 2462 | } | 2462 | } |
| 2463 | 2463 | ||
| 2464 | andSISIDXREG(SISCR, 0x32, ~0x14); | 2464 | SiS_SetRegAND(SISCR, 0x32, ~0x14); |
| 2465 | 2465 | ||
| 2466 | if(vga2_c || vga2) { | 2466 | if(vga2_c || vga2) { |
| 2467 | if(SISDoSense(ivideo, vga2, vga2_c)) { | 2467 | if(SISDoSense(ivideo, vga2, vga2_c)) { |
| @@ -2475,7 +2475,7 @@ SiS_Sense30x(struct sis_video_info *ivideo) | |||
| 2475 | } | 2475 | } |
| 2476 | } | 2476 | } |
| 2477 | 2477 | ||
| 2478 | andSISIDXREG(SISCR, 0x32, 0x3f); | 2478 | SiS_SetRegAND(SISCR, 0x32, 0x3f); |
| 2479 | 2479 | ||
| 2480 | if(ivideo->vbflags2 & VB2_30xCLV) { | 2480 | if(ivideo->vbflags2 & VB2_30xCLV) { |
| 2481 | SiS_SetRegOR(SISPART4, 0x0d, 0x04); | 2481 | SiS_SetRegOR(SISPART4, 0x0d, 0x04); |
| @@ -2493,7 +2493,7 @@ SiS_Sense30x(struct sis_video_info *ivideo) | |||
| 2493 | SiS_SetReg(SISPART2, 0x4d, backupP2_4d); | 2493 | SiS_SetReg(SISPART2, 0x4d, backupP2_4d); |
| 2494 | } | 2494 | } |
| 2495 | 2495 | ||
| 2496 | andSISIDXREG(SISCR, 0x32, ~0x03); | 2496 | SiS_SetRegAND(SISCR, 0x32, ~0x03); |
| 2497 | 2497 | ||
| 2498 | if(!(ivideo->vbflags & TV_YPBPR)) { | 2498 | if(!(ivideo->vbflags & TV_YPBPR)) { |
| 2499 | if((result = SISDoSense(ivideo, svhs, svhs_c))) { | 2499 | if((result = SISDoSense(ivideo, svhs, svhs_c))) { |
| @@ -2589,19 +2589,19 @@ SiS_SenseCh(struct sis_video_info *ivideo) | |||
| 2589 | printk(KERN_INFO "%s SVIDEO output\n", stdstr); | 2589 | printk(KERN_INFO "%s SVIDEO output\n", stdstr); |
| 2590 | ivideo->vbflags |= TV_SVIDEO; | 2590 | ivideo->vbflags |= TV_SVIDEO; |
| 2591 | SiS_SetRegOR(SISCR, 0x32, 0x02); | 2591 | SiS_SetRegOR(SISCR, 0x32, 0x02); |
| 2592 | andSISIDXREG(SISCR, 0x32, ~0x05); | 2592 | SiS_SetRegAND(SISCR, 0x32, ~0x05); |
| 2593 | } else if (temp1 == 0x01) { | 2593 | } else if (temp1 == 0x01) { |
| 2594 | printk(KERN_INFO "%s CVBS output\n", stdstr); | 2594 | printk(KERN_INFO "%s CVBS output\n", stdstr); |
| 2595 | ivideo->vbflags |= TV_AVIDEO; | 2595 | ivideo->vbflags |= TV_AVIDEO; |
| 2596 | SiS_SetRegOR(SISCR, 0x32, 0x01); | 2596 | SiS_SetRegOR(SISCR, 0x32, 0x01); |
| 2597 | andSISIDXREG(SISCR, 0x32, ~0x06); | 2597 | SiS_SetRegAND(SISCR, 0x32, ~0x06); |
| 2598 | } else { | 2598 | } else { |
| 2599 | SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8); | 2599 | SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8); |
| 2600 | andSISIDXREG(SISCR, 0x32, ~0x07); | 2600 | SiS_SetRegAND(SISCR, 0x32, ~0x07); |
| 2601 | } | 2601 | } |
| 2602 | } else if(temp1 == 0) { | 2602 | } else if(temp1 == 0) { |
| 2603 | SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8); | 2603 | SiS_SetCH70xxANDOR(&ivideo->SiS_Pr, 0x0e, 0x01, 0xF8); |
| 2604 | andSISIDXREG(SISCR, 0x32, ~0x07); | 2604 | SiS_SetRegAND(SISCR, 0x32, ~0x07); |
| 2605 | } | 2605 | } |
| 2606 | /* Set general purpose IO for Chrontel communication */ | 2606 | /* Set general purpose IO for Chrontel communication */ |
| 2607 | SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x00); | 2607 | SiS_SetChrontelGPIO(&ivideo->SiS_Pr, 0x00); |
| @@ -2633,21 +2633,21 @@ SiS_SenseCh(struct sis_video_info *ivideo) | |||
| 2633 | printk(KERN_INFO "%s CVBS output\n", stdstr); | 2633 | printk(KERN_INFO "%s CVBS output\n", stdstr); |
| 2634 | ivideo->vbflags |= TV_AVIDEO; | 2634 | ivideo->vbflags |= TV_AVIDEO; |
| 2635 | SiS_SetRegOR(SISCR, 0x32, 0x01); | 2635 | SiS_SetRegOR(SISCR, 0x32, 0x01); |
| 2636 | andSISIDXREG(SISCR, 0x32, ~0x06); | 2636 | SiS_SetRegAND(SISCR, 0x32, ~0x06); |
| 2637 | break; | 2637 | break; |
| 2638 | case 0x02: | 2638 | case 0x02: |
| 2639 | printk(KERN_INFO "%s SVIDEO output\n", stdstr); | 2639 | printk(KERN_INFO "%s SVIDEO output\n", stdstr); |
| 2640 | ivideo->vbflags |= TV_SVIDEO; | 2640 | ivideo->vbflags |= TV_SVIDEO; |
| 2641 | SiS_SetRegOR(SISCR, 0x32, 0x02); | 2641 | SiS_SetRegOR(SISCR, 0x32, 0x02); |
| 2642 | andSISIDXREG(SISCR, 0x32, ~0x05); | 2642 | SiS_SetRegAND(SISCR, 0x32, ~0x05); |
| 2643 | break; | 2643 | break; |
| 2644 | case 0x04: | 2644 | case 0x04: |
| 2645 | printk(KERN_INFO "%s SCART output\n", stdstr); | 2645 | printk(KERN_INFO "%s SCART output\n", stdstr); |
| 2646 | SiS_SetRegOR(SISCR, 0x32, 0x04); | 2646 | SiS_SetRegOR(SISCR, 0x32, 0x04); |
| 2647 | andSISIDXREG(SISCR, 0x32, ~0x03); | 2647 | SiS_SetRegAND(SISCR, 0x32, ~0x03); |
| 2648 | break; | 2648 | break; |
| 2649 | default: | 2649 | default: |
| 2650 | andSISIDXREG(SISCR, 0x32, ~0x07); | 2650 | SiS_SetRegAND(SISCR, 0x32, ~0x07); |
| 2651 | } | 2651 | } |
| 2652 | #endif | 2652 | #endif |
| 2653 | } | 2653 | } |
| @@ -3690,7 +3690,7 @@ sisfb_fixup_SR11(struct sis_video_info *ivideo) | |||
| 3690 | tmpreg = SiS_GetReg(SISSR, 0x11); | 3690 | tmpreg = SiS_GetReg(SISSR, 0x11); |
| 3691 | } | 3691 | } |
| 3692 | if(tmpreg & 0xf0) { | 3692 | if(tmpreg & 0xf0) { |
| 3693 | andSISIDXREG(SISSR,0x11,0x0f); | 3693 | SiS_SetRegAND(SISSR, 0x11, 0x0f); |
| 3694 | } | 3694 | } |
| 3695 | } | 3695 | } |
| 3696 | } | 3696 | } |
| @@ -3871,7 +3871,7 @@ sisfb_post_setmode(struct sis_video_info *ivideo) | |||
| 3871 | } | 3871 | } |
| 3872 | } | 3872 | } |
| 3873 | 3873 | ||
| 3874 | andSISIDXREG(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04); | 3874 | SiS_SetRegAND(SISSR, IND_SIS_RAMDAC_CONTROL, ~0x04); |
| 3875 | 3875 | ||
| 3876 | if(ivideo->currentvbflags & CRT2_TV) { | 3876 | if(ivideo->currentvbflags & CRT2_TV) { |
| 3877 | if(ivideo->vbflags2 & VB2_SISBRIDGE) { | 3877 | if(ivideo->vbflags2 & VB2_SISBRIDGE) { |
| @@ -4194,7 +4194,7 @@ sisfb_post_300_buswidth(struct sis_video_info *ivideo) | |||
| 4194 | unsigned char reg; | 4194 | unsigned char reg; |
| 4195 | int i, j; | 4195 | int i, j; |
| 4196 | 4196 | ||
| 4197 | andSISIDXREG(SISSR, 0x15, 0xFB); | 4197 | SiS_SetRegAND(SISSR, 0x15, 0xFB); |
| 4198 | SiS_SetRegOR(SISSR, 0x15, 0x04); | 4198 | SiS_SetRegOR(SISSR, 0x15, 0x04); |
| 4199 | SiS_SetReg(SISSR, 0x13, 0x00); | 4199 | SiS_SetReg(SISSR, 0x13, 0x00); |
| 4200 | SiS_SetReg(SISSR, 0x14, 0xBF); | 4200 | SiS_SetReg(SISSR, 0x14, 0xBF); |
| @@ -4208,7 +4208,7 @@ sisfb_post_300_buswidth(struct sis_video_info *ivideo) | |||
| 4208 | SiS_SetRegOR(SISSR, 0x3c, 0x01); | 4208 | SiS_SetRegOR(SISSR, 0x3c, 0x01); |
| 4209 | reg = SiS_GetReg(SISSR, 0x05); | 4209 | reg = SiS_GetReg(SISSR, 0x05); |
| 4210 | reg = SiS_GetReg(SISSR, 0x05); | 4210 | reg = SiS_GetReg(SISSR, 0x05); |
| 4211 | andSISIDXREG(SISSR, 0x3c, 0xfe); | 4211 | SiS_SetRegAND(SISSR, 0x3c, 0xfe); |
| 4212 | reg = SiS_GetReg(SISSR, 0x05); | 4212 | reg = SiS_GetReg(SISSR, 0x05); |
| 4213 | reg = SiS_GetReg(SISSR, 0x05); | 4213 | reg = SiS_GetReg(SISSR, 0x05); |
| 4214 | temp++; | 4214 | temp++; |
| @@ -4283,7 +4283,7 @@ sisfb_post_300_rwtest(struct sis_video_info *ivideo, int iteration, int buswidth | |||
| 4283 | PhysicalAdrHalfPage = (PageCapacity / 2 + PhysicalAdrHigh) % PageCapacity; | 4283 | PhysicalAdrHalfPage = (PageCapacity / 2 + PhysicalAdrHigh) % PageCapacity; |
| 4284 | PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh; | 4284 | PhysicalAdrOtherPage = PageCapacity * SiS_DRAMType[k][2] + PhysicalAdrHigh; |
| 4285 | 4285 | ||
| 4286 | andSISIDXREG(SISSR, 0x15, 0xFB); /* Test */ | 4286 | SiS_SetRegAND(SISSR, 0x15, 0xFB); /* Test */ |
| 4287 | SiS_SetRegOR(SISSR, 0x15, 0x04); /* Test */ | 4287 | SiS_SetRegOR(SISSR, 0x15, 0x04); /* Test */ |
| 4288 | sr14 = (SiS_DRAMType[k][3] * buswidth) - 1; | 4288 | sr14 = (SiS_DRAMType[k][3] * buswidth) - 1; |
| 4289 | if(buswidth == 4) sr14 |= 0x80; | 4289 | if(buswidth == 4) sr14 |= 0x80; |
| @@ -4423,7 +4423,7 @@ sisfb_post_sis300(struct pci_dev *pdev) | |||
| 4423 | SiS_SetReg(SISSR, 0x1a, v6); | 4423 | SiS_SetReg(SISSR, 0x1a, v6); |
| 4424 | SiS_SetReg(SISSR, 0x1b, v7); | 4424 | SiS_SetReg(SISSR, 0x1b, v7); |
| 4425 | SiS_SetReg(SISSR, 0x1c, v8); /* ---- */ | 4425 | SiS_SetReg(SISSR, 0x1c, v8); /* ---- */ |
| 4426 | andSISIDXREG(SISSR, 0x15 ,0xfb); | 4426 | SiS_SetRegAND(SISSR, 0x15, 0xfb); |
| 4427 | SiS_SetRegOR(SISSR, 0x15, 0x04); | 4427 | SiS_SetRegOR(SISSR, 0x15, 0x04); |
| 4428 | if(bios) { | 4428 | if(bios) { |
| 4429 | if(bios[0x53] & 0x02) { | 4429 | if(bios[0x53] & 0x02) { |
| @@ -4485,7 +4485,7 @@ sisfb_post_sis300(struct pci_dev *pdev) | |||
| 4485 | } | 4485 | } |
| 4486 | SiS_SetReg(SISSR, 0x32, v2); | 4486 | SiS_SetReg(SISSR, 0x32, v2); |
| 4487 | 4487 | ||
| 4488 | andSISIDXREG(SISPART1, 0x24, 0xfe); /* Lock CRT2 */ | 4488 | SiS_SetRegAND(SISPART1, 0x24, 0xfe); /* Lock CRT2 */ |
| 4489 | 4489 | ||
| 4490 | reg = SiS_GetReg(SISSR, 0x16); | 4490 | reg = SiS_GetReg(SISSR, 0x16); |
| 4491 | reg &= 0xc3; | 4491 | reg &= 0xc3; |
| @@ -5067,7 +5067,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
| 5067 | SiS_SetReg(SISCR, 0x7e, 0x0f); | 5067 | SiS_SetReg(SISCR, 0x7e, 0x0f); |
| 5068 | } | 5068 | } |
| 5069 | if(ivideo->revision_id == 0) { /* 40 *and* 20? */ | 5069 | if(ivideo->revision_id == 0) { /* 40 *and* 20? */ |
| 5070 | andSISIDXREG(SISCR, 0x58, 0xd7); | 5070 | SiS_SetRegAND(SISCR, 0x58, 0xd7); |
| 5071 | reg = SiS_GetReg(SISCR, 0xcb); | 5071 | reg = SiS_GetReg(SISCR, 0xcb); |
| 5072 | if(reg & 0x20) { | 5072 | if(reg & 0x20) { |
| 5073 | setSISIDXREG(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */ | 5073 | setSISIDXREG(SISCR, 0x58, 0xd7, (reg & 0x10) ? 0x08 : 0x20); /* =0x28 Z7 ? */ |
| @@ -5085,15 +5085,15 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
| 5085 | SiS_SetReg(SISVID, 0x30, 0x00); | 5085 | SiS_SetReg(SISVID, 0x30, 0x00); |
| 5086 | SiS_SetReg(SISVID, 0x32, 0x01); | 5086 | SiS_SetReg(SISVID, 0x32, 0x01); |
| 5087 | SiS_SetReg(SISVID, 0x30, 0x00); | 5087 | SiS_SetReg(SISVID, 0x30, 0x00); |
| 5088 | andSISIDXREG(SISVID, 0x2f, 0xdf); | 5088 | SiS_SetRegAND(SISVID, 0x2f, 0xdf); |
| 5089 | andSISIDXREG(SISCAP, 0x00, 0x3f); | 5089 | SiS_SetRegAND(SISCAP, 0x00, 0x3f); |
| 5090 | 5090 | ||
| 5091 | SiS_SetReg(SISPART1, 0x2f, 0x01); | 5091 | SiS_SetReg(SISPART1, 0x2f, 0x01); |
| 5092 | SiS_SetReg(SISPART1, 0x00, 0x00); | 5092 | SiS_SetReg(SISPART1, 0x00, 0x00); |
| 5093 | SiS_SetReg(SISPART1, 0x02, bios[0x7e]); | 5093 | SiS_SetReg(SISPART1, 0x02, bios[0x7e]); |
| 5094 | SiS_SetReg(SISPART1, 0x2e, 0x08); | 5094 | SiS_SetReg(SISPART1, 0x2e, 0x08); |
| 5095 | andSISIDXREG(SISPART1, 0x35, 0x7f); | 5095 | SiS_SetRegAND(SISPART1, 0x35, 0x7f); |
| 5096 | andSISIDXREG(SISPART1, 0x50, 0xfe); | 5096 | SiS_SetRegAND(SISPART1, 0x50, 0xfe); |
| 5097 | 5097 | ||
| 5098 | reg = SiS_GetReg(SISPART4, 0x00); | 5098 | reg = SiS_GetReg(SISPART4, 0x00); |
| 5099 | if(reg == 1 || reg == 2) { | 5099 | if(reg == 1 || reg == 2) { |
| @@ -5101,7 +5101,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
| 5101 | SiS_SetReg(SISPART4, 0x0d, bios[0x7f]); | 5101 | SiS_SetReg(SISPART4, 0x0d, bios[0x7f]); |
| 5102 | SiS_SetReg(SISPART4, 0x0e, bios[0x80]); | 5102 | SiS_SetReg(SISPART4, 0x0e, bios[0x80]); |
| 5103 | SiS_SetReg(SISPART4, 0x10, bios[0x81]); | 5103 | SiS_SetReg(SISPART4, 0x10, bios[0x81]); |
| 5104 | andSISIDXREG(SISPART4, 0x0f, 0x3f); | 5104 | SiS_SetRegAND(SISPART4, 0x0f, 0x3f); |
| 5105 | 5105 | ||
| 5106 | reg = SiS_GetReg(SISPART4, 0x01); | 5106 | reg = SiS_GetReg(SISPART4, 0x01); |
| 5107 | if((reg & 0xf0) >= 0xb0) { | 5107 | if((reg & 0xf0) >= 0xb0) { |
| @@ -5259,7 +5259,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
| 5259 | } | 5259 | } |
| 5260 | } | 5260 | } |
| 5261 | 5261 | ||
| 5262 | andSISIDXREG(SISCR, 0x6e, 0xfc); | 5262 | SiS_SetRegAND(SISCR, 0x6e, 0xfc); |
| 5263 | 5263 | ||
| 5264 | ptr = NULL; | 5264 | ptr = NULL; |
| 5265 | if(ivideo->haveXGIROM) { | 5265 | if(ivideo->haveXGIROM) { |
| @@ -5297,7 +5297,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
| 5297 | SiS_SetReg(SISCR, 0x80 + i, ptr[j + regb]); | 5297 | SiS_SetReg(SISCR, 0x80 + i, ptr[j + regb]); |
| 5298 | } | 5298 | } |
| 5299 | 5299 | ||
| 5300 | andSISIDXREG(SISCR, 0x89, 0x8f); | 5300 | SiS_SetRegAND(SISCR, 0x89, 0x8f); |
| 5301 | 5301 | ||
| 5302 | ptr = cs45a; | 5302 | ptr = cs45a; |
| 5303 | if(ivideo->haveXGIROM) { | 5303 | if(ivideo->haveXGIROM) { |
| @@ -5660,7 +5660,7 @@ sisfb_post_xgi(struct pci_dev *pdev) | |||
| 5660 | SiS_SetReg(SISSR, 0x05, 0x86); | 5660 | SiS_SetReg(SISSR, 0x05, 0x86); |
| 5661 | 5661 | ||
| 5662 | /* Disable read-cache */ | 5662 | /* Disable read-cache */ |
| 5663 | andSISIDXREG(SISSR, 0x21, 0xdf); | 5663 | SiS_SetRegAND(SISSR, 0x21, 0xdf); |
| 5664 | sisfb_post_xgi_ramsize(ivideo); | 5664 | sisfb_post_xgi_ramsize(ivideo); |
| 5665 | /* Enable read-cache */ | 5665 | /* Enable read-cache */ |
| 5666 | SiS_SetRegOR(SISSR, 0x21, 0x20); | 5666 | SiS_SetRegOR(SISSR, 0x21, 0x20); |
