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-rw-r--r--drivers/clk/tegra/Makefile1
-rw-r--r--drivers/clk/tegra/clk-tegra-audio.c215
-rw-r--r--drivers/clk/tegra/clk-tegra114.c390
-rw-r--r--drivers/clk/tegra/clk.h4
4 files changed, 402 insertions, 208 deletions
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index f49fac2d193a..796ff9aa3899 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -6,6 +6,7 @@ obj-y += clk-periph-gate.o
6obj-y += clk-pll.o 6obj-y += clk-pll.o
7obj-y += clk-pll-out.o 7obj-y += clk-pll-out.o
8obj-y += clk-super.o 8obj-y += clk-super.o
9obj-y += clk-tegra-audio.o
9 10
10obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o 11obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
11obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o 12obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o
diff --git a/drivers/clk/tegra/clk-tegra-audio.c b/drivers/clk/tegra/clk-tegra-audio.c
new file mode 100644
index 000000000000..5c38aab2c5b8
--- /dev/null
+++ b/drivers/clk/tegra/clk-tegra-audio.c
@@ -0,0 +1,215 @@
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/io.h>
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/of.h>
21#include <linux/of_address.h>
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/clk/tegra.h>
25
26#include "clk.h"
27#include "clk-id.h"
28
29#define AUDIO_SYNC_CLK_I2S0 0x4a0
30#define AUDIO_SYNC_CLK_I2S1 0x4a4
31#define AUDIO_SYNC_CLK_I2S2 0x4a8
32#define AUDIO_SYNC_CLK_I2S3 0x4ac
33#define AUDIO_SYNC_CLK_I2S4 0x4b0
34#define AUDIO_SYNC_CLK_SPDIF 0x4b4
35
36#define AUDIO_SYNC_DOUBLER 0x49c
37
38#define PLLA_OUT 0xb4
39
40struct tegra_sync_source_initdata {
41 char *name;
42 unsigned long rate;
43 unsigned long max_rate;
44 int clk_id;
45};
46
47#define SYNC(_name) \
48 {\
49 .name = #_name,\
50 .rate = 24000000,\
51 .max_rate = 24000000,\
52 .clk_id = tegra_clk_ ## _name,\
53 }
54
55struct tegra_audio_clk_initdata {
56 char *gate_name;
57 char *mux_name;
58 u32 offset;
59 int gate_clk_id;
60 int mux_clk_id;
61};
62
63#define AUDIO(_name, _offset) \
64 {\
65 .gate_name = #_name,\
66 .mux_name = #_name"_mux",\
67 .offset = _offset,\
68 .gate_clk_id = tegra_clk_ ## _name,\
69 .mux_clk_id = tegra_clk_ ## _name ## _mux,\
70 }
71
72struct tegra_audio2x_clk_initdata {
73 char *parent;
74 char *gate_name;
75 char *name_2x;
76 char *div_name;
77 int clk_id;
78 int clk_num;
79 u8 div_offset;
80};
81
82#define AUDIO2X(_name, _num, _offset) \
83 {\
84 .parent = #_name,\
85 .gate_name = #_name"_2x",\
86 .name_2x = #_name"_doubler",\
87 .div_name = #_name"_div",\
88 .clk_id = tegra_clk_ ## _name ## _2x,\
89 .clk_num = _num,\
90 .div_offset = _offset,\
91 }
92
93static DEFINE_SPINLOCK(clk_doubler_lock);
94
95static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
96 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
97};
98
99static struct tegra_sync_source_initdata sync_source_clks[] __initdata = {
100 SYNC(spdif_in_sync),
101 SYNC(i2s0_sync),
102 SYNC(i2s1_sync),
103 SYNC(i2s2_sync),
104 SYNC(i2s3_sync),
105 SYNC(i2s4_sync),
106 SYNC(vimclk_sync),
107};
108
109static struct tegra_audio_clk_initdata audio_clks[] = {
110 AUDIO(audio0, AUDIO_SYNC_CLK_I2S0),
111 AUDIO(audio1, AUDIO_SYNC_CLK_I2S1),
112 AUDIO(audio2, AUDIO_SYNC_CLK_I2S2),
113 AUDIO(audio3, AUDIO_SYNC_CLK_I2S3),
114 AUDIO(audio4, AUDIO_SYNC_CLK_I2S4),
115 AUDIO(spdif, AUDIO_SYNC_CLK_SPDIF),
116};
117
118static struct tegra_audio2x_clk_initdata audio2x_clks[] = {
119 AUDIO2X(audio0, 113, 24),
120 AUDIO2X(audio1, 114, 25),
121 AUDIO2X(audio2, 115, 26),
122 AUDIO2X(audio3, 116, 27),
123 AUDIO2X(audio4, 117, 28),
124 AUDIO2X(spdif, 118, 29),
125};
126
127void __init tegra_audio_clk_init(void __iomem *clk_base,
128 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
129 struct tegra_clk_pll_params *pll_a_params)
130{
131 struct clk *clk;
132 struct clk **dt_clk;
133 int i;
134
135 /* PLLA */
136 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a, tegra_clks);
137 if (dt_clk) {
138 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base,
139 pmc_base, 0, pll_a_params, NULL);
140 *dt_clk = clk;
141 }
142
143 /* PLLA_OUT0 */
144 dt_clk = tegra_lookup_dt_id(tegra_clk_pll_a_out0, tegra_clks);
145 if (dt_clk) {
146 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
147 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
148 8, 8, 1, NULL);
149 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
150 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
151 CLK_SET_RATE_PARENT, 0, NULL);
152 *dt_clk = clk;
153 }
154
155 for (i = 0; i < ARRAY_SIZE(sync_source_clks); i++) {
156 struct tegra_sync_source_initdata *data;
157
158 data = &sync_source_clks[i];
159
160 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
161 if (!dt_clk)
162 continue;
163
164 clk = tegra_clk_register_sync_source(data->name,
165 data->rate, data->max_rate);
166 *dt_clk = clk;
167 }
168
169 for (i = 0; i < ARRAY_SIZE(audio_clks); i++) {
170 struct tegra_audio_clk_initdata *data;
171
172 data = &audio_clks[i];
173 dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);
174
175 if (!dt_clk)
176 continue;
177 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk,
178 ARRAY_SIZE(mux_audio_sync_clk),
179 CLK_SET_RATE_NO_REPARENT,
180 clk_base + data->offset, 0, 3, 0,
181 NULL);
182 *dt_clk = clk;
183
184 dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);
185 if (!dt_clk)
186 continue;
187
188 clk = clk_register_gate(NULL, data->gate_name, data->mux_name,
189 0, clk_base + data->offset, 4,
190 CLK_GATE_SET_TO_DISABLE, NULL);
191 *dt_clk = clk;
192 }
193
194 for (i = 0; i < ARRAY_SIZE(audio2x_clks); i++) {
195 struct tegra_audio2x_clk_initdata *data;
196
197 data = &audio2x_clks[i];
198 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);
199 if (!dt_clk)
200 continue;
201
202 clk = clk_register_fixed_factor(NULL, data->name_2x,
203 data->parent, CLK_SET_RATE_PARENT, 2, 1);
204 clk = tegra_clk_register_divider(data->div_name,
205 data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,
206 0, 0, data->div_offset, 1, 0,
207 &clk_doubler_lock);
208 clk = tegra_clk_register_periph_gate(data->gate_name,
209 data->div_name, TEGRA_PERIPH_NO_RESET,
210 clk_base, CLK_SET_RATE_PARENT, data->clk_num,
211 periph_clk_enb_refcnt);
212 *dt_clk = clk;
213 }
214}
215
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index 48d4381357bb..8bb9a226d05c 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -26,6 +26,7 @@
26#include <dt-bindings/clock/tegra114-car.h> 26#include <dt-bindings/clock/tegra114-car.h>
27 27
28#include "clk.h" 28#include "clk.h"
29#include "clk-id.h"
29 30
30#define RST_DFLL_DVCO 0x2F4 31#define RST_DFLL_DVCO 0x2F4
31#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */ 32#define CPU_FINETRIM_SELECT 0x4d4 /* override default prop dlys */
@@ -107,16 +108,6 @@
107#define PLLM_OUT 0x94 108#define PLLM_OUT 0x94
108#define PLLP_OUTA 0xa4 109#define PLLP_OUTA 0xa4
109#define PLLP_OUTB 0xa8 110#define PLLP_OUTB 0xa8
110#define PLLA_OUT 0xb4
111
112#define AUDIO_SYNC_CLK_I2S0 0x4a0
113#define AUDIO_SYNC_CLK_I2S1 0x4a4
114#define AUDIO_SYNC_CLK_I2S2 0x4a8
115#define AUDIO_SYNC_CLK_I2S3 0x4ac
116#define AUDIO_SYNC_CLK_I2S4 0x4b0
117#define AUDIO_SYNC_CLK_SPDIF 0x4b4
118
119#define AUDIO_SYNC_DOUBLER 0x49c
120 111
121#define PMC_CLK_OUT_CNTRL 0x1a8 112#define PMC_CLK_OUT_CNTRL 0x1a8
122#define PMC_DPD_PADS_ORIDE 0x1c 113#define PMC_DPD_PADS_ORIDE 0x1c
@@ -272,7 +263,6 @@ static DEFINE_SPINLOCK(pll_d2_lock);
272static DEFINE_SPINLOCK(pll_u_lock); 263static DEFINE_SPINLOCK(pll_u_lock);
273static DEFINE_SPINLOCK(pll_div_lock); 264static DEFINE_SPINLOCK(pll_div_lock);
274static DEFINE_SPINLOCK(pll_re_lock); 265static DEFINE_SPINLOCK(pll_re_lock);
275static DEFINE_SPINLOCK(clk_doubler_lock);
276static DEFINE_SPINLOCK(clk_out_lock); 266static DEFINE_SPINLOCK(clk_out_lock);
277static DEFINE_SPINLOCK(sysrate_lock); 267static DEFINE_SPINLOCK(sysrate_lock);
278 268
@@ -963,6 +953,186 @@ static const struct clk_div_table pll_re_div_table[] = {
963 { .val = 0, .div = 0 }, 953 { .val = 0, .div = 0 },
964}; 954};
965 955
956static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
957 [tegra_clk_rtc] = { .dt_id = TEGRA114_CLK_RTC, .present = true },
958 [tegra_clk_timer] = { .dt_id = TEGRA114_CLK_TIMER, .present = true },
959 [tegra_clk_uarta] = { .dt_id = TEGRA114_CLK_UARTA, .present = true },
960 [tegra_clk_uartd] = { .dt_id = TEGRA114_CLK_UARTD, .present = true },
961 [tegra_clk_sdmmc2] = { .dt_id = TEGRA114_CLK_SDMMC2, .present = true },
962 [tegra_clk_i2s1] = { .dt_id = TEGRA114_CLK_I2S1, .present = true },
963 [tegra_clk_i2c1] = { .dt_id = TEGRA114_CLK_I2C1, .present = true },
964 [tegra_clk_ndflash] = { .dt_id = TEGRA114_CLK_NDFLASH, .present = true },
965 [tegra_clk_sdmmc1] = { .dt_id = TEGRA114_CLK_SDMMC1, .present = true },
966 [tegra_clk_sdmmc4] = { .dt_id = TEGRA114_CLK_SDMMC4, .present = true },
967 [tegra_clk_pwm] = { .dt_id = TEGRA114_CLK_PWM, .present = true },
968 [tegra_clk_i2s0] = { .dt_id = TEGRA114_CLK_I2S0, .present = true },
969 [tegra_clk_i2s2] = { .dt_id = TEGRA114_CLK_I2S2, .present = true },
970 [tegra_clk_epp_8] = { .dt_id = TEGRA114_CLK_EPP, .present = true },
971 [tegra_clk_gr2d_8] = { .dt_id = TEGRA114_CLK_GR2D, .present = true },
972 [tegra_clk_usbd] = { .dt_id = TEGRA114_CLK_USBD, .present = true },
973 [tegra_clk_isp] = { .dt_id = TEGRA114_CLK_ISP, .present = true },
974 [tegra_clk_gr3d_8] = { .dt_id = TEGRA114_CLK_GR3D, .present = true },
975 [tegra_clk_disp2] = { .dt_id = TEGRA114_CLK_DISP2, .present = true },
976 [tegra_clk_disp1] = { .dt_id = TEGRA114_CLK_DISP1, .present = true },
977 [tegra_clk_host1x_8] = { .dt_id = TEGRA114_CLK_HOST1X, .present = true },
978 [tegra_clk_vcp] = { .dt_id = TEGRA114_CLK_VCP, .present = true },
979 [tegra_clk_apbdma] = { .dt_id = TEGRA114_CLK_APBDMA, .present = true },
980 [tegra_clk_kbc] = { .dt_id = TEGRA114_CLK_KBC, .present = true },
981 [tegra_clk_kfuse] = { .dt_id = TEGRA114_CLK_KFUSE, .present = true },
982 [tegra_clk_sbc1_8] = { .dt_id = TEGRA114_CLK_SBC1, .present = true },
983 [tegra_clk_nor] = { .dt_id = TEGRA114_CLK_NOR, .present = true },
984 [tegra_clk_sbc2_8] = { .dt_id = TEGRA114_CLK_SBC2, .present = true },
985 [tegra_clk_sbc3_8] = { .dt_id = TEGRA114_CLK_SBC3, .present = true },
986 [tegra_clk_i2c5] = { .dt_id = TEGRA114_CLK_I2C5, .present = true },
987 [tegra_clk_dsia] = { .dt_id = TEGRA114_CLK_DSIA, .present = true },
988 [tegra_clk_mipi] = { .dt_id = TEGRA114_CLK_MIPI, .present = true },
989 [tegra_clk_hdmi] = { .dt_id = TEGRA114_CLK_HDMI, .present = true },
990 [tegra_clk_csi] = { .dt_id = TEGRA114_CLK_CSI, .present = true },
991 [tegra_clk_i2c2] = { .dt_id = TEGRA114_CLK_I2C2, .present = true },
992 [tegra_clk_uartc] = { .dt_id = TEGRA114_CLK_UARTC, .present = true },
993 [tegra_clk_mipi_cal] = { .dt_id = TEGRA114_CLK_MIPI_CAL, .present = true },
994 [tegra_clk_emc] = { .dt_id = TEGRA114_CLK_EMC, .present = true },
995 [tegra_clk_usb2] = { .dt_id = TEGRA114_CLK_USB2, .present = true },
996 [tegra_clk_usb3] = { .dt_id = TEGRA114_CLK_USB3, .present = true },
997 [tegra_clk_vde_8] = { .dt_id = TEGRA114_CLK_VDE, .present = true },
998 [tegra_clk_bsea] = { .dt_id = TEGRA114_CLK_BSEA, .present = true },
999 [tegra_clk_bsev] = { .dt_id = TEGRA114_CLK_BSEV, .present = true },
1000 [tegra_clk_i2c3] = { .dt_id = TEGRA114_CLK_I2C3, .present = true },
1001 [tegra_clk_sbc4_8] = { .dt_id = TEGRA114_CLK_SBC4, .present = true },
1002 [tegra_clk_sdmmc3] = { .dt_id = TEGRA114_CLK_SDMMC3, .present = true },
1003 [tegra_clk_owr] = { .dt_id = TEGRA114_CLK_OWR, .present = true },
1004 [tegra_clk_csite] = { .dt_id = TEGRA114_CLK_CSITE, .present = true },
1005 [tegra_clk_la] = { .dt_id = TEGRA114_CLK_LA, .present = true },
1006 [tegra_clk_trace] = { .dt_id = TEGRA114_CLK_TRACE, .present = true },
1007 [tegra_clk_soc_therm] = { .dt_id = TEGRA114_CLK_SOC_THERM, .present = true },
1008 [tegra_clk_dtv] = { .dt_id = TEGRA114_CLK_DTV, .present = true },
1009 [tegra_clk_ndspeed] = { .dt_id = TEGRA114_CLK_NDSPEED, .present = true },
1010 [tegra_clk_i2cslow] = { .dt_id = TEGRA114_CLK_I2CSLOW, .present = true },
1011 [tegra_clk_dsib] = { .dt_id = TEGRA114_CLK_DSIB, .present = true },
1012 [tegra_clk_tsec] = { .dt_id = TEGRA114_CLK_TSEC, .present = true },
1013 [tegra_clk_xusb_host] = { .dt_id = TEGRA114_CLK_XUSB_HOST, .present = true },
1014 [tegra_clk_msenc] = { .dt_id = TEGRA114_CLK_MSENC, .present = true },
1015 [tegra_clk_csus] = { .dt_id = TEGRA114_CLK_CSUS, .present = true },
1016 [tegra_clk_mselect] = { .dt_id = TEGRA114_CLK_MSELECT, .present = true },
1017 [tegra_clk_tsensor] = { .dt_id = TEGRA114_CLK_TSENSOR, .present = true },
1018 [tegra_clk_i2s3] = { .dt_id = TEGRA114_CLK_I2S3, .present = true },
1019 [tegra_clk_i2s4] = { .dt_id = TEGRA114_CLK_I2S4, .present = true },
1020 [tegra_clk_i2c4] = { .dt_id = TEGRA114_CLK_I2C4, .present = true },
1021 [tegra_clk_sbc5_8] = { .dt_id = TEGRA114_CLK_SBC5, .present = true },
1022 [tegra_clk_sbc6_8] = { .dt_id = TEGRA114_CLK_SBC6, .present = true },
1023 [tegra_clk_d_audio] = { .dt_id = TEGRA114_CLK_D_AUDIO, .present = true },
1024 [tegra_clk_apbif] = { .dt_id = TEGRA114_CLK_APBIF, .present = true },
1025 [tegra_clk_dam0] = { .dt_id = TEGRA114_CLK_DAM0, .present = true },
1026 [tegra_clk_dam1] = { .dt_id = TEGRA114_CLK_DAM1, .present = true },
1027 [tegra_clk_dam2] = { .dt_id = TEGRA114_CLK_DAM2, .present = true },
1028 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA114_CLK_HDA2CODEC_2X, .present = true },
1029 [tegra_clk_audio0_2x] = { .dt_id = TEGRA114_CLK_AUDIO0_2X, .present = true },
1030 [tegra_clk_audio1_2x] = { .dt_id = TEGRA114_CLK_AUDIO1_2X, .present = true },
1031 [tegra_clk_audio2_2x] = { .dt_id = TEGRA114_CLK_AUDIO2_2X, .present = true },
1032 [tegra_clk_audio3_2x] = { .dt_id = TEGRA114_CLK_AUDIO3_2X, .present = true },
1033 [tegra_clk_audio4_2x] = { .dt_id = TEGRA114_CLK_AUDIO4_2X, .present = true },
1034 [tegra_clk_spdif_2x] = { .dt_id = TEGRA114_CLK_SPDIF_2X, .present = true },
1035 [tegra_clk_actmon] = { .dt_id = TEGRA114_CLK_ACTMON, .present = true },
1036 [tegra_clk_extern1] = { .dt_id = TEGRA114_CLK_EXTERN1, .present = true },
1037 [tegra_clk_extern2] = { .dt_id = TEGRA114_CLK_EXTERN2, .present = true },
1038 [tegra_clk_extern3] = { .dt_id = TEGRA114_CLK_EXTERN3, .present = true },
1039 [tegra_clk_hda] = { .dt_id = TEGRA114_CLK_HDA, .present = true },
1040 [tegra_clk_se] = { .dt_id = TEGRA114_CLK_SE, .present = true },
1041 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA114_CLK_HDA2HDMI, .present = true },
1042 [tegra_clk_cilab] = { .dt_id = TEGRA114_CLK_CILAB, .present = true },
1043 [tegra_clk_cilcd] = { .dt_id = TEGRA114_CLK_CILCD, .present = true },
1044 [tegra_clk_cile] = { .dt_id = TEGRA114_CLK_CILE, .present = true },
1045 [tegra_clk_dsialp] = { .dt_id = TEGRA114_CLK_DSIALP, .present = true },
1046 [tegra_clk_dsiblp] = { .dt_id = TEGRA114_CLK_DSIBLP, .present = true },
1047 [tegra_clk_dds] = { .dt_id = TEGRA114_CLK_DDS, .present = true },
1048 [tegra_clk_dp2] = { .dt_id = TEGRA114_CLK_DP2, .present = true },
1049 [tegra_clk_amx] = { .dt_id = TEGRA114_CLK_AMX, .present = true },
1050 [tegra_clk_adx] = { .dt_id = TEGRA114_CLK_ADX, .present = true },
1051 [tegra_clk_xusb_ss] = { .dt_id = TEGRA114_CLK_XUSB_SS, .present = true },
1052 [tegra_clk_uartb] = { .dt_id = TEGRA114_CLK_UARTB, .present = true },
1053 [tegra_clk_vfir] = { .dt_id = TEGRA114_CLK_VFIR, .present = true },
1054 [tegra_clk_spdif_in] = { .dt_id = TEGRA114_CLK_SPDIF_IN, .present = true },
1055 [tegra_clk_spdif_out] = { .dt_id = TEGRA114_CLK_SPDIF_OUT, .present = true },
1056 [tegra_clk_vi_8] = { .dt_id = TEGRA114_CLK_VI, .present = true },
1057 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA114_CLK_VI_SENSOR, .present = true },
1058 [tegra_clk_fuse] = { .dt_id = TEGRA114_CLK_FUSE, .present = true },
1059 [tegra_clk_fuse_burn] = { .dt_id = TEGRA114_CLK_FUSE_BURN, .present = true },
1060 [tegra_clk_clk_32k] = { .dt_id = TEGRA114_CLK_CLK_32K, .present = true },
1061 [tegra_clk_clk_m] = { .dt_id = TEGRA114_CLK_CLK_M, .present = true },
1062 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA114_CLK_CLK_M_DIV2, .present = true },
1063 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA114_CLK_CLK_M_DIV4, .present = true },
1064 [tegra_clk_pll_ref] = { .dt_id = TEGRA114_CLK_PLL_REF, .present = true },
1065 [tegra_clk_pll_c] = { .dt_id = TEGRA114_CLK_PLL_C, .present = true },
1066 [tegra_clk_pll_c_out1] = { .dt_id = TEGRA114_CLK_PLL_C_OUT1, .present = true },
1067 [tegra_clk_pll_c2] = { .dt_id = TEGRA114_CLK_PLL_C2, .present = true },
1068 [tegra_clk_pll_c3] = { .dt_id = TEGRA114_CLK_PLL_C3, .present = true },
1069 [tegra_clk_pll_m] = { .dt_id = TEGRA114_CLK_PLL_M, .present = true },
1070 [tegra_clk_pll_m_out1] = { .dt_id = TEGRA114_CLK_PLL_M_OUT1, .present = true },
1071 [tegra_clk_pll_p] = { .dt_id = TEGRA114_CLK_PLL_P, .present = true },
1072 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA114_CLK_PLL_P_OUT1, .present = true },
1073 [tegra_clk_pll_p_out2_int] = { .dt_id = TEGRA114_CLK_PLL_P_OUT2, .present = true },
1074 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA114_CLK_PLL_P_OUT3, .present = true },
1075 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA114_CLK_PLL_P_OUT4, .present = true },
1076 [tegra_clk_pll_a] = { .dt_id = TEGRA114_CLK_PLL_A, .present = true },
1077 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA114_CLK_PLL_A_OUT0, .present = true },
1078 [tegra_clk_pll_d] = { .dt_id = TEGRA114_CLK_PLL_D, .present = true },
1079 [tegra_clk_pll_d_out0] = { .dt_id = TEGRA114_CLK_PLL_D_OUT0, .present = true },
1080 [tegra_clk_pll_d2] = { .dt_id = TEGRA114_CLK_PLL_D2, .present = true },
1081 [tegra_clk_pll_d2_out0] = { .dt_id = TEGRA114_CLK_PLL_D2_OUT0, .present = true },
1082 [tegra_clk_pll_u] = { .dt_id = TEGRA114_CLK_PLL_U, .present = true },
1083 [tegra_clk_pll_u_480m] = { .dt_id = TEGRA114_CLK_PLL_U_480M, .present = true },
1084 [tegra_clk_pll_u_60m] = { .dt_id = TEGRA114_CLK_PLL_U_60M, .present = true },
1085 [tegra_clk_pll_u_48m] = { .dt_id = TEGRA114_CLK_PLL_U_48M, .present = true },
1086 [tegra_clk_pll_u_12m] = { .dt_id = TEGRA114_CLK_PLL_U_12M, .present = true },
1087 [tegra_clk_pll_x] = { .dt_id = TEGRA114_CLK_PLL_X, .present = true },
1088 [tegra_clk_pll_x_out0] = { .dt_id = TEGRA114_CLK_PLL_X_OUT0, .present = true },
1089 [tegra_clk_pll_re_vco] = { .dt_id = TEGRA114_CLK_PLL_RE_VCO, .present = true },
1090 [tegra_clk_pll_re_out] = { .dt_id = TEGRA114_CLK_PLL_RE_OUT, .present = true },
1091 [tegra_clk_pll_e_out0] = { .dt_id = TEGRA114_CLK_PLL_E_OUT0, .present = true },
1092 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA114_CLK_SPDIF_IN_SYNC, .present = true },
1093 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA114_CLK_I2S0_SYNC, .present = true },
1094 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA114_CLK_I2S1_SYNC, .present = true },
1095 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA114_CLK_I2S2_SYNC, .present = true },
1096 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA114_CLK_I2S3_SYNC, .present = true },
1097 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA114_CLK_I2S4_SYNC, .present = true },
1098 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA114_CLK_VIMCLK_SYNC, .present = true },
1099 [tegra_clk_audio0] = { .dt_id = TEGRA114_CLK_AUDIO0, .present = true },
1100 [tegra_clk_audio1] = { .dt_id = TEGRA114_CLK_AUDIO1, .present = true },
1101 [tegra_clk_audio2] = { .dt_id = TEGRA114_CLK_AUDIO2, .present = true },
1102 [tegra_clk_audio3] = { .dt_id = TEGRA114_CLK_AUDIO3, .present = true },
1103 [tegra_clk_audio4] = { .dt_id = TEGRA114_CLK_AUDIO4, .present = true },
1104 [tegra_clk_spdif] = { .dt_id = TEGRA114_CLK_SPDIF, .present = true },
1105 [tegra_clk_clk_out_1] = { .dt_id = TEGRA114_CLK_CLK_OUT_1, .present = true },
1106 [tegra_clk_clk_out_2] = { .dt_id = TEGRA114_CLK_CLK_OUT_2, .present = true },
1107 [tegra_clk_clk_out_3] = { .dt_id = TEGRA114_CLK_CLK_OUT_3, .present = true },
1108 [tegra_clk_blink] = { .dt_id = TEGRA114_CLK_BLINK, .present = true },
1109 [tegra_clk_xusb_host_src] = { .dt_id = TEGRA114_CLK_XUSB_HOST_SRC, .present = true },
1110 [tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
1111 [tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
1112 [tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
1113 [tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
1114 [tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
1115 [tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
1116 [tegra_clk_sclk] = { .dt_id = TEGRA114_CLK_SCLK, .present = true },
1117 [tegra_clk_hclk] = { .dt_id = TEGRA114_CLK_HCLK, .present = true },
1118 [tegra_clk_pclk] = { .dt_id = TEGRA114_CLK_PCLK, .present = true },
1119 [tegra_clk_cclk_g] = { .dt_id = TEGRA114_CLK_CCLK_G, .present = true },
1120 [tegra_clk_cclk_lp] = { .dt_id = TEGRA114_CLK_CCLK_LP, .present = true },
1121 [tegra_clk_dfll_ref] = { .dt_id = TEGRA114_CLK_DFLL_REF, .present = true },
1122 [tegra_clk_dfll_soc] = { .dt_id = TEGRA114_CLK_DFLL_SOC, .present = true },
1123 [tegra_clk_audio0_mux] = { .dt_id = TEGRA114_CLK_AUDIO0_MUX, .present = true },
1124 [tegra_clk_audio1_mux] = { .dt_id = TEGRA114_CLK_AUDIO1_MUX, .present = true },
1125 [tegra_clk_audio2_mux] = { .dt_id = TEGRA114_CLK_AUDIO2_MUX, .present = true },
1126 [tegra_clk_audio3_mux] = { .dt_id = TEGRA114_CLK_AUDIO3_MUX, .present = true },
1127 [tegra_clk_audio4_mux] = { .dt_id = TEGRA114_CLK_AUDIO4_MUX, .present = true },
1128 [tegra_clk_spdif_mux] = { .dt_id = TEGRA114_CLK_SPDIF_MUX, .present = true },
1129 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_1_MUX, .present = true },
1130 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_2_MUX, .present = true },
1131 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA114_CLK_CLK_OUT_3_MUX, .present = true },
1132 [tegra_clk_dsia_mux] = { .dt_id = TEGRA114_CLK_DSIA_MUX, .present = true },
1133 [tegra_clk_dsib_mux] = { .dt_id = TEGRA114_CLK_DSIB_MUX, .present = true },
1134};
1135
966static struct tegra_devclk devclks[] __initdata = { 1136static struct tegra_devclk devclks[] __initdata = {
967 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M }, 1137 { .con_id = "clk_m", .dt_id = TEGRA114_CLK_CLK_M },
968 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF }, 1138 { .con_id = "pll_ref", .dt_id = TEGRA114_CLK_PLL_REF },
@@ -1324,20 +1494,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1324 CLK_SET_RATE_PARENT, 1, 2); 1494 CLK_SET_RATE_PARENT, 1, 2);
1325 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk; 1495 clks[TEGRA114_CLK_PLL_D2_OUT0] = clk;
1326 1496
1327 /* PLLA */
1328 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, pmc, 0,
1329 &pll_a_params, NULL);
1330 clks[TEGRA114_CLK_PLL_A] = clk;
1331
1332 /* PLLA_OUT0 */
1333 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
1334 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
1335 8, 8, 1, NULL);
1336 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
1337 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
1338 CLK_SET_RATE_PARENT, 0, NULL);
1339 clks[TEGRA114_CLK_PLL_A_OUT0] = clk;
1340
1341 /* PLLRE */ 1497 /* PLLRE */
1342 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, 1498 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc,
1343 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq); 1499 0, &pll_re_vco_params, &pll_re_lock, pll_ref_freq);
@@ -1354,10 +1510,6 @@ static void __init tegra114_pll_init(void __iomem *clk_base,
1354 clks[TEGRA114_CLK_PLL_E_OUT0] = clk; 1510 clks[TEGRA114_CLK_PLL_E_OUT0] = clk;
1355} 1511}
1356 1512
1357static const char *mux_audio_sync_clk[] = { "spdif_in_sync", "i2s0_sync",
1358 "i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
1359};
1360
1361static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2", 1513static const char *clk_out1_parents[] = { "clk_m", "clk_m_div2",
1362 "clk_m_div4", "extern1", 1514 "clk_m_div4", "extern1",
1363}; 1515};
@@ -1370,184 +1522,6 @@ static const char *clk_out3_parents[] = { "clk_m", "clk_m_div2",
1370 "clk_m_div4", "extern3", 1522 "clk_m_div4", "extern3",
1371}; 1523};
1372 1524
1373static void __init tegra114_audio_clk_init(void __iomem *clk_base)
1374{
1375 struct clk *clk;
1376
1377 /* spdif_in_sync */
1378 clk = tegra_clk_register_sync_source("spdif_in_sync", 24000000,
1379 24000000);
1380 clks[TEGRA114_CLK_SPDIF_IN_SYNC] = clk;
1381
1382 /* i2s0_sync */
1383 clk = tegra_clk_register_sync_source("i2s0_sync", 24000000, 24000000);
1384 clks[TEGRA114_CLK_I2S0_SYNC] = clk;
1385
1386 /* i2s1_sync */
1387 clk = tegra_clk_register_sync_source("i2s1_sync", 24000000, 24000000);
1388 clks[TEGRA114_CLK_I2S1_SYNC] = clk;
1389
1390 /* i2s2_sync */
1391 clk = tegra_clk_register_sync_source("i2s2_sync", 24000000, 24000000);
1392 clks[TEGRA114_CLK_I2S2_SYNC] = clk;
1393
1394 /* i2s3_sync */
1395 clk = tegra_clk_register_sync_source("i2s3_sync", 24000000, 24000000);
1396 clks[TEGRA114_CLK_I2S3_SYNC] = clk;
1397
1398 /* i2s4_sync */
1399 clk = tegra_clk_register_sync_source("i2s4_sync", 24000000, 24000000);
1400 clks[TEGRA114_CLK_I2S4_SYNC] = clk;
1401
1402 /* vimclk_sync */
1403 clk = tegra_clk_register_sync_source("vimclk_sync", 24000000, 24000000);
1404 clks[TEGRA114_CLK_VIMCLK_SYNC] = clk;
1405
1406 /* audio0 */
1407 clk = clk_register_mux(NULL, "audio0_mux", mux_audio_sync_clk,
1408 ARRAY_SIZE(mux_audio_sync_clk),
1409 CLK_SET_RATE_NO_REPARENT,
1410 clk_base + AUDIO_SYNC_CLK_I2S0, 0, 3, 0,
1411 NULL);
1412 clks[TEGRA114_CLK_AUDIO0_MUX] = clk;
1413 clk = clk_register_gate(NULL, "audio0", "audio0_mux", 0,
1414 clk_base + AUDIO_SYNC_CLK_I2S0, 4,
1415 CLK_GATE_SET_TO_DISABLE, NULL);
1416 clks[TEGRA114_CLK_AUDIO0] = clk;
1417
1418 /* audio1 */
1419 clk = clk_register_mux(NULL, "audio1_mux", mux_audio_sync_clk,
1420 ARRAY_SIZE(mux_audio_sync_clk),
1421 CLK_SET_RATE_NO_REPARENT,
1422 clk_base + AUDIO_SYNC_CLK_I2S1, 0, 3, 0,
1423 NULL);
1424 clks[TEGRA114_CLK_AUDIO1_MUX] = clk;
1425 clk = clk_register_gate(NULL, "audio1", "audio1_mux", 0,
1426 clk_base + AUDIO_SYNC_CLK_I2S1, 4,
1427 CLK_GATE_SET_TO_DISABLE, NULL);
1428 clks[TEGRA114_CLK_AUDIO1] = clk;
1429
1430 /* audio2 */
1431 clk = clk_register_mux(NULL, "audio2_mux", mux_audio_sync_clk,
1432 ARRAY_SIZE(mux_audio_sync_clk),
1433 CLK_SET_RATE_NO_REPARENT,
1434 clk_base + AUDIO_SYNC_CLK_I2S2, 0, 3, 0,
1435 NULL);
1436 clks[TEGRA114_CLK_AUDIO2_MUX] = clk;
1437 clk = clk_register_gate(NULL, "audio2", "audio2_mux", 0,
1438 clk_base + AUDIO_SYNC_CLK_I2S2, 4,
1439 CLK_GATE_SET_TO_DISABLE, NULL);
1440 clks[TEGRA114_CLK_AUDIO2] = clk;
1441
1442 /* audio3 */
1443 clk = clk_register_mux(NULL, "audio3_mux", mux_audio_sync_clk,
1444 ARRAY_SIZE(mux_audio_sync_clk),
1445 CLK_SET_RATE_NO_REPARENT,
1446 clk_base + AUDIO_SYNC_CLK_I2S3, 0, 3, 0,
1447 NULL);
1448 clks[TEGRA114_CLK_AUDIO3_MUX] = clk;
1449 clk = clk_register_gate(NULL, "audio3", "audio3_mux", 0,
1450 clk_base + AUDIO_SYNC_CLK_I2S3, 4,
1451 CLK_GATE_SET_TO_DISABLE, NULL);
1452 clks[TEGRA114_CLK_AUDIO3] = clk;
1453
1454 /* audio4 */
1455 clk = clk_register_mux(NULL, "audio4_mux", mux_audio_sync_clk,
1456 ARRAY_SIZE(mux_audio_sync_clk),
1457 CLK_SET_RATE_NO_REPARENT,
1458 clk_base + AUDIO_SYNC_CLK_I2S4, 0, 3, 0,
1459 NULL);
1460 clks[TEGRA114_CLK_AUDIO4_MUX] = clk;
1461 clk = clk_register_gate(NULL, "audio4", "audio4_mux", 0,
1462 clk_base + AUDIO_SYNC_CLK_I2S4, 4,
1463 CLK_GATE_SET_TO_DISABLE, NULL);
1464 clks[TEGRA114_CLK_AUDIO4] = clk;
1465
1466 /* spdif */
1467 clk = clk_register_mux(NULL, "spdif_mux", mux_audio_sync_clk,
1468 ARRAY_SIZE(mux_audio_sync_clk),
1469 CLK_SET_RATE_NO_REPARENT,
1470 clk_base + AUDIO_SYNC_CLK_SPDIF, 0, 3, 0,
1471 NULL);
1472 clks[TEGRA114_CLK_SPDIF_MUX] = clk;
1473 clk = clk_register_gate(NULL, "spdif", "spdif_mux", 0,
1474 clk_base + AUDIO_SYNC_CLK_SPDIF, 4,
1475 CLK_GATE_SET_TO_DISABLE, NULL);
1476 clks[TEGRA114_CLK_SPDIF] = clk;
1477
1478 /* audio0_2x */
1479 clk = clk_register_fixed_factor(NULL, "audio0_doubler", "audio0",
1480 CLK_SET_RATE_PARENT, 2, 1);
1481 clk = tegra_clk_register_divider("audio0_div", "audio0_doubler",
1482 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 24, 1,
1483 0, &clk_doubler_lock);
1484 clk = tegra_clk_register_periph_gate("audio0_2x", "audio0_div",
1485 TEGRA_PERIPH_NO_RESET, clk_base,
1486 CLK_SET_RATE_PARENT, 113,
1487 periph_clk_enb_refcnt);
1488 clks[TEGRA114_CLK_AUDIO0_2X] = clk;
1489
1490 /* audio1_2x */
1491 clk = clk_register_fixed_factor(NULL, "audio1_doubler", "audio1",
1492 CLK_SET_RATE_PARENT, 2, 1);
1493 clk = tegra_clk_register_divider("audio1_div", "audio1_doubler",
1494 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 25, 1,
1495 0, &clk_doubler_lock);
1496 clk = tegra_clk_register_periph_gate("audio1_2x", "audio1_div",
1497 TEGRA_PERIPH_NO_RESET, clk_base,
1498 CLK_SET_RATE_PARENT, 114,
1499 periph_clk_enb_refcnt);
1500 clks[TEGRA114_CLK_AUDIO1_2X] = clk;
1501
1502 /* audio2_2x */
1503 clk = clk_register_fixed_factor(NULL, "audio2_doubler", "audio2",
1504 CLK_SET_RATE_PARENT, 2, 1);
1505 clk = tegra_clk_register_divider("audio2_div", "audio2_doubler",
1506 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 26, 1,
1507 0, &clk_doubler_lock);
1508 clk = tegra_clk_register_periph_gate("audio2_2x", "audio2_div",
1509 TEGRA_PERIPH_NO_RESET, clk_base,
1510 CLK_SET_RATE_PARENT, 115,
1511 periph_clk_enb_refcnt);
1512 clks[TEGRA114_CLK_AUDIO2_2X] = clk;
1513
1514 /* audio3_2x */
1515 clk = clk_register_fixed_factor(NULL, "audio3_doubler", "audio3",
1516 CLK_SET_RATE_PARENT, 2, 1);
1517 clk = tegra_clk_register_divider("audio3_div", "audio3_doubler",
1518 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 27, 1,
1519 0, &clk_doubler_lock);
1520 clk = tegra_clk_register_periph_gate("audio3_2x", "audio3_div",
1521 TEGRA_PERIPH_NO_RESET, clk_base,
1522 CLK_SET_RATE_PARENT, 116,
1523 periph_clk_enb_refcnt);
1524 clks[TEGRA114_CLK_AUDIO3_2X] = clk;
1525
1526 /* audio4_2x */
1527 clk = clk_register_fixed_factor(NULL, "audio4_doubler", "audio4",
1528 CLK_SET_RATE_PARENT, 2, 1);
1529 clk = tegra_clk_register_divider("audio4_div", "audio4_doubler",
1530 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 28, 1,
1531 0, &clk_doubler_lock);
1532 clk = tegra_clk_register_periph_gate("audio4_2x", "audio4_div",
1533 TEGRA_PERIPH_NO_RESET, clk_base,
1534 CLK_SET_RATE_PARENT, 117,
1535 periph_clk_enb_refcnt);
1536 clks[TEGRA114_CLK_AUDIO4_2X] = clk;
1537
1538 /* spdif_2x */
1539 clk = clk_register_fixed_factor(NULL, "spdif_doubler", "spdif",
1540 CLK_SET_RATE_PARENT, 2, 1);
1541 clk = tegra_clk_register_divider("spdif_div", "spdif_doubler",
1542 clk_base + AUDIO_SYNC_DOUBLER, 0, 0, 29, 1,
1543 0, &clk_doubler_lock);
1544 clk = tegra_clk_register_periph_gate("spdif_2x", "spdif_div",
1545 TEGRA_PERIPH_NO_RESET, clk_base,
1546 CLK_SET_RATE_PARENT, 118,
1547 periph_clk_enb_refcnt);
1548 clks[TEGRA114_CLK_SPDIF_2X] = clk;
1549}
1550
1551static void __init tegra114_pmc_clk_init(void __iomem *pmc_base) 1525static void __init tegra114_pmc_clk_init(void __iomem *pmc_base)
1552{ 1526{
1553 struct clk *clk; 1527 struct clk *clk;
@@ -2194,7 +2168,7 @@ static void __init tegra114_clock_init(struct device_node *np)
2194 tegra114_fixed_clk_init(clk_base); 2168 tegra114_fixed_clk_init(clk_base);
2195 tegra114_pll_init(clk_base, pmc_base); 2169 tegra114_pll_init(clk_base, pmc_base);
2196 tegra114_periph_clk_init(clk_base); 2170 tegra114_periph_clk_init(clk_base);
2197 tegra114_audio_clk_init(clk_base); 2171 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, &pll_a_params);
2198 tegra114_pmc_clk_init(pmc_base); 2172 tegra114_pmc_clk_init(pmc_base);
2199 tegra114_super_clk_init(clk_base); 2173 tegra114_super_clk_init(clk_base);
2200 2174
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index f742c7dda4cc..3306e41e6270 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -593,6 +593,10 @@ struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
593void tegra_add_of_provider(struct device_node *np); 593void tegra_add_of_provider(struct device_node *np);
594void tegra_register_devclks(struct tegra_devclk *dev_clks, int num); 594void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
595 595
596void tegra_audio_clk_init(void __iomem *clk_base,
597 void __iomem *pmc_base, struct tegra_clk *tegra_clks,
598 struct tegra_clk_pll_params *pll_params);
599
596void tegra114_clock_tune_cpu_trimmers_high(void); 600void tegra114_clock_tune_cpu_trimmers_high(void);
597void tegra114_clock_tune_cpu_trimmers_low(void); 601void tegra114_clock_tune_cpu_trimmers_low(void);
598void tegra114_clock_tune_cpu_trimmers_init(void); 602void tegra114_clock_tune_cpu_trimmers_init(void);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-24 08:45:27 -0400