16 files changed, 897 insertions, 127 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 62c227104781..74c6b42d2597 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -34,6 +34,8 @@
 #define MAX(a,b)                   (((a)>(b))?(a):(b))
 #define MIN(a,b)                   (((a)<(b))?(a):(b))
 
+int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,
+                           struct radeon_cs_reloc **cs_reloc);
 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
                                           struct radeon_cs_reloc **cs_reloc);
 
@@ -507,20 +509,28 @@ static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
                 /* height is npipes htiles aligned == npipes * 8 pixel aligned */
                 nby = round_up(nby, track->npipes * 8);
         } else {
+                /* always assume 8x8 htile */
+                /* align is htile align * 8, htile align vary according to
+                 * number of pipe and tile width and nby
+                 */
                 switch (track->npipes) {
                 case 8:
+                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
                         nbx = round_up(nbx, 64 * 8);
                         nby = round_up(nby, 64 * 8);
                         break;
                 case 4:
+                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
                         nbx = round_up(nbx, 64 * 8);
                         nby = round_up(nby, 32 * 8);
                         break;
                 case 2:
+                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
                         nbx = round_up(nbx, 32 * 8);
                         nby = round_up(nby, 32 * 8);
                         break;
                 case 1:
+                        /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/
                         nbx = round_up(nbx, 32 * 8);
                         nby = round_up(nby, 16 * 8);
                         break;
@@ -531,9 +541,10 @@ static int evergreen_cs_track_validate_htile(struct radeon_cs_parser *p,
                 }
         }
         /* compute number of htile */
-        nbx = nbx / 8;
-        nby = nby / 8;
-        size = nbx * nby * 4;
+        nbx = nbx >> 3;
+        nby = nby >> 3;
+        /* size must be aligned on npipes * 2K boundary */
+        size = roundup(nbx * nby * 4, track->npipes * (2 << 10));
         size += track->htile_offset;
 
         if (size > radeon_bo_size(track->htile_bo)) {
@@ -1790,6 +1801,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case DB_HTILE_SURFACE:
                 /* 8x8 only */
                 track->htile_surface = radeon_get_ib_value(p, idx);
+                /* force 8x8 htile width and height */
+                ib[idx] |= 3;
                 track->db_dirty = true;
                 break;
         case CB_IMMED0_BASE:
@@ -2243,6 +2256,18 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
                 command = radeon_get_ib_value(p, idx+4);
                 size = command & 0x1fffff;
                 info = radeon_get_ib_value(p, idx+1);
+                if ((((info & 0x60000000) >> 29) != 0) || /* src = GDS or DATA */
+                    (((info & 0x00300000) >> 20) != 0) || /* dst = GDS */
+                    ((((info & 0x00300000) >> 20) == 0) &&
+                     (command & PACKET3_CP_DMA_CMD_DAS)) || /* dst = register */
+                    ((((info & 0x60000000) >> 29) == 0) &&
+                     (command & PACKET3_CP_DMA_CMD_SAS))) { /* src = register */
+                        /* non mem to mem copies requires dw aligned count */
+                        if (size % 4) {
+                                DRM_ERROR("CP DMA command requires dw count alignment\n");
+                                return -EINVAL;
+                        }
+                }
                 if (command & PACKET3_CP_DMA_CMD_SAS) {
                         /* src address space is register */
                         /* GDS is ok */
@@ -2804,6 +2829,455 @@ int evergreen_cs_parse(struct radeon_cs_parser *p)
         return 0;
 }
 
+/*
+ *  DMA
+ */
+
+#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)
+#define GET_DMA_COUNT(h) ((h) & 0x000fffff)
+#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)
+#define GET_DMA_NEW(h) (((h) & 0x04000000) >> 26)
+#define GET_DMA_MISC(h) (((h) & 0x0700000) >> 20)
+
+/**
+ * evergreen_dma_cs_parse() - parse the DMA IB
+ * @p:          parser structure holding parsing context.
+ *
+ * Parses the DMA IB from the CS ioctl and updates
+ * the GPU addresses based on the reloc information and
+ * checks for errors. (Evergreen-Cayman)
+ * Returns 0 for success and an error on failure.
+ **/
+int evergreen_dma_cs_parse(struct radeon_cs_parser *p)
+{
+        struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
+        struct radeon_cs_reloc *src_reloc, *dst_reloc, *dst2_reloc;
+        u32 header, cmd, count, tiled, new_cmd, misc;
+        volatile u32 *ib = p->ib.ptr;
+        u32 idx, idx_value;
+        u64 src_offset, dst_offset, dst2_offset;
+        int r;
+
+        do {
+                if (p->idx >= ib_chunk->length_dw) {
+                        DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
+                                  p->idx, ib_chunk->length_dw);
+                        return -EINVAL;
+                }
+                idx = p->idx;
+                header = radeon_get_ib_value(p, idx);
+                cmd = GET_DMA_CMD(header);
+                count = GET_DMA_COUNT(header);
+                tiled = GET_DMA_T(header);
+                new_cmd = GET_DMA_NEW(header);
+                misc = GET_DMA_MISC(header);
+
+                switch (cmd) {
+                case DMA_PACKET_WRITE:
+                        r = r600_dma_cs_next_reloc(p, &dst_reloc);
+                        if (r) {
+                                DRM_ERROR("bad DMA_PACKET_WRITE\n");
+                                return -EINVAL;
+                        }
+                        if (tiled) {
+                                dst_offset = ib[idx+1];
+                                dst_offset <<= 8;
+
+                                ib[idx+1] += (u32)(dst_reloc->lobj.gpu_offset >> 8);
+                                p->idx += count + 7;