16 files changed, 1938 insertions, 4 deletions

diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
index e3264c19aabe..72a0c788b472 100644
--- a/arch/mips/include/asm/netlogic/haldefs.h
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -40,6 +40,9 @@
  * and will provide a way to read 32/64 bit memory mapped registers in
  * all ABIs
  */
+#if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP)
+#error "o32 compile not supported on XLP yet"
+#endif
 /*
  * For o32 compilation, we have to disable interrupts and enable KX bit to
  * access 64 bit addresses or data.
@@ -133,10 +136,28 @@ nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val)
 /* Location where IO base is mapped */
 extern uint64_t nlm_io_base;
 
+#if defined(CONFIG_CPU_XLP)
+static inline uint64_t
+nlm_pcicfg_base(uint32_t devoffset)
+{
+        return nlm_io_base + devoffset;
+}
+
+static inline uint64_t
+nlm_xkphys_map_pcibar0(uint64_t pcibase)
+{
+        uint64_t paddr;
+
+        paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu;
+        return (uint64_t)0x9000000000000000 | paddr;
+}
+#elif defined(CONFIG_CPU_XLR)
+
 static inline uint64_t
 nlm_mmio_base(uint32_t devoffset)
 {
         return nlm_io_base + devoffset;
 }
+#endif
 
 #endif
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
new file mode 100644
index 000000000000..ca95133f1ad1
--- /dev/null
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __NLM_HAL_BRIDGE_H__
+#define __NLM_HAL_BRIDGE_H__
+
+/**
+* @file_name mio.h
+* @author Netlogic Microsystems
+* @brief Basic definitions of XLP memory and io subsystem
+*/
+
+/*
+ * BRIDGE specific registers
+ *
+ * These registers start after the PCIe header, which has 0x40
+ * standard entries
+ */
+#define BRIDGE_MODE                     0x00
+#define BRIDGE_PCI_CFG_BASE             0x01
+#define BRIDGE_PCI_CFG_LIMIT            0x02
+#define BRIDGE_PCIE_CFG_BASE            0x03
+#define BRIDGE_PCIE_CFG_LIMIT           0x04
+#define BRIDGE_BUSNUM_BAR0              0x05
+#define BRIDGE_BUSNUM_BAR1              0x06
+#define BRIDGE_BUSNUM_BAR2              0x07
+#define BRIDGE_BUSNUM_BAR3              0x08
+#define BRIDGE_BUSNUM_BAR4              0x09
+#define BRIDGE_BUSNUM_BAR5              0x0a
+#define BRIDGE_BUSNUM_BAR6              0x0b
+#define BRIDGE_FLASH_BAR0               0x0c
+#define BRIDGE_FLASH_BAR1               0x0d
+#define BRIDGE_FLASH_BAR2               0x0e
+#define BRIDGE_FLASH_BAR3               0x0f
+#define BRIDGE_FLASH_LIMIT0             0x10
+#define BRIDGE_FLASH_LIMIT1             0x11
+#define BRIDGE_FLASH_LIMIT2             0x12
+#define BRIDGE_FLASH_LIMIT3             0x13
+
+#define BRIDGE_DRAM_BAR(i)              (0x14 + (i))
+#define BRIDGE_DRAM_BAR0                0x14
+#define BRIDGE_DRAM_BAR1                0x15
+#define BRIDGE_DRAM_BAR2                0x16
+#define BRIDGE_DRAM_BAR3                0x17
+#define BRIDGE_DRAM_BAR4                0x18
+#define BRIDGE_DRAM_BAR5                0x19
+#define BRIDGE_DRAM_BAR6                0x1a
+#define BRIDGE_DRAM_BAR7                0x1b
+
+#define BRIDGE_DRAM_LIMIT(i)            (0x1c + (i))
+#define BRIDGE_DRAM_LIMIT0              0x1c
+#define BRIDGE_DRAM_LIMIT1              0x1d
+#define BRIDGE_DRAM_LIMIT2              0x1e
+#define BRIDGE_DRAM_LIMIT3              0x1f
+#define BRIDGE_DRAM_LIMIT4              0x20
+#define BRIDGE_DRAM_LIMIT5              0x21
+#define BRIDGE_DRAM_LIMIT6              0x22
+#define BRIDGE_DRAM_LIMIT7              0x23
+
+#define BRIDGE_DRAM_NODE_TRANSLN0       0x24
+#define BRIDGE_DRAM_NODE_TRANSLN1       0x25
+#define BRIDGE_DRAM_NODE_TRANSLN2       0x26
+#define BRIDGE_DRAM_NODE_TRANSLN3       0x27
+#define BRIDGE_DRAM_NODE_TRANSLN4       0x28
+#define BRIDGE_DRAM_NODE_TRANSLN5       0x29
+#define BRIDGE_DRAM_NODE_TRANSLN6       0x2a
+#define BRIDGE_DRAM_NODE_TRANSLN7       0x2b
+#define BRIDGE_DRAM_CHNL_TRANSLN0       0x2c
+#define BRIDGE_DRAM_CHNL_TRANSLN1       0x2d
+#define BRIDGE_DRAM_CHNL_TRANSLN2       0x2e
+#define BRIDGE_DRAM_CHNL_TRANSLN3       0x2f
+#define BRIDGE_DRAM_CHNL_TRANSLN4       0x30
+#define BRIDGE_DRAM_CHNL_TRANSLN5       0x31
+#define BRIDGE_DRAM_CHNL_TRANSLN6       0x32
+#define BRIDGE_DRAM_CHNL_TRANSLN7       0x33
+#define BRIDGE_PCIEMEM_BASE0            0x34
+#define BRIDGE_PCIEMEM_BASE1            0x35
+#define BRIDGE_PCIEMEM_BASE2            0x36
+#define BRIDGE_PCIEMEM_BASE3            0x37
+#define BRIDGE_PCIEMEM_LIMIT0           0x38
+#define BRIDGE_PCIEMEM_LIMIT1           0x39
+#define BRIDGE_PCIEMEM_LIMIT2           0x3a
+#define BRIDGE_PCIEMEM_LIMIT3           0x3b
+#define BRIDGE_PCIEIO_BASE0             0x3c