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-rw-r--r--drivers/edac/r82600_edac.c27
1 files changed, 18 insertions, 9 deletions
diff --git a/drivers/edac/r82600_edac.c b/drivers/edac/r82600_edac.c
index c41b375e1f38..aea1a0c0eca3 100644
--- a/drivers/edac/r82600_edac.c
+++ b/drivers/edac/r82600_edac.c
@@ -179,10 +179,11 @@ static int r82600_process_error_info(struct mem_ctl_info *mci,
179 error_found = 1; 179 error_found = 1;
180 180
181 if (handle_errors) 181 if (handle_errors)
182 edac_mc_handle_ce(mci, page, 0, /* not avail */ 182 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
183 syndrome, 183 page, 0, syndrome,
184 edac_mc_find_csrow_by_page(mci, page), 184 edac_mc_find_csrow_by_page(mci, page),
185 0, mci->ctl_name); 185 0, -1,
186 mci->ctl_name, "", NULL);
186 } 187 }
187 188
188 if (info->eapr & BIT(1)) { /* UE? */ 189 if (info->eapr & BIT(1)) { /* UE? */
@@ -190,9 +191,11 @@ static int r82600_process_error_info(struct mem_ctl_info *mci,
190 191
191 if (handle_errors) 192 if (handle_errors)
192 /* 82600 doesn't give enough info */ 193 /* 82600 doesn't give enough info */
193 edac_mc_handle_ue(mci, page, 0, 194 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
194 edac_mc_find_csrow_by_page(mci, page), 195 page, 0, 0,
195 mci->ctl_name); 196 edac_mc_find_csrow_by_page(mci, page),
197 0, -1,
198 mci->ctl_name, "", NULL);
196 } 199 }
197 200
198 return error_found; 201 return error_found;
@@ -267,6 +270,7 @@ static void r82600_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
267static int r82600_probe1(struct pci_dev *pdev, int dev_idx) 270static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
268{ 271{
269 struct mem_ctl_info *mci; 272 struct mem_ctl_info *mci;
273 struct edac_mc_layer layers[2];
270 u8 dramcr; 274 u8 dramcr;
271 u32 eapr; 275 u32 eapr;
272 u32 scrub_disabled; 276 u32 scrub_disabled;
@@ -281,8 +285,13 @@ static int r82600_probe1(struct pci_dev *pdev, int dev_idx)
281 debugf2("%s(): sdram refresh rate = %#0x\n", __func__, 285 debugf2("%s(): sdram refresh rate = %#0x\n", __func__,
282 sdram_refresh_rate); 286 sdram_refresh_rate);
283 debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr); 287 debugf2("%s(): DRAMC register = %#0x\n", __func__, dramcr);
284 mci = edac_mc_alloc(0, R82600_NR_CSROWS, R82600_NR_CHANS, 0); 288 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
285 289 layers[0].size = R82600_NR_CSROWS;
290 layers[0].is_virt_csrow = true;
291 layers[1].type = EDAC_MC_LAYER_CHANNEL;
292 layers[1].size = R82600_NR_CHANS;
293 layers[1].is_virt_csrow = false;
294 mci = new_edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
286 if (mci == NULL) 295 if (mci == NULL)
287 return -ENOMEM; 296 return -ENOMEM;
288 297