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-rw-r--r--arch/arm/mach-at91rm9200/Makefile6
-rw-r--r--arch/arm/mach-at91rm9200/at91sam9260.c294
-rw-r--r--arch/arm/mach-at91rm9200/at91sam9261.c289
-rw-r--r--arch/arm/mach-at91rm9200/generic.h5
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9260.h125
-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam9261.h292
6 files changed, 1008 insertions, 3 deletions
diff --git a/arch/arm/mach-at91rm9200/Makefile b/arch/arm/mach-at91rm9200/Makefile
index 568d8d76cde0..40e89bf459f1 100644
--- a/arch/arm/mach-at91rm9200/Makefile
+++ b/arch/arm/mach-at91rm9200/Makefile
@@ -11,10 +11,10 @@ obj-$(CONFIG_PM) += pm.o
11 11
12# CPU-specific support 12# CPU-specific support
13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.c 13obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.c
14obj-$(CONFIG_ARCH_AT91SAM9260) += 14obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o
15obj-$(CONFIG_ARCH_AT91SAM9261) += 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o
16 16
17# AT91RM9200 Board-specific support 17# AT91RM9200 board-specific support
18obj-$(CONFIG_MACH_ONEARM) += board-1arm.o 18obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
19obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o 19obj-$(CONFIG_ARCH_AT91RM9200DK) += board-dk.o
20obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o 20obj-$(CONFIG_MACH_AT91RM9200EK) += board-ek.o
diff --git a/arch/arm/mach-at91rm9200/at91sam9260.c b/arch/arm/mach-at91rm9200/at91sam9260.c
new file mode 100644
index 000000000000..203f073a53e6
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9260.c
@@ -0,0 +1,294 @@
1/*
2 * arch/arm/mach-at91rm9200/at91sam9260.c
3 *
4 * Copyright (C) 2006 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/arch/at91sam9260.h>
18#include <asm/arch/at91_pmc.h>
19
20#include "generic.h"
21#include "clock.h"
22
23static struct map_desc at91sam9260_io_desc[] __initdata = {
24 {
25 .virtual = AT91_VA_BASE_SYS,
26 .pfn = __phys_to_pfn(AT91_BASE_SYS),
27 .length = SZ_16K,
28 .type = MT_DEVICE,
29 }, {
30 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
31 .pfn = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
32 .length = AT91SAM9260_SRAM0_SIZE,
33 .type = MT_DEVICE,
34 }, {
35 .virtual = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE - AT91SAM9260_SRAM1_SIZE,
36 .pfn = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
37 .length = AT91SAM9260_SRAM1_SIZE,
38 .type = MT_DEVICE,
39 },
40};
41
42/* --------------------------------------------------------------------
43 * Clocks
44 * -------------------------------------------------------------------- */
45
46/*
47 * The peripheral clocks.
48 */
49static struct clk pioA_clk = {
50 .name = "pioA_clk",
51 .pmc_mask = 1 << AT91SAM9260_ID_PIOA,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk pioB_clk = {
55 .name = "pioB_clk",
56 .pmc_mask = 1 << AT91SAM9260_ID_PIOB,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk pioC_clk = {
60 .name = "pioC_clk",
61 .pmc_mask = 1 << AT91SAM9260_ID_PIOC,
62 .type = CLK_TYPE_PERIPHERAL,
63};
64static struct clk adc_clk = {
65 .name = "adc_clk",
66 .pmc_mask = 1 << AT91SAM9260_ID_ADC,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk usart0_clk = {
70 .name = "usart0_clk",
71 .pmc_mask = 1 << AT91SAM9260_ID_US0,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk usart1_clk = {
75 .name = "usart1_clk",
76 .pmc_mask = 1 << AT91SAM9260_ID_US1,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk usart2_clk = {
80 .name = "usart2_clk",
81 .pmc_mask = 1 << AT91SAM9260_ID_US2,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk mmc_clk = {
85 .name = "mci_clk",
86 .pmc_mask = 1 << AT91SAM9260_ID_MCI,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk udc_clk = {
90 .name = "udc_clk",
91 .pmc_mask = 1 << AT91SAM9260_ID_UDP,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk twi_clk = {
95 .name = "twi_clk",
96 .pmc_mask = 1 << AT91SAM9260_ID_TWI,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk spi0_clk = {
100 .name = "spi0_clk",
101 .pmc_mask = 1 << AT91SAM9260_ID_SPI0,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk spi1_clk = {
105 .name = "spi1_clk",
106 .pmc_mask = 1 << AT91SAM9260_ID_SPI1,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109static struct clk ohci_clk = {
110 .name = "ohci_clk",
111 .pmc_mask = 1 << AT91SAM9260_ID_UHP,
112 .type = CLK_TYPE_PERIPHERAL,
113};
114static struct clk ether_clk = {
115 .name = "ether_clk",
116 .pmc_mask = 1 << AT91SAM9260_ID_EMAC,
117 .type = CLK_TYPE_PERIPHERAL,
118};
119static struct clk isi_clk = {
120 .name = "isi_clk",
121 .pmc_mask = 1 << AT91SAM9260_ID_ISI,
122 .type = CLK_TYPE_PERIPHERAL,
123};
124static struct clk usart3_clk = {
125 .name = "usart3_clk",
126 .pmc_mask = 1 << AT91SAM9260_ID_US3,
127 .type = CLK_TYPE_PERIPHERAL,
128};
129static struct clk usart4_clk = {
130 .name = "usart4_clk",
131 .pmc_mask = 1 << AT91SAM9260_ID_US4,
132 .type = CLK_TYPE_PERIPHERAL,
133};
134static struct clk usart5_clk = {
135 .name = "usart5_clk",
136 .pmc_mask = 1 << AT91SAM9260_ID_US5,
137 .type = CLK_TYPE_PERIPHERAL,
138};
139
140static struct clk *periph_clocks[] __initdata = {
141 &pioA_clk,
142 &pioB_clk,
143 &pioC_clk,
144 &adc_clk,
145 &usart0_clk,
146 &usart1_clk,
147 &usart2_clk,
148 &mmc_clk,
149 &udc_clk,
150 &twi_clk,
151 &spi0_clk,
152 &spi1_clk,
153 // ssc
154 // tc0 .. tc2
155 &ohci_clk,
156 &ether_clk,
157 &isi_clk,
158 &usart3_clk,
159 &usart4_clk,
160 &usart5_clk,
161 // tc3 .. tc5
162 // irq0 .. irq2
163};
164
165/*
166 * The two programmable clocks.
167 * You must configure pin multiplexing to bring these signals out.
168 */
169static struct clk pck0 = {
170 .name = "pck0",
171 .pmc_mask = AT91_PMC_PCK0,
172 .type = CLK_TYPE_PROGRAMMABLE,
173 .id = 0,
174};
175static struct clk pck1 = {
176 .name = "pck1",
177 .pmc_mask = AT91_PMC_PCK1,
178 .type = CLK_TYPE_PROGRAMMABLE,
179 .id = 1,
180};
181
182static void __init at91sam9260_register_clocks(void)
183{
184 int i;
185
186 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
187 clk_register(periph_clocks[i]);
188
189 clk_register(&pck0);
190 clk_register(&pck1);
191}
192
193/* --------------------------------------------------------------------
194 * GPIO
195 * -------------------------------------------------------------------- */
196
197static struct at91_gpio_bank at91sam9260_gpio[] = {
198 {
199 .id = AT91SAM9260_ID_PIOA,
200 .offset = AT91_PIOA,
201 .clock = &pioA_clk,
202 }, {
203 .id = AT91SAM9260_ID_PIOB,
204 .offset = AT91_PIOB,
205 .clock = &pioB_clk,
206 }, {
207 .id = AT91SAM9260_ID_PIOC,
208 .offset = AT91_PIOC,
209 .clock = &pioC_clk,
210 }
211};
212
213static void at91sam9260_reset(void)
214{
215#warning "Implement CPU reset"
216}
217
218
219/* --------------------------------------------------------------------
220 * AT91SAM9260 processor initialization
221 * -------------------------------------------------------------------- */
222
223void __init at91sam9260_initialize(unsigned long main_clock)
224{
225 /* Map peripherals */
226 iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
227
228 at91_arch_reset = at91sam9260_reset;
229 at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
230 | (1 << AT91SAM9260_ID_IRQ2);
231
232 /* Init clock subsystem */
233 at91_clock_init(main_clock);
234
235 /* Register the processor-specific clocks */
236 at91sam9260_register_clocks();
237
238 /* Register GPIO subsystem */
239 at91_gpio_init(at91sam9260_gpio, 3);
240}
241
242/* --------------------------------------------------------------------
243 * Interrupt initialization
244 * -------------------------------------------------------------------- */
245
246/*
247 * The default interrupt priority levels (0 = lowest, 7 = highest).
248 */
249static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = {
250 7, /* Advanced Interrupt Controller */
251 7, /* System Peripherals */
252 0, /* Parallel IO Controller A */
253 0, /* Parallel IO Controller B */
254 0, /* Parallel IO Controller C */
255 0, /* Analog-to-Digital Converter */
256 6, /* USART 0 */
257 6, /* USART 1 */
258 6, /* USART 2 */
259 0, /* Multimedia Card Interface */
260 4, /* USB Device Port */
261 0, /* Two-Wire Interface */
262 6, /* Serial Peripheral Interface 0 */
263 6, /* Serial Peripheral Interface 1 */
264 5, /* Serial Synchronous Controller */
265 0,
266 0,
267 0, /* Timer Counter 0 */
268 0, /* Timer Counter 1 */
269 0, /* Timer Counter 2 */
270 3, /* USB Host port */
271 3, /* Ethernet */
272 0, /* Image Sensor Interface */
273 6, /* USART 3 */
274 6, /* USART 4 */
275 6, /* USART 5 */
276 0, /* Timer Counter 3 */
277 0, /* Timer Counter 4 */
278 0, /* Timer Counter 5 */
279 0, /* Advanced Interrupt Controller */
280 0, /* Advanced Interrupt Controller */
281 0, /* Advanced Interrupt Controller */
282};
283
284void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])
285{
286 if (!priority)
287 priority = at91sam9260_default_irq_priority;
288
289 /* Initialize the AIC interrupt controller */
290 at91_aic_init(priority);
291
292 /* Enable GPIO interrupts */
293 at91_gpio_irq_setup();
294}
diff --git a/arch/arm/mach-at91rm9200/at91sam9261.c b/arch/arm/mach-at91rm9200/at91sam9261.c
new file mode 100644
index 000000000000..5a82f35da2e9
--- /dev/null
+++ b/arch/arm/mach-at91rm9200/at91sam9261.c
@@ -0,0 +1,289 @@
1/*
2 * arch/arm/mach-at91rm9200/at91sam9261.c
3 *
4 * Copyright (C) 2005 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12
13#include <linux/module.h>
14
15#include <asm/mach/arch.h>
16#include <asm/mach/map.h>
17#include <asm/arch/at91sam9261.h>
18#include <asm/arch/at91_pmc.h>
19
20#include "generic.h"
21#include "clock.h"
22
23static struct map_desc at91sam9261_io_desc[] __initdata = {
24 {
25 .virtual = AT91_VA_BASE_SYS,
26 .pfn = __phys_to_pfn(AT91_BASE_SYS),
27 .length = SZ_16K,
28 .type = MT_DEVICE,
29 }, {
30 .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
31 .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
32 .length = AT91SAM9261_SRAM_SIZE,
33 .type = MT_DEVICE,
34 },
35};
36
37/* --------------------------------------------------------------------
38 * Clocks
39 * -------------------------------------------------------------------- */
40
41/*
42 * The peripheral clocks.
43 */
44static struct clk pioA_clk = {
45 .name = "pioA_clk",
46 .pmc_mask = 1 << AT91SAM9261_ID_PIOA,
47 .type = CLK_TYPE_PERIPHERAL,
48};
49static struct clk pioB_clk = {
50 .name = "pioB_clk",
51 .pmc_mask = 1 << AT91SAM9261_ID_PIOB,
52 .type = CLK_TYPE_PERIPHERAL,
53};
54static struct clk pioC_clk = {
55 .name = "pioC_clk",
56 .pmc_mask = 1 << AT91SAM9261_ID_PIOC,
57 .type = CLK_TYPE_PERIPHERAL,
58};
59static struct clk usart0_clk = {
60 .name = "usart0_clk",
61 .pmc_mask = 1 << AT91SAM9261_ID_US0,
62 .type = CLK_TYPE_PERIPHERAL,
63};
64static struct clk usart1_clk = {
65 .name = "usart1_clk",
66 .pmc_mask = 1 << AT91SAM9261_ID_US1,
67 .type = CLK_TYPE_PERIPHERAL,
68};
69static struct clk usart2_clk = {
70 .name = "usart2_clk",
71 .pmc_mask = 1 << AT91SAM9261_ID_US2,
72 .type = CLK_TYPE_PERIPHERAL,
73};
74static struct clk mmc_clk = {
75 .name = "mci_clk",
76 .pmc_mask = 1 << AT91SAM9261_ID_MCI,
77 .type = CLK_TYPE_PERIPHERAL,
78};
79static struct clk udc_clk = {
80 .name = "udc_clk",
81 .pmc_mask = 1 << AT91SAM9261_ID_UDP,
82 .type = CLK_TYPE_PERIPHERAL,
83};
84static struct clk twi_clk = {
85 .name = "twi_clk",
86 .pmc_mask = 1 << AT91SAM9261_ID_TWI,
87 .type = CLK_TYPE_PERIPHERAL,
88};
89static struct clk spi0_clk = {
90 .name = "spi0_clk",
91 .pmc_mask = 1 << AT91SAM9261_ID_SPI0,
92 .type = CLK_TYPE_PERIPHERAL,
93};
94static struct clk spi1_clk = {
95 .name = "spi1_clk",
96 .pmc_mask = 1 << AT91SAM9261_ID_SPI1,
97 .type = CLK_TYPE_PERIPHERAL,
98};
99static struct clk ohci_clk = {
100 .name = "ohci_clk",
101 .pmc_mask = 1 << AT91SAM9261_ID_UHP,
102 .type = CLK_TYPE_PERIPHERAL,
103};
104static struct clk lcdc_clk = {
105 .name = "lcdc_clk",
106 .pmc_mask = 1 << AT91SAM9261_ID_LCDC,
107 .type = CLK_TYPE_PERIPHERAL,
108};
109
110static struct clk *periph_clocks[] __initdata = {
111 &pioA_clk,
112 &pioB_clk,
113 &pioC_clk,
114 &usart0_clk,
115 &usart1_clk,
116 &usart2_clk,
117 &mmc_clk,
118 &udc_clk,
119 &twi_clk,
120 &spi0_clk,
121 &spi1_clk,
122 // ssc 0 .. ssc2
123 // tc0 .. tc2
124 &ohci_clk,
125 &lcdc_clk,
126 // irq0 .. irq2
127};
128
129/*
130 * The four programmable clocks.
131 * You must configure pin multiplexing to bring these signals out.
132 */
133static struct clk pck0 = {
134 .name = "pck0",
135 .pmc_mask = AT91_PMC_PCK0,
136 .type = CLK_TYPE_PROGRAMMABLE,
137 .id = 0,
138};
139static struct clk pck1 = {
140 .name = "pck1",
141 .pmc_mask = AT91_PMC_PCK1,
142 .type = CLK_TYPE_PROGRAMMABLE,
143 .id = 1,
144};
145static struct clk pck2 = {
146 .name = "pck2",
147 .pmc_mask = AT91_PMC_PCK2,
148 .type = CLK_TYPE_PROGRAMMABLE,
149 .id = 2,
150};
151static struct clk pck3 = {
152 .name = "pck3",
153 .pmc_mask = AT91_PMC_PCK3,
154 .type = CLK_TYPE_PROGRAMMABLE,
155 .id = 3,
156};
157
158/* HClocks */
159static struct clk hck0 = {
160 .name = "hck0",
161 .pmc_mask = AT91_PMC_HCK0,
162 .type = CLK_TYPE_SYSTEM,
163 .id = 0,
164};
165static struct clk hck1 = {
166 .name = "hck1",
167 .pmc_mask = AT91_PMC_HCK1,
168 .type = CLK_TYPE_SYSTEM,
169 .id = 1,
170};
171
172static void __init at91sam9261_register_clocks(void)
173{
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
177 clk_register(periph_clocks[i]);
178
179 clk_register(&pck0);
180 clk_register(&pck1);
181 clk_register(&pck2);
182 clk_register(&pck3);
183
184 clk_register(&hck0);
185 clk_register(&hck1);
186}
187
188/* --------------------------------------------------------------------
189 * GPIO
190 * -------------------------------------------------------------------- */
191
192static struct at91_gpio_bank at91sam9261_gpio[] = {
193 {
194 .id = AT91SAM9261_ID_PIOA,
195 .offset = AT91_PIOA,
196 .clock = &pioA_clk,
197 }, {
198 .id = AT91SAM9261_ID_PIOB,
199 .offset = AT91_PIOB,
200 .clock = &pioB_clk,
201 }, {
202 .id = AT91SAM9261_ID_PIOC,
203 .offset = AT91_PIOC,
204 .clock = &pioC_clk,
205 }
206};
207
208static void at91sam9261_reset(void)
209{
210#warning "Implement CPU reset"
211}
212
213
214/* --------------------------------------------------------------------
215 * AT91SAM9261 processor initialization
216 * -------------------------------------------------------------------- */
217
218void __init at91sam9261_initialize(unsigned long main_clock)
219{
220 /* Map peripherals */
221 iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
222
223 at91_arch_reset = at91sam9261_reset;
224 at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
225 | (1 << AT91SAM9261_ID_IRQ2);
226
227 /* Init clock subsystem */
228 at91_clock_init(main_clock);
229
230 /* Register the processor-specific clocks */
231 at91sam9261_register_clocks();
232
233 /* Register GPIO subsystem */
234 at91_gpio_init(at91sam9261_gpio, 3);
235}
236
237/* --------------------------------------------------------------------
238 * Interrupt initialization
239 * -------------------------------------------------------------------- */
240
241/*
242 * The default interrupt priority levels (0 = lowest, 7 = highest).
243 */
244static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = {
245 7, /* Advanced Interrupt Controller */
246 7, /* System Peripherals */
247 0, /* Parallel IO Controller A */
248 0, /* Parallel IO Controller B */
249 0, /* Parallel IO Controller C */
250 0,
251 6, /* USART 0 */
252 6, /* USART 1 */
253 6, /* USART 2 */
254 0, /* Multimedia Card Interface */
255 4, /* USB Device Port */
256 0, /* Two-Wire Interface */
257 6, /* Serial Peripheral Interface 0 */
258 6, /* Serial Peripheral Interface 1 */
259 5, /* Serial Synchronous Controller 0 */
260 5, /* Serial Synchronous Controller 1 */
261 5, /* Serial Synchronous Controller 2 */
262 0, /* Timer Counter 0 */
263 0, /* Timer Counter 1 */
264 0, /* Timer Counter 2 */
265 3, /* USB Host port */
266 3, /* LCD Controller */
267 0,
268 0,
269 0,
270 0,
271 0,
272 0,
273 0,
274 0, /* Advanced Interrupt Controller */
275 0, /* Advanced Interrupt Controller */
276 0, /* Advanced Interrupt Controller */
277};
278
279void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])
280{
281 if (!priority)
282 priority = at91sam9261_default_irq_priority;
283
284 /* Initialize the AIC interrupt controller */
285 at91_aic_init(priority);
286
287 /* Enable GPIO interrupts */
288 at91_gpio_irq_setup();
289}
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
index fd98e353c5a2..8c4d5a77d485 100644
--- a/arch/arm/mach-at91rm9200/generic.h
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -10,14 +10,19 @@
10 10
11 /* Processors */ 11 /* Processors */
12extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks); 12extern void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banks);
13extern void __init at91sam9260_initialize(unsigned long main_clock);
14extern void __init at91sam9261_initialize(unsigned long main_clock);
13 15
14 /* Interrupts */ 16 /* Interrupts */
15extern void __init at91rm9200_init_interrupts(unsigned int priority[]); 17extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
18extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
19extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
16extern void __init at91_aic_init(unsigned int priority[]); 20extern void __init at91_aic_init(unsigned int priority[]);
17 21
18 /* Timer */ 22 /* Timer */
19struct sys_timer; 23struct sys_timer;
20extern struct sys_timer at91rm9200_timer; 24extern struct sys_timer at91rm9200_timer;
25extern struct sys_timer at91sam926x_timer;
21 26
22 /* Clocks */ 27 /* Clocks */
23extern int __init at91_clock_init(unsigned long main_clock); 28extern int __init at91_clock_init(unsigned long main_clock);
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9260.h b/include/asm-arm/arch-at91rm9200/at91sam9260.h
new file mode 100644
index 000000000000..46f4dd65c035
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9260.h
@@ -0,0 +1,125 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam9260.h
3 *
4 * (C) 2006 Andrew Victor
5 *
6 * Common definitions.
7 * Based on AT91SAM9260 datasheet revision A (Preliminary).
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9260_H
16#define AT91SAM9260_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
26#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
27#define AT91SAM9260_ID_US0 6 /* USART 0 */
28#define AT91SAM9260_ID_US1 7 /* USART 1 */
29#define AT91SAM9260_ID_US2 8 /* USART 2 */
30#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
31#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
32#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
33#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
34#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
35#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
36#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
37#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
38#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
39#define AT91SAM9260_ID_UHP 20 /* USB Host port */
40#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
41#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
42#define AT91SAM9260_ID_US3 23 /* USART 3 */
43#define AT91SAM9260_ID_US4 24 /* USART 4 */
44#define AT91SAM9260_ID_US5 25 /* USART 5 */
45#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
46#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
47#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
48#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
49#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
50#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
51
52
53/*
54 * User Peripheral physical base addresses.
55 */
56#define AT91SAM9260_BASE_TCB0 0xfffa0000
57#define AT91SAM9260_BASE_TC0 0xfffa0000
58#define AT91SAM9260_BASE_TC1 0xfffa0040
59#define AT91SAM9260_BASE_TC2 0xfffa0080
60#define AT91SAM9260_BASE_UDP 0xfffa4000
61#define AT91SAM9260_BASE_MCI 0xfffa8000
62#define AT91SAM9260_BASE_TWI 0xfffac000
63#define AT91SAM9260_BASE_US0 0xfffb0000
64#define AT91SAM9260_BASE_US1 0xfffb4000
65#define AT91SAM9260_BASE_US2 0xfffb8000
66#define AT91SAM9260_BASE_SSC 0xfffbc000
67#define AT91SAM9260_BASE_ISI 0xfffc0000
68#define AT91SAM9260_BASE_EMAC 0xfffc4000
69#define AT91SAM9260_BASE_SPI0 0xfffc8000
70#define AT91SAM9260_BASE_SPI1 0xfffcc000
71#define AT91SAM9260_BASE_US3 0xfffd0000
72#define AT91SAM9260_BASE_US4 0xfffd4000
73#define AT91SAM9260_BASE_US5 0xfffd8000
74#define AT91SAM9260_BASE_TCB1 0xfffdc000
75#define AT91SAM9260_BASE_TC3 0xfffdc000
76#define AT91SAM9260_BASE_TC4 0xfffdc040
77#define AT91SAM9260_BASE_TC5 0xfffdc080
78#define AT91SAM9260_BASE_ADC 0xfffe0000
79#define AT91_BASE_SYS 0xffffe800
80
81/*
82 * System Peripherals (offset from AT91_BASE_SYS)
83 */
84#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
85#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
86#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
87#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
88#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
89#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
90#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
91#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
92#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
93#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
94#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
95#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
96#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
97#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
98#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
99#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
100#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
101
102
103/*
104 * Internal Memory.
105 */
106#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
107#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
108
109#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
110#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
111#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
112#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
113
114#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
115
116#if 0
117/*
118 * PIO pin definitions (peripheral A/B multiplexing).
119 */
120
121// TODO: Add
122
123#endif
124
125#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91sam9261.h b/include/asm-arm/arch-at91rm9200/at91sam9261.h
new file mode 100644
index 000000000000..8d39672d5b82
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91sam9261.h
@@ -0,0 +1,292 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam9261.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Common definitions.
7 * Based on AT91SAM9261 datasheet revision E. (Preliminary)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91SAM9261_H
16#define AT91SAM9261_H
17
18/*
19 * Peripheral identifiers/interrupts.
20 */
21#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
22#define AT91_ID_SYS 1 /* System Peripherals */
23#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
24#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
25#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
26#define AT91SAM9261_ID_US0 6 /* USART 0 */
27#define AT91SAM9261_ID_US1 7 /* USART 1 */
28#define AT91SAM9261_ID_US2 8 /* USART 2 */
29#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
30#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
31#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
32#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
33#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
34#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
35#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
36#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
37#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
38#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
39#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
40#define AT91SAM9261_ID_UHP 20 /* USB Host port */
41#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
42#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
43#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
44#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
45
46
47/*
48 * User Peripheral physical base addresses.
49 */
50#define AT91SAM9261_BASE_TCB0 0xfffa0000
51#define AT91SAM9261_BASE_TC0 0xfffa0000
52#define AT91SAM9261_BASE_TC1 0xfffa0040
53#define AT91SAM9261_BASE_TC2 0xfffa0080
54#define AT91SAM9261_BASE_UDP 0xfffa4000
55#define AT91SAM9261_BASE_MCI 0xfffa8000
56#define AT91SAM9261_BASE_TWI 0xfffac000
57#define AT91SAM9261_BASE_US0 0xfffb0000
58#define AT91SAM9261_BASE_US1 0xfffb4000
59#define AT91SAM9261_BASE_US2 0xfffb8000
60#define AT91SAM9261_BASE_SSC0 0xfffbc000
61#define AT91SAM9261_BASE_SSC1 0xfffc0000
62#define AT91SAM9261_BASE_SSC2 0xfffc4000
63#define AT91SAM9261_BASE_SPI0 0xfffc8000
64#define AT91SAM9261_BASE_SPI1 0xfffcc000
65#define AT91_BASE_SYS 0xffffea00
66
67
68/*
69 * System Peripherals (offset from AT91_BASE_SYS)
70 */
71#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
72#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
73#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
74#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
75#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
76#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
77#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
78#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
79#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
80#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
81#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
82#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
83#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
84#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
85#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
86
87
88/*
89 * Internal Memory.
90 */
91#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
92#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
93
94#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
95#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
96
97#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
98#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
99
100
101#if 0
102/*
103 * PIO pin definitions (peripheral A/B multiplexing).
104 */
105#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */
106#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */
107#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */
108#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */
109#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */
110#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */
111#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */
112#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */
113#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */
114#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */
115#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */
116#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */
117#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */
118#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */
119#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */
120#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */
121#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */
122#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */
123#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */
124#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */
125#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */
126#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */
127#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */
128#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */
129#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */
130#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */
131#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */
132#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */
133#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */
134#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */
135#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */
136#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */
137#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */
138#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */
139#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */
140#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */
141#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */
142#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */
143#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */
144#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */
145#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */
146#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */
147#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */
148#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */
149#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */
150#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */
151#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */
152#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */
153#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */
154#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */
155#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */
156#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */
157#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */
158#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */
159#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */
160#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */
161#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */
162#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */
163#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */
164#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */
165#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */
166#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */
167#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */
168
169#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */
170#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */
171#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */
172#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */
173#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */
174#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */
175#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */
176#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */
177#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */
178#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */
179#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */
180#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */
181#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */
182#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */
183#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */
184#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */
185#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */
186#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */
187#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */
188#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */
189#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */
190#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */
191#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */
192#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */
193#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */
194#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */
195#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */
196#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */
197#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */
198#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */
199#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */
200#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */
201#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */
202#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */
203#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */
204#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */
205#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */
206#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */
207#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */
208#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */
209#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */
210#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */
211#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */
212#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */
213#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */
214#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */
215#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */
216#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */
217#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */
218#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */
219#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */
220#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */
221#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */
222#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */
223#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */
224#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */
225#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */
226#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */
227#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */
228#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */
229#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */
230
231#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */
232#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */
233#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */
234#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */
235#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */
236#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */
237#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */
238#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */
239#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */
240#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */
241#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */
242#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */
243#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */
244#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */
245#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */
246#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */
247#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */
248#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */
249#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */
250#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */
251#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */
252#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */
253#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */
254#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */
255#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */
256#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */
257#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */
258#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */
259#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */
260#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */
261#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */
262#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */
263#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */
264#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */
265#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
266#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */
267#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
268#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */
269#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
270#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */
271#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
272#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */
273#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
274#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */
275#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
276#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */
277#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */
278#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */
279#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */
280#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */
281#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */
282#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */
283#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */
284#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */
285#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */
286#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */
287#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */
288#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */
289#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */
290#endif
291
292#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-14 16:19:02 -0400