aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/gma500/psb_drm.h159
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.c507
-rw-r--r--drivers/gpu/drm/gma500/psb_drv.h2
3 files changed, 24 insertions, 644 deletions
diff --git a/drivers/gpu/drm/gma500/psb_drm.h b/drivers/gpu/drm/gma500/psb_drm.h
index dca7b20568f9..72eeb7a9d4be 100644
--- a/drivers/gpu/drm/gma500/psb_drm.h
+++ b/drivers/gpu/drm/gma500/psb_drm.h
@@ -24,168 +24,41 @@
24 24
25#define PSB_NUM_PIPE 3 25#define PSB_NUM_PIPE 3
26 26
27#define PSB_GPU_ACCESS_READ (1ULL << 32)
28#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
29#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
30
31#define PSB_BO_FLAG_COMMAND (1ULL << 52)
32 27
33/* 28/*
34 * Feedback components: 29 * Manage the LUT for an output
35 */ 30 */
36
37struct drm_psb_sizes_arg {
38 u32 ta_mem_size;
39 u32 mmu_size;
40 u32 pds_size;
41 u32 rastgeom_size;
42 u32 tt_size;
43 u32 vram_size;
44};
45
46struct drm_psb_dpst_lut_arg { 31struct drm_psb_dpst_lut_arg {
47 uint8_t lut[256]; 32 uint8_t lut[256];
48 int output_id; 33 int output_id;
49}; 34};
50 35
51#define PSB_DC_CRTC_SAVE 0x01 36/*
52#define PSB_DC_CRTC_RESTORE 0x02 37 * Validate modes
53#define PSB_DC_OUTPUT_SAVE 0x04 38 */
54#define PSB_DC_OUTPUT_RESTORE 0x08
55#define PSB_DC_CRTC_MASK 0x03
56#define PSB_DC_OUTPUT_MASK 0x0C
57
58struct drm_psb_dc_state_arg {
59 u32 flags;
60 u32 obj_id;
61};
62
63struct drm_psb_mode_operation_arg { 39struct drm_psb_mode_operation_arg {
64 u32 obj_id; 40 u32 obj_id;
65 u16 operation; 41 u16 operation;
66 struct drm_mode_modeinfo mode; 42 struct drm_mode_modeinfo mode;
67 void *data; 43 u64 data;
68}; 44};
69 45
46/*
47 * Query the stolen memory for smarter management of
48 * memory by the server
49 */
70struct drm_psb_stolen_memory_arg { 50struct drm_psb_stolen_memory_arg {
71 u32 base; 51 u32 base;
72 u32 size; 52 u32 size;
73}; 53};
74 54
75/*Display Register Bits*/
76#define REGRWBITS_PFIT_CONTROLS (1 << 0)
77#define REGRWBITS_PFIT_AUTOSCALE_RATIOS (1 << 1)
78#define REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS (1 << 2)
79#define REGRWBITS_PIPEASRC (1 << 3)
80#define REGRWBITS_PIPEBSRC (1 << 4)
81#define REGRWBITS_VTOTAL_A (1 << 5)
82#define REGRWBITS_VTOTAL_B (1 << 6)
83#define REGRWBITS_DSPACNTR (1 << 8)
84#define REGRWBITS_DSPBCNTR (1 << 9)
85#define REGRWBITS_DSPCCNTR (1 << 10)
86
87/*Overlay Register Bits*/
88#define OV_REGRWBITS_OVADD (1 << 0)
89#define OV_REGRWBITS_OGAM_ALL (1 << 1)
90
91#define OVC_REGRWBITS_OVADD (1 << 2)
92#define OVC_REGRWBITS_OGAM_ALL (1 << 3)
93
94struct drm_psb_register_rw_arg {
95 u32 b_force_hw_on;
96
97 u32 display_read_mask;
98 u32 display_write_mask;
99
100 struct {
101 u32 pfit_controls;
102 u32 pfit_autoscale_ratios;
103 u32 pfit_programmed_scale_ratios;
104 u32 pipeasrc;
105 u32 pipebsrc;
106 u32 vtotal_a;
107 u32 vtotal_b;
108 } display;
109
110 u32 overlay_read_mask;
111 u32 overlay_write_mask;
112
113 struct {
114 u32 OVADD;
115 u32 OGAMC0;
116 u32 OGAMC1;
117 u32 OGAMC2;
118 u32 OGAMC3;
119 u32 OGAMC4;
120 u32 OGAMC5;
121 u32 IEP_ENABLED;
122 u32 IEP_BLE_MINMAX;
123 u32 IEP_BSSCC_CONTROL;
124 u32 b_wait_vblank;
125 } overlay;
126
127 u32 sprite_enable_mask;
128 u32 sprite_disable_mask;
129
130 struct {
131 u32 dspa_control;
132 u32 dspa_key_value;
133 u32 dspa_key_mask;
134 u32 dspc_control;
135 u32 dspc_stride;
136 u32 dspc_position;
137 u32 dspc_linear_offset;
138 u32 dspc_size;
139 u32 dspc_surface;
140 } sprite;
141
142 u32 subpicture_enable_mask;
143 u32 subpicture_disable_mask;
144};
145
146/* Controlling the kernel modesetting buffers */
147
148#define DRM_PSB_SIZES 0x07
149#define DRM_PSB_FUSE_REG 0x08
150#define DRM_PSB_DC_STATE 0x0A
151#define DRM_PSB_ADB 0x0B
152#define DRM_PSB_MODE_OPERATION 0x0C
153#define DRM_PSB_STOLEN_MEMORY 0x0D
154#define DRM_PSB_REGISTER_RW 0x0E
155
156/*
157 * NOTE: Add new commands here, but increment
158 * the values below and increment their
159 * corresponding defines where they're
160 * defined elsewhere.
161 */
162
163#define DRM_PSB_GEM_CREATE 0x10
164#define DRM_PSB_2D_OP 0x11 /* Will be merged later */
165#define DRM_PSB_GEM_MMAP 0x12
166#define DRM_PSB_DPST 0x1B
167#define DRM_PSB_GAMMA 0x1C
168#define DRM_PSB_DPST_BL 0x1D
169#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1F
170
171#define PSB_MODE_OPERATION_MODE_VALID 0x01
172#define PSB_MODE_OPERATION_SET_DC_BASE 0x02
173
174struct drm_psb_get_pipe_from_crtc_id_arg { 55struct drm_psb_get_pipe_from_crtc_id_arg {
175 /** ID of CRTC being requested **/ 56 /** ID of CRTC being requested **/
176 u32 crtc_id; 57 u32 crtc_id;
177
178 /** pipe of requested CRTC **/ 58 /** pipe of requested CRTC **/
179 u32 pipe; 59 u32 pipe;
180}; 60};
181 61
182/* FIXME: move this into a medfield header once we are sure it isn't needed for an
183 ioctl */
184struct psb_drm_dpu_rect {
185 int x, y;
186 int width, height;
187};
188
189struct drm_psb_gem_create { 62struct drm_psb_gem_create {
190 __u64 size; 63 __u64 size;
191 __u32 handle; 64 __u32 handle;
@@ -204,4 +77,18 @@ struct drm_psb_gem_mmap {
204 __u64 offset; 77 __u64 offset;
205}; 78};
206 79
80/* Controlling the kernel modesetting buffers */
81
82#define DRM_PSB_GEM_CREATE 0x00 /* Create a GEM object */
83#define DRM_PSB_GEM_MMAP 0x01 /* Map GEM memory */
84#define DRM_PSB_STOLEN_MEMORY 0x02 /* Report stolen memory */
85#define DRM_PSB_2D_OP 0x03 /* Will be merged later */
86#define DRM_PSB_GAMMA 0x04 /* Set gamma table */
87#define DRM_PSB_ADB 0x05 /* Get backlight */
88#define DRM_PSB_DPST_BL 0x06 /* Set backlight */
89#define DRM_PSB_GET_PIPE_FROM_CRTC_ID 0x1 /* CRTC to physical pipe# */
90#define DRM_PSB_MODE_OPERATION 0x07 /* Mode validation/DC set */
91#define PSB_MODE_OPERATION_MODE_VALID 0x01
92
93
207#endif 94#endif
diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c
index 97b5b11fb10d..c65a8725b154 100644
--- a/drivers/gpu/drm/gma500/psb_drv.c
+++ b/drivers/gpu/drm/gma500/psb_drv.c
@@ -80,14 +80,6 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
80 * Standard IOCTLs. 80 * Standard IOCTLs.
81 */ 81 */
82 82
83#define DRM_IOCTL_PSB_SIZES \
84 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
85 struct drm_psb_sizes_arg)
86#define DRM_IOCTL_PSB_FUSE_REG \
87 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
88#define DRM_IOCTL_PSB_DC_STATE \
89 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
90 struct drm_psb_dc_state_arg)
91#define DRM_IOCTL_PSB_ADB \ 83#define DRM_IOCTL_PSB_ADB \
92 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t) 84 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
93#define DRM_IOCTL_PSB_MODE_OPERATION \ 85#define DRM_IOCTL_PSB_MODE_OPERATION \
@@ -96,12 +88,6 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
96#define DRM_IOCTL_PSB_STOLEN_MEMORY \ 88#define DRM_IOCTL_PSB_STOLEN_MEMORY \
97 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \ 89 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
98 struct drm_psb_stolen_memory_arg) 90 struct drm_psb_stolen_memory_arg)
99#define DRM_IOCTL_PSB_REGISTER_RW \
100 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
101 struct drm_psb_register_rw_arg)
102#define DRM_IOCTL_PSB_DPST \
103 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
104 uint32_t)
105#define DRM_IOCTL_PSB_GAMMA \ 91#define DRM_IOCTL_PSB_GAMMA \
106 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \ 92 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
107 struct drm_psb_dpst_lut_arg) 93 struct drm_psb_dpst_lut_arg)
@@ -118,20 +104,12 @@ MODULE_DEVICE_TABLE(pci, pciidlist);
118 DRM_IOWR(DRM_PSB_GEM_MMAP + DRM_COMMAND_BASE, \ 104 DRM_IOWR(DRM_PSB_GEM_MMAP + DRM_COMMAND_BASE, \
119 struct drm_psb_gem_mmap) 105 struct drm_psb_gem_mmap)
120 106
121static int psb_sizes_ioctl(struct drm_device *dev, void *data,
122 struct drm_file *file_priv);
123static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
124 struct drm_file *file_priv);
125static int psb_adb_ioctl(struct drm_device *dev, void *data, 107static int psb_adb_ioctl(struct drm_device *dev, void *data,
126 struct drm_file *file_priv); 108 struct drm_file *file_priv);
127static int psb_mode_operation_ioctl(struct drm_device *dev, void *data, 109static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
128 struct drm_file *file_priv); 110 struct drm_file *file_priv);
129static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data, 111static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
130 struct drm_file *file_priv); 112 struct drm_file *file_priv);
131static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
132 struct drm_file *file_priv);
133static int psb_dpst_ioctl(struct drm_device *dev, void *data,
134 struct drm_file *file_priv);
135static int psb_gamma_ioctl(struct drm_device *dev, void *data, 113static int psb_gamma_ioctl(struct drm_device *dev, void *data,
136 struct drm_file *file_priv); 114 struct drm_file *file_priv);
137static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data, 115static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
@@ -141,16 +119,11 @@ static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
141 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func} 119 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
142 120
143static struct drm_ioctl_desc psb_ioctls[] = { 121static struct drm_ioctl_desc psb_ioctls[] = {
144 PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
145 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
146 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH), 122 PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
147 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl, 123 PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
148 DRM_AUTH), 124 DRM_AUTH),
149 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl, 125 PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
150 DRM_AUTH), 126 DRM_AUTH),
151 PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
152 DRM_AUTH),
153 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
154 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH), 127 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
155 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH), 128 PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
156 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID, 129 PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
@@ -442,75 +415,6 @@ int psb_driver_device_is_agp(struct drm_device *dev)
442 return 0; 415 return 0;
443} 416}
444 417
445
446static int psb_sizes_ioctl(struct drm_device *dev, void *data,
447 struct drm_file *file_priv)
448{
449 struct drm_psb_private *dev_priv = psb_priv(dev);
450 struct drm_psb_sizes_arg *arg =
451 (struct drm_psb_sizes_arg *) data;
452
453 *arg = dev_priv->sizes;
454 return 0;
455}
456
457static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
458 struct drm_file *file_priv)
459{
460 uint32_t flags;
461 uint32_t obj_id;
462 struct drm_mode_object *obj;
463 struct drm_connector *connector;
464 struct drm_crtc *crtc;
465 struct drm_psb_dc_state_arg *arg = data;
466
467
468 /* Double check MRST case */
469 if (IS_MRST(dev) || IS_MFLD(dev))
470 return -EOPNOTSUPP;
471
472 flags = arg->flags;
473 obj_id = arg->obj_id;
474
475 if (flags & PSB_DC_CRTC_MASK) {
476 obj = drm_mode_object_find(dev, obj_id,
477 DRM_MODE_OBJECT_CRTC);
478 if (!obj) {
479 dev_dbg(dev->dev, "Invalid CRTC object.\n");
480 return -EINVAL;
481 }
482
483 crtc = obj_to_crtc(obj);
484
485 mutex_lock(&dev->mode_config.mutex);
486 if (drm_helper_crtc_in_use(crtc)) {
487 if (flags & PSB_DC_CRTC_SAVE)
488 crtc->funcs->save(crtc);
489 else
490 crtc->funcs->restore(crtc);
491 }
492 mutex_unlock(&dev->mode_config.mutex);
493
494 return 0;
495 } else if (flags & PSB_DC_OUTPUT_MASK) {
496 obj = drm_mode_object_find(dev, obj_id,
497 DRM_MODE_OBJECT_CONNECTOR);
498 if (!obj) {
499 dev_dbg(dev->dev, "Invalid connector id.\n");
500 return -EINVAL;
501 }
502
503 connector = obj_to_connector(obj);
504 if (flags & PSB_DC_OUTPUT_SAVE)
505 connector->funcs->save(connector);
506 else
507 connector->funcs->restore(connector);
508
509 return 0;
510 }
511 return -EINVAL;
512}
513
514static inline void get_brightness(struct backlight_device *bd) 418static inline void get_brightness(struct backlight_device *bd)
515{ 419{
516#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE 420#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
@@ -543,36 +447,6 @@ static int psb_adb_ioctl(struct drm_device *dev, void *data,
543 return 0; 447 return 0;
544} 448}
545 449
546/* return the current mode to the dpst module */
547static int psb_dpst_ioctl(struct drm_device *dev, void *data,
548 struct drm_file *file_priv)
549{
550 struct drm_psb_private *dev_priv = psb_priv(dev);
551 uint32_t *arg = data;
552 uint32_t x;
553 uint32_t y;
554 uint32_t reg;
555
556 if (!gma_power_begin(dev, 0))
557 return -EIO;
558
559 reg = PSB_RVDC32(PIPEASRC);
560
561 gma_power_end(dev);
562
563 /* horizontal is the left 16 bits */
564 x = reg >> 16;
565 /* vertical is the right 16 bits */
566 y = reg & 0x0000ffff;
567
568 /* the values are the image size minus one */
569 x++;
570 y++;
571
572 *arg = (x << 16) | y;
573
574 return 0;
575}
576static int psb_gamma_ioctl(struct drm_device *dev, void *data, 450static int psb_gamma_ioctl(struct drm_device *dev, void *data,
577 struct drm_file *file_priv) 451 struct drm_file *file_priv)
578{ 452{
@@ -613,37 +487,15 @@ static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
613 struct drm_psb_mode_operation_arg *arg; 487 struct drm_psb_mode_operation_arg *arg;
614 struct drm_mode_object *obj; 488 struct drm_mode_object *obj;
615 struct drm_connector *connector; 489 struct drm_connector *connector;
616 struct drm_framebuffer *drm_fb;
617 struct psb_framebuffer *psb_fb;
618 struct drm_connector_helper_funcs *connector_funcs; 490 struct drm_connector_helper_funcs *connector_funcs;
619 int ret = 0; 491 int ret = 0;
620 int resp = MODE_OK; 492 int resp = MODE_OK;
621 struct drm_psb_private *dev_priv = psb_priv(dev);
622 493
623 arg = (struct drm_psb_mode_operation_arg *)data; 494 arg = (struct drm_psb_mode_operation_arg *)data;
624 obj_id = arg->obj_id; 495 obj_id = arg->obj_id;
625 op = arg->operation; 496 op = arg->operation;
626 497
627 switch (op) { 498 switch (op) {
628 case PSB_MODE_OPERATION_SET_DC_BASE:
629 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
630 if (!obj) {
631 dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
632 return -EINVAL;
633 }
634
635 drm_fb = obj_to_fb(obj);
636 psb_fb = to_psb_fb(drm_fb);
637
638 if (gma_power_begin(dev, 0)) {
639 REG_WRITE(DSPASURF, psb_fb->gtt->offset);
640 REG_READ(DSPASURF);
641 gma_power_end(dev);
642 } else {
643 dev_priv->saveDSPASURF = psb_fb->gtt->offset;
644 }
645
646 return 0;
647 case PSB_MODE_OPERATION_MODE_VALID: 499 case PSB_MODE_OPERATION_MODE_VALID:
648 umode = &arg->mode; 500 umode = &arg->mode;
649 501
@@ -689,7 +541,7 @@ static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
689 541
690 if (connector_funcs->mode_valid) { 542 if (connector_funcs->mode_valid) {
691 resp = connector_funcs->mode_valid(connector, mode); 543 resp = connector_funcs->mode_valid(connector, mode);
692 arg->data = (void *)resp; 544 arg->data = resp;
693 } 545 }
694 546
695 /*do some clean up work*/ 547 /*do some clean up work*/
@@ -719,363 +571,6 @@ static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
719 return 0; 571 return 0;
720} 572}
721 573
722/* FIXME: needs Medfield changes */
723static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
724 struct drm_file *file_priv)
725{
726 struct drm_psb_private *dev_priv = psb_priv(dev);
727 struct drm_psb_register_rw_arg *arg = data;
728 bool usage = arg->b_force_hw_on ? true : false;
729
730 if (arg->display_write_mask != 0) {
731 if (gma_power_begin(dev, usage)) {
732 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
733 PSB_WVDC32(arg->display.pfit_controls,
734 PFIT_CONTROL);
735 if (arg->display_write_mask &
736 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
737 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
738 PFIT_AUTO_RATIOS);
739 if (arg->display_write_mask &
740 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
741 PSB_WVDC32(
742 arg->display.pfit_programmed_scale_ratios,
743 PFIT_PGM_RATIOS);
744 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
745 PSB_WVDC32(arg->display.pipeasrc,
746 PIPEASRC);
747 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
748 PSB_WVDC32(arg->display.pipebsrc,
749 PIPEBSRC);
750 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
751 PSB_WVDC32(arg->display.vtotal_a,
752 VTOTAL_A);
753 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
754 PSB_WVDC32(arg->display.vtotal_b,
755 VTOTAL_B);
756 gma_power_end(dev);
757 } else {
758 if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
759 dev_priv->savePFIT_CONTROL =
760 arg->display.pfit_controls;
761 if (arg->display_write_mask &
762 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
763 dev_priv->savePFIT_AUTO_RATIOS =
764 arg->display.pfit_autoscale_ratios;
765 if (arg->display_write_mask &
766 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
767 dev_priv->savePFIT_PGM_RATIOS =
768 arg->display.pfit_programmed_scale_ratios;
769 if (arg->display_write_mask & REGRWBITS_PIPEASRC)
770 dev_priv->savePIPEASRC = arg->display.pipeasrc;
771 if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
772 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
773 if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
774 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
775 if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
776 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
777 }
778 }
779
780 if (arg->display_read_mask != 0) {
781 if (gma_power_begin(dev, usage)) {
782 if (arg->display_read_mask &
783 REGRWBITS_PFIT_CONTROLS)
784 arg->display.pfit_controls =
785 PSB_RVDC32(PFIT_CONTROL);
786 if (arg->display_read_mask &
787 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
788 arg->display.pfit_autoscale_ratios =
789 PSB_RVDC32(PFIT_AUTO_RATIOS);
790 if (arg->display_read_mask &
791 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
792 arg->display.pfit_programmed_scale_ratios =
793 PSB_RVDC32(PFIT_PGM_RATIOS);
794 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
795 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
796 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
797 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
798 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
799 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
800 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
801 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
802 gma_power_end(dev);
803 } else {
804 if (arg->display_read_mask &
805 REGRWBITS_PFIT_CONTROLS)
806 arg->display.pfit_controls =
807 dev_priv->savePFIT_CONTROL;
808 if (arg->display_read_mask &
809 REGRWBITS_PFIT_AUTOSCALE_RATIOS)
810 arg->display.pfit_autoscale_ratios =
811 dev_priv->savePFIT_AUTO_RATIOS;
812 if (arg->display_read_mask &
813 REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
814 arg->display.pfit_programmed_scale_ratios =
815 dev_priv->savePFIT_PGM_RATIOS;
816 if (arg->display_read_mask & REGRWBITS_PIPEASRC)
817 arg->display.pipeasrc = dev_priv->savePIPEASRC;
818 if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
819 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
820 if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
821 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
822 if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
823 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
824 }
825 }
826
827 if (arg->overlay_write_mask != 0) {
828 if (gma_power_begin(dev, usage)) {
829 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
830 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
831 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
832 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
833 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
834 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
835 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
836 }
837 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
838 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
839 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
840 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
841 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
842 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
843 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
844 }
845
846 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
847 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
848
849 if (arg->overlay.b_wait_vblank) {
850 /* Wait for 20ms.*/
851 unsigned long vblank_timeout = jiffies
852 + HZ/50;
853 uint32_t temp;
854 while (time_before_eq(jiffies,
855 vblank_timeout)) {
856 temp = PSB_RVDC32(OV_DOVASTA);
857 if ((temp & (0x1 << 31)) != 0)
858 break;
859 cpu_relax();
860 }
861 }
862 }
863 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
864 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
865 if (arg->overlay.b_wait_vblank) {
866 /* Wait for 20ms.*/
867 unsigned long vblank_timeout =
868 jiffies + HZ/50;
869 uint32_t temp;
870 while (time_before_eq(jiffies,
871 vblank_timeout)) {
872 temp = PSB_RVDC32(OVC_DOVCSTA);
873 if ((temp & (0x1 << 31)) != 0)
874 break;
875 cpu_relax();
876 }
877 }
878 }
879 gma_power_end(dev);
880 } else {
881 if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
882 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
883 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
884 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
885 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
886 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
887 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
888 }
889 if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
890 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
891 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
892 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
893 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
894 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
895 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
896 }
897 if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
898 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
899 if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
900 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
901 }
902 }
903
904 if (arg->overlay_read_mask != 0) {
905 if (gma_power_begin(dev, usage)) {
906 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
907 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
908 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
909 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
910 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
911 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
912 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
913 }
914 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
915 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
916 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
917 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
918 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
919 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
920 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
921 }
922 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
923 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
924 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
925 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
926 gma_power_end(dev);
927 } else {
928 if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
929 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
930 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
931 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
932 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
933 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
934 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
935 }
936 if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
937 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
938 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
939 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
940 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
941 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
942 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
943 }
944 if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
945 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
946 if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
947 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
948 }
949 }
950
951 if (arg->sprite_enable_mask != 0) {
952 if (gma_power_begin(dev, usage)) {
953 PSB_WVDC32(0x1F3E, DSPARB);
954 PSB_WVDC32(arg->sprite.dspa_control
955 | PSB_RVDC32(DSPACNTR), DSPACNTR);
956 PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
957 PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
958 PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
959 PSB_RVDC32(DSPASURF);
960 PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
961 PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
962 PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
963 PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
964 PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
965 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
966 PSB_RVDC32(DSPCSURF);
967 gma_power_end(dev);
968 }
969 }
970
971 if (arg->sprite_disable_mask != 0) {
972 if (gma_power_begin(dev, usage)) {
973 PSB_WVDC32(0x3F3E, DSPARB);
974 PSB_WVDC32(0x0, DSPCCNTR);
975 PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
976 PSB_RVDC32(DSPCSURF);
977 gma_power_end(dev);
978 }
979 }
980
981 if (arg->subpicture_enable_mask != 0) {
982 if (gma_power_begin(dev, usage)) {
983 uint32_t temp;
984 if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
985 temp = PSB_RVDC32(DSPACNTR);
986 temp &= ~DISPPLANE_PIXFORMAT_MASK;
987 temp &= ~DISPPLANE_BOTTOM;
988 temp |= DISPPLANE_32BPP;
989 PSB_WVDC32(temp, DSPACNTR);
990
991 temp = PSB_RVDC32(DSPABASE);
992 PSB_WVDC32(temp, DSPABASE);
993 PSB_RVDC32(DSPABASE);
994 temp = PSB_RVDC32(DSPASURF);
995 PSB_WVDC32(temp, DSPASURF);
996 PSB_RVDC32(DSPASURF);
997 }
998 if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
999 temp = PSB_RVDC32(DSPBCNTR);
1000 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1001 temp &= ~DISPPLANE_BOTTOM;
1002 temp |= DISPPLANE_32BPP;
1003 PSB_WVDC32(temp, DSPBCNTR);
1004
1005 temp = PSB_RVDC32(DSPBBASE);
1006 PSB_WVDC32(temp, DSPBBASE);
1007 PSB_RVDC32(DSPBBASE);
1008 temp = PSB_RVDC32(DSPBSURF);
1009 PSB_WVDC32(temp, DSPBSURF);
1010 PSB_RVDC32(DSPBSURF);
1011 }
1012 if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1013 temp = PSB_RVDC32(DSPCCNTR);
1014 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1015 temp &= ~DISPPLANE_BOTTOM;
1016 temp |= DISPPLANE_32BPP;
1017 PSB_WVDC32(temp, DSPCCNTR);
1018
1019 temp = PSB_RVDC32(DSPCBASE);
1020 PSB_WVDC32(temp, DSPCBASE);
1021 PSB_RVDC32(DSPCBASE);
1022 temp = PSB_RVDC32(DSPCSURF);
1023 PSB_WVDC32(temp, DSPCSURF);
1024 PSB_RVDC32(DSPCSURF);
1025 }
1026 gma_power_end(dev);
1027 }
1028 }
1029
1030 if (arg->subpicture_disable_mask != 0) {
1031 if (gma_power_begin(dev, usage)) {
1032 uint32_t temp;
1033 if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1034 temp = PSB_RVDC32(DSPACNTR);
1035 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1036 temp |= DISPPLANE_32BPP_NO_ALPHA;
1037 PSB_WVDC32(temp, DSPACNTR);
1038
1039 temp = PSB_RVDC32(DSPABASE);
1040 PSB_WVDC32(temp, DSPABASE);
1041 PSB_RVDC32(DSPABASE);
1042 temp = PSB_RVDC32(DSPASURF);
1043 PSB_WVDC32(temp, DSPASURF);
1044 PSB_RVDC32(DSPASURF);
1045 }
1046 if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1047 temp = PSB_RVDC32(DSPBCNTR);
1048 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1049 temp |= DISPPLANE_32BPP_NO_ALPHA;
1050 PSB_WVDC32(temp, DSPBCNTR);
1051
1052 temp = PSB_RVDC32(DSPBBASE);
1053 PSB_WVDC32(temp, DSPBBASE);
1054 PSB_RVDC32(DSPBBASE);
1055 temp = PSB_RVDC32(DSPBSURF);
1056 PSB_WVDC32(temp, DSPBSURF);
1057 PSB_RVDC32(DSPBSURF);
1058 }
1059 if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1060 temp = PSB_RVDC32(DSPCCNTR);
1061 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1062 temp |= DISPPLANE_32BPP_NO_ALPHA;
1063 PSB_WVDC32(temp, DSPCCNTR);
1064
1065 temp = PSB_RVDC32(DSPCBASE);
1066 PSB_WVDC32(temp, DSPCBASE);
1067 PSB_RVDC32(DSPCBASE);
1068 temp = PSB_RVDC32(DSPCSURF);
1069 PSB_WVDC32(temp, DSPCSURF);
1070 PSB_RVDC32(DSPCSURF);
1071 }
1072 gma_power_end(dev);
1073 }
1074 }
1075
1076 return 0;
1077}
1078
1079static int psb_driver_open(struct drm_device *dev, struct drm_file *priv) 574static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1080{ 575{
1081 return 0; 576 return 0;
diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h
index a5ae9b185efb..956774888cc3 100644
--- a/drivers/gpu/drm/gma500/psb_drv.h
+++ b/drivers/gpu/drm/gma500/psb_drv.h
@@ -324,8 +324,6 @@ struct drm_psb_private {
324 * Sizes info 324 * Sizes info
325 */ 325 */
326 326
327 struct drm_psb_sizes_arg sizes;
328
329 u32 fuse_reg_value; 327 u32 fuse_reg_value;
330 u32 video_device_fuse; 328 u32 video_device_fuse;
331 329
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 18:08:33 -0500