diff options
-rw-r--r-- | arch/x86/kernel/numaq_32.c | 278 | ||||
-rw-r--r-- | arch/x86/mach-generic/Makefile | 1 | ||||
-rw-r--r-- | arch/x86/mach-generic/numaq.c | 277 |
3 files changed, 278 insertions, 278 deletions
diff --git a/arch/x86/kernel/numaq_32.c b/arch/x86/kernel/numaq_32.c index 3928280278f0..83bb05524f43 100644 --- a/arch/x86/kernel/numaq_32.c +++ b/arch/x86/kernel/numaq_32.c | |||
@@ -291,3 +291,281 @@ int __init get_memcfg_numaq(void) | |||
291 | smp_dump_qct(); | 291 | smp_dump_qct(); |
292 | return 1; | 292 | return 1; |
293 | } | 293 | } |
294 | |||
295 | /* | ||
296 | * APIC driver for the IBM NUMAQ chipset. | ||
297 | */ | ||
298 | #define APIC_DEFINITION 1 | ||
299 | #include <linux/threads.h> | ||
300 | #include <linux/cpumask.h> | ||
301 | #include <asm/mpspec.h> | ||
302 | #include <asm/genapic.h> | ||
303 | #include <asm/fixmap.h> | ||
304 | #include <asm/apicdef.h> | ||
305 | #include <linux/kernel.h> | ||
306 | #include <linux/string.h> | ||
307 | #include <linux/init.h> | ||
308 | #include <linux/numa.h> | ||
309 | #include <linux/smp.h> | ||
310 | #include <asm/numaq.h> | ||
311 | #include <asm/io.h> | ||
312 | #include <linux/mmzone.h> | ||
313 | #include <linux/nodemask.h> | ||
314 | |||
315 | #define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER) | ||
316 | |||
317 | static inline unsigned int numaq_get_apic_id(unsigned long x) | ||
318 | { | ||
319 | return (x >> 24) & 0x0F; | ||
320 | } | ||
321 | |||
322 | void default_send_IPI_mask_sequence(const struct cpumask *mask, int vector); | ||
323 | void default_send_IPI_mask_allbutself(const struct cpumask *mask, int vector); | ||
324 | |||
325 | static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector) | ||
326 | { | ||
327 | default_send_IPI_mask_sequence(mask, vector); | ||
328 | } | ||
329 | |||
330 | static inline void numaq_send_IPI_allbutself(int vector) | ||
331 | { | ||
332 | default_send_IPI_mask_allbutself(cpu_online_mask, vector); | ||
333 | } | ||
334 | |||
335 | static inline void numaq_send_IPI_all(int vector) | ||
336 | { | ||
337 | numaq_send_IPI_mask(cpu_online_mask, vector); | ||
338 | } | ||
339 | |||
340 | extern void numaq_mps_oem_check(struct mpc_table *, char *, char *); | ||
341 | |||
342 | #define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8) | ||
343 | #define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa) | ||
344 | |||
345 | /* | ||
346 | * Because we use NMIs rather than the INIT-STARTUP sequence to | ||
347 | * bootstrap the CPUs, the APIC may be in a weird state. Kick it: | ||
348 | */ | ||
349 | static inline void numaq_smp_callin_clear_local_apic(void) | ||
350 | { | ||
351 | clear_local_APIC(); | ||
352 | } | ||
353 | |||
354 | static inline void | ||
355 | numaq_store_NMI_vector(unsigned short *high, unsigned short *low) | ||
356 | { | ||
357 | printk("Storing NMI vector\n"); | ||
358 | *high = | ||
359 | *((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_HIGH)); | ||
360 | *low = | ||
361 | *((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_LOW)); | ||
362 | } | ||
363 | |||
364 | static inline const cpumask_t *numaq_target_cpus(void) | ||
365 | { | ||
366 | return &CPU_MASK_ALL; | ||
367 | } | ||
368 | |||
369 | static inline unsigned long | ||
370 | numaq_check_apicid_used(physid_mask_t bitmap, int apicid) | ||
371 | { | ||
372 | return physid_isset(apicid, bitmap); | ||
373 | } | ||
374 | |||
375 | static inline unsigned long numaq_check_apicid_present(int bit) | ||
376 | { | ||
377 | return physid_isset(bit, phys_cpu_present_map); | ||
378 | } | ||
379 | |||
380 | #define apicid_cluster(apicid) (apicid & 0xF0) | ||
381 | |||
382 | static inline int numaq_apic_id_registered(void) | ||
383 | { | ||
384 | return 1; | ||
385 | } | ||
386 | |||
387 | static inline void numaq_init_apic_ldr(void) | ||
388 | { | ||
389 | /* Already done in NUMA-Q firmware */ | ||
390 | } | ||
391 | |||
392 | static inline void numaq_setup_apic_routing(void) | ||
393 | { | ||
394 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", | ||
395 | "NUMA-Q", nr_ioapics); | ||
396 | } | ||
397 | |||
398 | /* | ||
399 | * Skip adding the timer int on secondary nodes, which causes | ||
400 | * a small but painful rift in the time-space continuum. | ||
401 | */ | ||
402 | static inline int numaq_multi_timer_check(int apic, int irq) | ||
403 | { | ||
404 | return apic != 0 && irq == 0; | ||
405 | } | ||
406 | |||
407 | static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map) | ||
408 | { | ||
409 | /* We don't have a good way to do this yet - hack */ | ||
410 | return physids_promote(0xFUL); | ||
411 | } | ||
412 | |||
413 | /* Mapping from cpu number to logical apicid */ | ||
414 | extern u8 cpu_2_logical_apicid[]; | ||
415 | |||
416 | static inline int numaq_cpu_to_logical_apicid(int cpu) | ||
417 | { | ||
418 | if (cpu >= nr_cpu_ids) | ||
419 | return BAD_APICID; | ||
420 | return (int)cpu_2_logical_apicid[cpu]; | ||
421 | } | ||
422 | |||
423 | /* | ||
424 | * Supporting over 60 cpus on NUMA-Q requires a locality-dependent | ||
425 | * cpu to APIC ID relation to properly interact with the intelligent | ||
426 | * mode of the cluster controller. | ||
427 | */ | ||
428 | static inline int numaq_cpu_present_to_apicid(int mps_cpu) | ||
429 | { | ||
430 | if (mps_cpu < 60) | ||
431 | return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3)); | ||
432 | else | ||
433 | return BAD_APICID; | ||
434 | } | ||
435 | |||
436 | static inline int numaq_apicid_to_node(int logical_apicid) | ||
437 | { | ||
438 | return logical_apicid >> 4; | ||
439 | } | ||
440 | |||
441 | static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid) | ||
442 | { | ||
443 | int node = numaq_apicid_to_node(logical_apicid); | ||
444 | int cpu = __ffs(logical_apicid & 0xf); | ||
445 | |||
446 | return physid_mask_of_physid(cpu + 4*node); | ||
447 | } | ||
448 | |||
449 | extern void *xquad_portio; | ||
450 | |||
451 | static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid) | ||
452 | { | ||
453 | return 1; | ||
454 | } | ||
455 | |||
456 | /* | ||
457 | * We use physical apicids here, not logical, so just return the default | ||
458 | * physical broadcast to stop people from breaking us | ||
459 | */ | ||
460 | static inline unsigned int numaq_cpu_mask_to_apicid(const cpumask_t *cpumask) | ||
461 | { | ||
462 | return 0x0F; | ||
463 | } | ||
464 | |||
465 | static inline unsigned int | ||
466 | numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
467 | const struct cpumask *andmask) | ||
468 | { | ||
469 | return 0x0F; | ||
470 | } | ||
471 | |||
472 | /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */ | ||
473 | static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb) | ||
474 | { | ||
475 | return cpuid_apic >> index_msb; | ||
476 | } | ||
477 | static int __numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid) | ||
478 | { | ||
479 | numaq_mps_oem_check(mpc, oem, productid); | ||
480 | return found_numaq; | ||
481 | } | ||
482 | |||
483 | static int probe_numaq(void) | ||
484 | { | ||
485 | /* already know from get_memcfg_numaq() */ | ||
486 | return found_numaq; | ||
487 | } | ||
488 | |||
489 | static void numaq_vector_allocation_domain(int cpu, cpumask_t *retmask) | ||
490 | { | ||
491 | /* Careful. Some cpus do not strictly honor the set of cpus | ||
492 | * specified in the interrupt destination when using lowest | ||
493 | * priority interrupt delivery mode. | ||
494 | * | ||
495 | * In particular there was a hyperthreading cpu observed to | ||
496 | * deliver interrupts to the wrong hyperthread when only one | ||
497 | * hyperthread was specified in the interrupt desitination. | ||
498 | */ | ||
499 | *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } }; | ||
500 | } | ||
501 | |||
502 | static void numaq_setup_portio_remap(void) | ||
503 | { | ||
504 | int num_quads = num_online_nodes(); | ||
505 | |||
506 | if (num_quads <= 1) | ||
507 | return; | ||
508 | |||
509 | printk("Remapping cross-quad port I/O for %d quads\n", num_quads); | ||
510 | xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD); | ||
511 | printk("xquad_portio vaddr 0x%08lx, len %08lx\n", | ||
512 | (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD); | ||
513 | } | ||
514 | |||
515 | struct genapic apic_numaq = { | ||
516 | |||
517 | .name = "NUMAQ", | ||
518 | .probe = probe_numaq, | ||
519 | .acpi_madt_oem_check = NULL, | ||
520 | .apic_id_registered = numaq_apic_id_registered, | ||
521 | |||
522 | .irq_delivery_mode = dest_LowestPrio, | ||
523 | /* physical delivery on LOCAL quad: */ | ||
524 | .irq_dest_mode = 0, | ||
525 | |||
526 | .target_cpus = numaq_target_cpus, | ||
527 | .disable_esr = 1, | ||
528 | .dest_logical = APIC_DEST_LOGICAL, | ||
529 | .check_apicid_used = numaq_check_apicid_used, | ||
530 | .check_apicid_present = numaq_check_apicid_present, | ||
531 | |||
532 | .vector_allocation_domain = numaq_vector_allocation_domain, | ||
533 | .init_apic_ldr = numaq_init_apic_ldr, | ||
534 | |||
535 | .ioapic_phys_id_map = numaq_ioapic_phys_id_map, | ||
536 | .setup_apic_routing = numaq_setup_apic_routing, | ||
537 | .multi_timer_check = numaq_multi_timer_check, | ||
538 | .apicid_to_node = numaq_apicid_to_node, | ||
539 | .cpu_to_logical_apicid = numaq_cpu_to_logical_apicid, | ||
540 | .cpu_present_to_apicid = numaq_cpu_present_to_apicid, | ||
541 | .apicid_to_cpu_present = numaq_apicid_to_cpu_present, | ||
542 | .setup_portio_remap = numaq_setup_portio_remap, | ||
543 | .check_phys_apicid_present = numaq_check_phys_apicid_present, | ||
544 | .enable_apic_mode = NULL, | ||
545 | .phys_pkg_id = numaq_phys_pkg_id, | ||
546 | .mps_oem_check = __numaq_mps_oem_check, | ||
547 | |||
548 | .get_apic_id = numaq_get_apic_id, | ||
549 | .set_apic_id = NULL, | ||
550 | .apic_id_mask = 0x0F << 24, | ||
551 | |||
552 | .cpu_mask_to_apicid = numaq_cpu_mask_to_apicid, | ||
553 | .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and, | ||
554 | |||
555 | .send_IPI_mask = numaq_send_IPI_mask, | ||
556 | .send_IPI_mask_allbutself = NULL, | ||
557 | .send_IPI_allbutself = numaq_send_IPI_allbutself, | ||
558 | .send_IPI_all = numaq_send_IPI_all, | ||
559 | .send_IPI_self = NULL, | ||
560 | |||
561 | .wakeup_cpu = NULL, | ||
562 | .trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW, | ||
563 | .trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH, | ||
564 | |||
565 | /* We don't do anything here because we use NMI's to boot instead */ | ||
566 | .wait_for_init_deassert = NULL, | ||
567 | |||
568 | .smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic, | ||
569 | .store_NMI_vector = numaq_store_NMI_vector, | ||
570 | .inquire_remote_apic = NULL, | ||
571 | }; | ||
diff --git a/arch/x86/mach-generic/Makefile b/arch/x86/mach-generic/Makefile index 05e47acfd666..4ede08d309e6 100644 --- a/arch/x86/mach-generic/Makefile +++ b/arch/x86/mach-generic/Makefile | |||
@@ -5,5 +5,4 @@ | |||
5 | EXTRA_CFLAGS := -Iarch/x86/kernel | 5 | EXTRA_CFLAGS := -Iarch/x86/kernel |
6 | 6 | ||
7 | obj-y := probe.o default.o | 7 | obj-y := probe.o default.o |
8 | obj-$(CONFIG_X86_NUMAQ) += numaq.o | ||
9 | obj-$(CONFIG_X86_BIGSMP) += bigsmp.o | 8 | obj-$(CONFIG_X86_BIGSMP) += bigsmp.o |
diff --git a/arch/x86/mach-generic/numaq.c b/arch/x86/mach-generic/numaq.c deleted file mode 100644 index c221cfb2c2db..000000000000 --- a/arch/x86/mach-generic/numaq.c +++ /dev/null | |||
@@ -1,277 +0,0 @@ | |||
1 | /* | ||
2 | * APIC driver for the IBM NUMAQ chipset. | ||
3 | */ | ||
4 | #define APIC_DEFINITION 1 | ||
5 | #include <linux/threads.h> | ||
6 | #include <linux/cpumask.h> | ||
7 | #include <asm/mpspec.h> | ||
8 | #include <asm/genapic.h> | ||
9 | #include <asm/fixmap.h> | ||
10 | #include <asm/apicdef.h> | ||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/string.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/numa.h> | ||
15 | #include <linux/smp.h> | ||
16 | #include <asm/numaq.h> | ||
17 | #include <asm/io.h> | ||
18 | #include <linux/mmzone.h> | ||
19 | #include <linux/nodemask.h> | ||
20 | |||
21 | #define NUMAQ_APIC_DFR_VALUE (APIC_DFR_CLUSTER) | ||
22 | |||
23 | static inline unsigned int numaq_get_apic_id(unsigned long x) | ||
24 | { | ||
25 | return (x >> 24) & 0x0F; | ||
26 | } | ||
27 | |||
28 | void default_send_IPI_mask_sequence(const struct cpumask *mask, int vector); | ||
29 | void default_send_IPI_mask_allbutself(const struct cpumask *mask, int vector); | ||
30 | |||
31 | static inline void numaq_send_IPI_mask(const struct cpumask *mask, int vector) | ||
32 | { | ||
33 | default_send_IPI_mask_sequence(mask, vector); | ||
34 | } | ||
35 | |||
36 | static inline void numaq_send_IPI_allbutself(int vector) | ||
37 | { | ||
38 | default_send_IPI_mask_allbutself(cpu_online_mask, vector); | ||
39 | } | ||
40 | |||
41 | static inline void numaq_send_IPI_all(int vector) | ||
42 | { | ||
43 | numaq_send_IPI_mask(cpu_online_mask, vector); | ||
44 | } | ||
45 | |||
46 | extern void numaq_mps_oem_check(struct mpc_table *, char *, char *); | ||
47 | |||
48 | #define NUMAQ_TRAMPOLINE_PHYS_LOW (0x8) | ||
49 | #define NUMAQ_TRAMPOLINE_PHYS_HIGH (0xa) | ||
50 | |||
51 | /* | ||
52 | * Because we use NMIs rather than the INIT-STARTUP sequence to | ||
53 | * bootstrap the CPUs, the APIC may be in a weird state. Kick it: | ||
54 | */ | ||
55 | static inline void numaq_smp_callin_clear_local_apic(void) | ||
56 | { | ||
57 | clear_local_APIC(); | ||
58 | } | ||
59 | |||
60 | static inline void | ||
61 | numaq_store_NMI_vector(unsigned short *high, unsigned short *low) | ||
62 | { | ||
63 | printk("Storing NMI vector\n"); | ||
64 | *high = | ||
65 | *((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_HIGH)); | ||
66 | *low = | ||
67 | *((volatile unsigned short *)phys_to_virt(NUMAQ_TRAMPOLINE_PHYS_LOW)); | ||
68 | } | ||
69 | |||
70 | static inline const cpumask_t *numaq_target_cpus(void) | ||
71 | { | ||
72 | return &CPU_MASK_ALL; | ||
73 | } | ||
74 | |||
75 | static inline unsigned long | ||
76 | numaq_check_apicid_used(physid_mask_t bitmap, int apicid) | ||
77 | { | ||
78 | return physid_isset(apicid, bitmap); | ||
79 | } | ||
80 | |||
81 | static inline unsigned long numaq_check_apicid_present(int bit) | ||
82 | { | ||
83 | return physid_isset(bit, phys_cpu_present_map); | ||
84 | } | ||
85 | |||
86 | #define apicid_cluster(apicid) (apicid & 0xF0) | ||
87 | |||
88 | static inline int numaq_apic_id_registered(void) | ||
89 | { | ||
90 | return 1; | ||
91 | } | ||
92 | |||
93 | static inline void numaq_init_apic_ldr(void) | ||
94 | { | ||
95 | /* Already done in NUMA-Q firmware */ | ||
96 | } | ||
97 | |||
98 | static inline void numaq_setup_apic_routing(void) | ||
99 | { | ||
100 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", | ||
101 | "NUMA-Q", nr_ioapics); | ||
102 | } | ||
103 | |||
104 | /* | ||
105 | * Skip adding the timer int on secondary nodes, which causes | ||
106 | * a small but painful rift in the time-space continuum. | ||
107 | */ | ||
108 | static inline int numaq_multi_timer_check(int apic, int irq) | ||
109 | { | ||
110 | return apic != 0 && irq == 0; | ||
111 | } | ||
112 | |||
113 | static inline physid_mask_t numaq_ioapic_phys_id_map(physid_mask_t phys_map) | ||
114 | { | ||
115 | /* We don't have a good way to do this yet - hack */ | ||
116 | return physids_promote(0xFUL); | ||
117 | } | ||
118 | |||
119 | /* Mapping from cpu number to logical apicid */ | ||
120 | extern u8 cpu_2_logical_apicid[]; | ||
121 | |||
122 | static inline int numaq_cpu_to_logical_apicid(int cpu) | ||
123 | { | ||
124 | if (cpu >= nr_cpu_ids) | ||
125 | return BAD_APICID; | ||
126 | return (int)cpu_2_logical_apicid[cpu]; | ||
127 | } | ||
128 | |||
129 | /* | ||
130 | * Supporting over 60 cpus on NUMA-Q requires a locality-dependent | ||
131 | * cpu to APIC ID relation to properly interact with the intelligent | ||
132 | * mode of the cluster controller. | ||
133 | */ | ||
134 | static inline int numaq_cpu_present_to_apicid(int mps_cpu) | ||
135 | { | ||
136 | if (mps_cpu < 60) | ||
137 | return ((mps_cpu >> 2) << 4) | (1 << (mps_cpu & 0x3)); | ||
138 | else | ||
139 | return BAD_APICID; | ||
140 | } | ||
141 | |||
142 | static inline int numaq_apicid_to_node(int logical_apicid) | ||
143 | { | ||
144 | return logical_apicid >> 4; | ||
145 | } | ||
146 | |||
147 | static inline physid_mask_t numaq_apicid_to_cpu_present(int logical_apicid) | ||
148 | { | ||
149 | int node = numaq_apicid_to_node(logical_apicid); | ||
150 | int cpu = __ffs(logical_apicid & 0xf); | ||
151 | |||
152 | return physid_mask_of_physid(cpu + 4*node); | ||
153 | } | ||
154 | |||
155 | extern void *xquad_portio; | ||
156 | |||
157 | static inline int numaq_check_phys_apicid_present(int boot_cpu_physical_apicid) | ||
158 | { | ||
159 | return 1; | ||
160 | } | ||
161 | |||
162 | /* | ||
163 | * We use physical apicids here, not logical, so just return the default | ||
164 | * physical broadcast to stop people from breaking us | ||
165 | */ | ||
166 | static inline unsigned int numaq_cpu_mask_to_apicid(const cpumask_t *cpumask) | ||
167 | { | ||
168 | return 0x0F; | ||
169 | } | ||
170 | |||
171 | static inline unsigned int | ||
172 | numaq_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | ||
173 | const struct cpumask *andmask) | ||
174 | { | ||
175 | return 0x0F; | ||
176 | } | ||
177 | |||
178 | /* No NUMA-Q box has a HT CPU, but it can't hurt to use the default code. */ | ||
179 | static inline int numaq_phys_pkg_id(int cpuid_apic, int index_msb) | ||
180 | { | ||
181 | return cpuid_apic >> index_msb; | ||
182 | } | ||
183 | static int __numaq_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid) | ||
184 | { | ||
185 | numaq_mps_oem_check(mpc, oem, productid); | ||
186 | return found_numaq; | ||
187 | } | ||
188 | |||
189 | static int probe_numaq(void) | ||
190 | { | ||
191 | /* already know from get_memcfg_numaq() */ | ||
192 | return found_numaq; | ||
193 | } | ||
194 | |||
195 | static void numaq_vector_allocation_domain(int cpu, cpumask_t *retmask) | ||
196 | { | ||
197 | /* Careful. Some cpus do not strictly honor the set of cpus | ||
198 | * specified in the interrupt destination when using lowest | ||
199 | * priority interrupt delivery mode. | ||
200 | * | ||
201 | * In particular there was a hyperthreading cpu observed to | ||
202 | * deliver interrupts to the wrong hyperthread when only one | ||
203 | * hyperthread was specified in the interrupt desitination. | ||
204 | */ | ||
205 | *retmask = (cpumask_t){ { [0] = APIC_ALL_CPUS, } }; | ||
206 | } | ||
207 | |||
208 | static void numaq_setup_portio_remap(void) | ||
209 | { | ||
210 | int num_quads = num_online_nodes(); | ||
211 | |||
212 | if (num_quads <= 1) | ||
213 | return; | ||
214 | |||
215 | printk("Remapping cross-quad port I/O for %d quads\n", num_quads); | ||
216 | xquad_portio = ioremap(XQUAD_PORTIO_BASE, num_quads*XQUAD_PORTIO_QUAD); | ||
217 | printk("xquad_portio vaddr 0x%08lx, len %08lx\n", | ||
218 | (u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD); | ||
219 | } | ||
220 | |||
221 | struct genapic apic_numaq = { | ||
222 | |||
223 | .name = "NUMAQ", | ||
224 | .probe = probe_numaq, | ||
225 | .acpi_madt_oem_check = NULL, | ||
226 | .apic_id_registered = numaq_apic_id_registered, | ||
227 | |||
228 | .irq_delivery_mode = dest_LowestPrio, | ||
229 | /* physical delivery on LOCAL quad: */ | ||
230 | .irq_dest_mode = 0, | ||
231 | |||
232 | .target_cpus = numaq_target_cpus, | ||
233 | .disable_esr = 1, | ||
234 | .dest_logical = APIC_DEST_LOGICAL, | ||
235 | .check_apicid_used = numaq_check_apicid_used, | ||
236 | .check_apicid_present = numaq_check_apicid_present, | ||
237 | |||
238 | .vector_allocation_domain = numaq_vector_allocation_domain, | ||
239 | .init_apic_ldr = numaq_init_apic_ldr, | ||
240 | |||
241 | .ioapic_phys_id_map = numaq_ioapic_phys_id_map, | ||
242 | .setup_apic_routing = numaq_setup_apic_routing, | ||
243 | .multi_timer_check = numaq_multi_timer_check, | ||
244 | .apicid_to_node = numaq_apicid_to_node, | ||
245 | .cpu_to_logical_apicid = numaq_cpu_to_logical_apicid, | ||
246 | .cpu_present_to_apicid = numaq_cpu_present_to_apicid, | ||
247 | .apicid_to_cpu_present = numaq_apicid_to_cpu_present, | ||
248 | .setup_portio_remap = numaq_setup_portio_remap, | ||
249 | .check_phys_apicid_present = numaq_check_phys_apicid_present, | ||
250 | .enable_apic_mode = NULL, | ||
251 | .phys_pkg_id = numaq_phys_pkg_id, | ||
252 | .mps_oem_check = __numaq_mps_oem_check, | ||
253 | |||
254 | .get_apic_id = numaq_get_apic_id, | ||
255 | .set_apic_id = NULL, | ||
256 | .apic_id_mask = 0x0F << 24, | ||
257 | |||
258 | .cpu_mask_to_apicid = numaq_cpu_mask_to_apicid, | ||
259 | .cpu_mask_to_apicid_and = numaq_cpu_mask_to_apicid_and, | ||
260 | |||
261 | .send_IPI_mask = numaq_send_IPI_mask, | ||
262 | .send_IPI_mask_allbutself = NULL, | ||
263 | .send_IPI_allbutself = numaq_send_IPI_allbutself, | ||
264 | .send_IPI_all = numaq_send_IPI_all, | ||
265 | .send_IPI_self = NULL, | ||
266 | |||
267 | .wakeup_cpu = NULL, | ||
268 | .trampoline_phys_low = NUMAQ_TRAMPOLINE_PHYS_LOW, | ||
269 | .trampoline_phys_high = NUMAQ_TRAMPOLINE_PHYS_HIGH, | ||
270 | |||
271 | /* We don't do anything here because we use NMI's to boot instead */ | ||
272 | .wait_for_init_deassert = NULL, | ||
273 | |||
274 | .smp_callin_clear_local_apic = numaq_smp_callin_clear_local_apic, | ||
275 | .store_NMI_vector = numaq_store_NMI_vector, | ||
276 | .inquire_remote_apic = NULL, | ||
277 | }; | ||