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-rw-r--r--drivers/gpu/drm/i915/i915_drv.c14
1 files changed, 0 insertions, 14 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3fa3eae0ee06..5c66b568bb81 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1199,21 +1199,7 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1199 u32 val; 1199 u32 val;
1200 int err; 1200 int err;
1201 1201
1202 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1203
1204#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) 1202#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1205 /* Wait for a previous force-off to settle */
1206 if (force_on && !IS_CHERRYVIEW(dev_priv->dev)) {
1207 /* WARN_ON only for the Valleyview */
1208 WARN_ON(!!(val & VLV_GFX_CLK_FORCE_ON_BIT) == force_on);
1209
1210 err = wait_for(!COND, 20);
1211 if (err) {
1212 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1213 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1214 return err;
1215 }
1216 }
1217 1203
1218 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); 1204 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1219 val &= ~VLV_GFX_CLK_FORCE_ON_BIT; 1205 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;