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-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-post.dtsi36
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi36
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi60
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi61
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi113
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi8
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi43
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi61
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi86
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi12
16 files changed, 536 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
index 5a6615d0ade2..60566f9927be 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -86,6 +86,42 @@
86 86
87 clockgen: global-utilities@e1000 { 87 clockgen: global-utilities@e1000 {
88 compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0"; 88 compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
89 ranges = <0x0 0xe1000 0x1000>;
90 #address-cells = <1>;
91 #size-cells = <1>;
92
93 sysclk: sysclk {
94 #clock-cells = <0>;
95 compatible = "fsl,qoriq-sysclk-2.0";
96 clock-output-names = "sysclk";
97 };
98
99 pll0: pll0@800 {
100 #clock-cells = <1>;
101 reg = <0x800 0x4>;
102 compatible = "fsl,qoriq-core-pll-2.0";
103 clocks = <&sysclk>;
104 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
105 };
106
107 pll1: pll1@820 {
108 #clock-cells = <1>;
109 reg = <0x820 0x4>;
110 compatible = "fsl,qoriq-core-pll-2.0";
111 clocks = <&sysclk>;
112 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
113 };
114
115 mux0: mux0@0 {
116 #clock-cells = <0>;
117 reg = <0x0 0x4>;
118 compatible = "fsl,qoriq-core-mux-2.0";
119 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
120 <&pll1 0>, <&pll1 1>, <&pll1 2>;
121 clock-names = "pll0", "pll0-div2", "pll0-div4",
122 "pll1", "pll1-div2", "pll1-div4";
123 clock-output-names = "cmux0";
124 };
89 }; 125 };
90 126
91 rcpm: global-utilities@e2000 { 127 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index c6e451affb05..2419731c2c54 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -64,11 +64,13 @@
64 cpu0: PowerPC,e6500@0 { 64 cpu0: PowerPC,e6500@0 {
65 device_type = "cpu"; 65 device_type = "cpu";
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>;
67 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
68 }; 69 };
69 cpu1: PowerPC,e6500@2 { 70 cpu1: PowerPC,e6500@2 {
70 device_type = "cpu"; 71 device_type = "cpu";
71 reg = <2 3>; 72 reg = <2 3>;
73 clocks = <&mux0>;
72 next-level-cache = <&L2>; 74 next-level-cache = <&L2>;
73 }; 75 };
74 }; 76 };
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index 981397518fc6..cbc354b05117 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -130,6 +130,42 @@
130 130
131 clockgen: global-utilities@e1000 { 131 clockgen: global-utilities@e1000 {
132 compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0"; 132 compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
133 ranges = <0x0 0xe1000 0x1000>;
134 #address-cells = <1>;
135 #size-cells = <1>;
136
137 sysclk: sysclk {
138 #clock-cells = <0>;
139 compatible = "fsl,qoriq-sysclk-2.0";
140 clock-output-names = "sysclk";
141 };
142
143 pll0: pll0@800 {
144 #clock-cells = <1>;
145 reg = <0x800 0x4>;
146 compatible = "fsl,qoriq-core-pll-2.0";
147 clocks = <&sysclk>;
148 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
149 };
150
151 pll1: pll1@820 {
152 #clock-cells = <1>;
153 reg = <0x820 0x4>;
154 compatible = "fsl,qoriq-core-pll-2.0";
155 clocks = <&sysclk>;
156 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
157 };
158
159 mux0: mux0@0 {
160 #clock-cells = <0>;
161 reg = <0x0 0x4>;
162 compatible = "fsl,qoriq-core-mux-2.0";
163 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
164 <&pll1 0>, <&pll1 1>, <&pll1 2>;
165 clock-names = "pll0", "pll0-div2", "pll0-div4",
166 "pll1", "pll1-div2", "pll1-div4";
167 clock-output-names = "cmux0";
168 };
133 }; 169 };
134 170
135 rcpm: global-utilities@e2000 { 171 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 9bc26b147900..142ac862cacf 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -64,21 +64,25 @@
64 cpu0: PowerPC,e6500@0 { 64 cpu0: PowerPC,e6500@0 {
65 device_type = "cpu"; 65 device_type = "cpu";
66 reg = <0 1>; 66 reg = <0 1>;
67 clocks = <&mux0>;
67 next-level-cache = <&L2>; 68 next-level-cache = <&L2>;
68 }; 69 };
69 cpu1: PowerPC,e6500@2 { 70 cpu1: PowerPC,e6500@2 {
70 device_type = "cpu"; 71 device_type = "cpu";
71 reg = <2 3>; 72 reg = <2 3>;
73 clocks = <&mux0>;
72 next-level-cache = <&L2>; 74 next-level-cache = <&L2>;
73 }; 75 };
74 cpu2: PowerPC,e6500@4 { 76 cpu2: PowerPC,e6500@4 {
75 device_type = "cpu"; 77 device_type = "cpu";
76 reg = <4 5>; 78 reg = <4 5>;
79 clocks = <&mux0>;
77 next-level-cache = <&L2>; 80 next-level-cache = <&L2>;
78 }; 81 };
79 cpu3: PowerPC,e6500@6 { 82 cpu3: PowerPC,e6500@6 {
80 device_type = "cpu"; 83 device_type = "cpu";
81 reg = <6 7>; 84 reg = <6 7>;
85 clocks = <&mux0>;
82 next-level-cache = <&L2>; 86 next-level-cache = <&L2>;
83 }; 87 };
84 }; 88 };
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index dc6cc5afd189..e2987a33083c 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -306,8 +306,68 @@
306 306
307 clockgen: global-utilities@e1000 { 307 clockgen: global-utilities@e1000 {
308 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0"; 308 compatible = "fsl,p2041-clockgen", "fsl,qoriq-clockgen-1.0";
309 ranges = <0x0 0xe1000 0x1000>;
309 reg = <0xe1000 0x1000>; 310 reg = <0xe1000 0x1000>;
310 clock-frequency = <0>; 311 clock-frequency = <0>;
312 #address-cells = <1>;
313 #size-cells = <1>;
314
315 sysclk: sysclk {
316 #clock-cells = <0>;
317 compatible = "fsl,qoriq-sysclk-1.0";
318 clock-output-names = "sysclk";
319 };
320
321 pll0: pll0@800 {
322 #clock-cells = <1>;
323 reg = <0x800 0x4>;
324 compatible = "fsl,qoriq-core-pll-1.0";
325 clocks = <&sysclk>;
326 clock-output-names = "pll0", "pll0-div2";
327 };
328
329 pll1: pll1@820 {
330 #clock-cells = <1>;
331 reg = <0x820 0x4>;
332 compatible = "fsl,qoriq-core-pll-1.0";
333 clocks = <&sysclk>;
334 clock-output-names = "pll1", "pll1-div2";
335 };
336
337 mux0: mux0@0 {
338 #clock-cells = <0>;
339 reg = <0x0 0x4>;
340 compatible = "fsl,qoriq-core-mux-1.0";
341 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
342 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
343 clock-output-names = "cmux0";
344 };
345
346 mux1: mux1@20 {
347 #clock-cells = <0>;
348 reg = <0x20 0x4>;
349 compatible = "fsl,qoriq-core-mux-1.0";
350 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
351 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
352 clock-output-names = "cmux1";
353 };
354
355 mux2: mux2@40 {
356 #clock-cells = <0>;
357 reg = <0x40 0x4>;
358 compatible = "fsl,qoriq-core-mux-1.0";
359 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
360 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
361 };
362
363 mux3: mux3@60 {
364 #clock-cells = <0>;
365 reg = <0x60 0x4>;
366 compatible = "fsl,qoriq-core-mux-1.0";
367 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
368 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
369 clock-output-names = "cmux3";
370 };
311 }; 371 };
312 372
313 rcpm: global-utilities@e2000 { 373 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
index 7a2697d04549..22f3b14517de 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-pre.dtsi
@@ -81,6 +81,7 @@
81 cpu0: PowerPC,e500mc@0 { 81 cpu0: PowerPC,e500mc@0 {
82 device_type = "cpu"; 82 device_type = "cpu";
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>;
84 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
85 L2_0: l2-cache { 86 L2_0: l2-cache {
86 next-level-cache = <&cpc>; 87 next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
89 cpu1: PowerPC,e500mc@1 { 90 cpu1: PowerPC,e500mc@1 {
90 device_type = "cpu"; 91 device_type = "cpu";
91 reg = <1>; 92 reg = <1>;
93 clocks = <&mux1>;
92 next-level-cache = <&L2_1>; 94 next-level-cache = <&L2_1>;
93 L2_1: l2-cache { 95 L2_1: l2-cache {
94 next-level-cache = <&cpc>; 96 next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
97 cpu2: PowerPC,e500mc@2 { 99 cpu2: PowerPC,e500mc@2 {
98 device_type = "cpu"; 100 device_type = "cpu";
99 reg = <2>; 101 reg = <2>;
102 clocks = <&mux2>;
100 next-level-cache = <&L2_2>; 103 next-level-cache = <&L2_2>;
101 L2_2: l2-cache { 104 L2_2: l2-cache {
102 next-level-cache = <&cpc>; 105 next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
105 cpu3: PowerPC,e500mc@3 { 108 cpu3: PowerPC,e500mc@3 {
106 device_type = "cpu"; 109 device_type = "cpu";
107 reg = <3>; 110 reg = <3>;
111 clocks = <&mux3>;
108 next-level-cache = <&L2_3>; 112 next-level-cache = <&L2_3>;
109 L2_3: l2-cache { 113 L2_3: l2-cache {
110 next-level-cache = <&cpc>; 114 next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 3fa1e22d544a..7af6d45fd998 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -333,8 +333,69 @@
333 333
334 clockgen: global-utilities@e1000 { 334 clockgen: global-utilities@e1000 {
335 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0"; 335 compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
336 ranges = <0x0 0xe1000 0x1000>;
336 reg = <0xe1000 0x1000>; 337 reg = <0xe1000 0x1000>;
337 clock-frequency = <0>; 338 clock-frequency = <0>;
339 #address-cells = <1>;
340 #size-cells = <1>;
341
342 sysclk: sysclk {
343 #clock-cells = <0>;
344 compatible = "fsl,qoriq-sysclk-1.0";
345 clock-output-names = "sysclk";
346 };
347
348 pll0: pll0@800 {
349 #clock-cells = <1>;
350 reg = <0x800 0x4>;
351 compatible = "fsl,qoriq-core-pll-1.0";
352 clocks = <&sysclk>;
353 clock-output-names = "pll0", "pll0-div2";
354 };
355
356 pll1: pll1@820 {
357 #clock-cells = <1>;
358 reg = <0x820 0x4>;
359 compatible = "fsl,qoriq-core-pll-1.0";
360 clocks = <&sysclk>;
361 clock-output-names = "pll1", "pll1-div2";
362 };
363
364 mux0: mux0@0 {
365 #clock-cells = <0>;
366 reg = <0x0 0x4>;
367 compatible = "fsl,qoriq-core-mux-1.0";
368 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
369 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
370 clock-output-names = "cmux0";
371 };
372
373 mux1: mux1@20 {
374 #clock-cells = <0>;
375 reg = <0x20 0x4>;
376 compatible = "fsl,qoriq-core-mux-1.0";
377 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
378 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
379 clock-output-names = "cmux1";
380 };
381
382 mux2: mux2@40 {
383 #clock-cells = <0>;
384 reg = <0x40 0x4>;
385 compatible = "fsl,qoriq-core-mux-1.0";
386 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
387 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
388 clock-output-names = "cmux2";
389 };
390
391 mux3: mux3@60 {
392 #clock-cells = <0>;
393 reg = <0x60 0x4>;
394 compatible = "fsl,qoriq-core-mux-1.0";
395 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
396 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
397 clock-output-names = "cmux3";
398 };
338 }; 399 };
339 400
340 rcpm: global-utilities@e2000 { 401 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
index c9ca2c305cfe..468e8be8ac6f 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-pre.dtsi
@@ -82,6 +82,7 @@
82 cpu0: PowerPC,e500mc@0 { 82 cpu0: PowerPC,e500mc@0 {
83 device_type = "cpu"; 83 device_type = "cpu";
84 reg = <0>; 84 reg = <0>;
85 clocks = <&mux0>;
85 next-level-cache = <&L2_0>; 86 next-level-cache = <&L2_0>;
86 L2_0: l2-cache { 87 L2_0: l2-cache {
87 next-level-cache = <&cpc>; 88 next-level-cache = <&cpc>;
@@ -90,6 +91,7 @@
90 cpu1: PowerPC,e500mc@1 { 91 cpu1: PowerPC,e500mc@1 {
91 device_type = "cpu"; 92 device_type = "cpu";
92 reg = <1>; 93 reg = <1>;
94 clocks = <&mux1>;
93 next-level-cache = <&L2_1>; 95 next-level-cache = <&L2_1>;
94 L2_1: l2-cache { 96 L2_1: l2-cache {
95 next-level-cache = <&cpc>; 97 next-level-cache = <&cpc>;
@@ -98,6 +100,7 @@
98 cpu2: PowerPC,e500mc@2 { 100 cpu2: PowerPC,e500mc@2 {
99 device_type = "cpu"; 101 device_type = "cpu";
100 reg = <2>; 102 reg = <2>;
103 clocks = <&mux2>;
101 next-level-cache = <&L2_2>; 104 next-level-cache = <&L2_2>;
102 L2_2: l2-cache { 105 L2_2: l2-cache {
103 next-level-cache = <&cpc>; 106 next-level-cache = <&cpc>;
@@ -106,6 +109,7 @@
106 cpu3: PowerPC,e500mc@3 { 109 cpu3: PowerPC,e500mc@3 {
107 device_type = "cpu"; 110 device_type = "cpu";
108 reg = <3>; 111 reg = <3>;
112 clocks = <&mux3>;
109 next-level-cache = <&L2_3>; 113 next-level-cache = <&L2_3>;
110 L2_3: l2-cache { 114 L2_3: l2-cache {
111 next-level-cache = <&cpc>; 115 next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 34769a7eafea..2415e1f1d3fa 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -353,8 +353,121 @@
353 353
354 clockgen: global-utilities@e1000 { 354 clockgen: global-utilities@e1000 {
355 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0"; 355 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
356 ranges = <0x0 0xe1000 0x1000>;
356 reg = <0xe1000 0x1000>; 357 reg = <0xe1000 0x1000>;
357 clock-frequency = <0>; 358 clock-frequency = <0>;
359 #address-cells = <1>;
360 #size-cells = <1>;
361
362 sysclk: sysclk {
363 #clock-cells = <0>;
364 compatible = "fsl,qoriq-sysclk-1.0";
365 clock-output-names = "sysclk";
366 };
367
368 pll0: pll0@800 {
369 #clock-cells = <1>;
370 reg = <0x800 0x4>;
371 compatible = "fsl,qoriq-core-pll-1.0";
372 clocks = <&sysclk>;
373 clock-output-names = "pll0", "pll0-div2";
374 };
375
376 pll1: pll1@820 {
377 #clock-cells = <1>;
378 reg = <0x820 0x4>;
379 compatible = "fsl,qoriq-core-pll-1.0";
380 clocks = <&sysclk>;
381 clock-output-names = "pll1", "pll1-div2";
382 };
383
384 pll2: pll2@840 {
385 #clock-cells = <1>;
386 reg = <0x840 0x4>;
387 compatible = "fsl,qoriq-core-pll-1.0";
388 clocks = <&sysclk>;
389 clock-output-names = "pll2", "pll2-div2";
390 };
391
392 pll3: pll3@860 {
393 #clock-cells = <1>;
394 reg = <0x860 0x4>;
395 compatible = "fsl,qoriq-core-pll-1.0";
396 clocks = <&sysclk>;
397 clock-output-names = "pll3", "pll3-div2";
398 };
399
400 mux0: mux0@0 {
401 #clock-cells = <0>;
402 reg = <0x0 0x4>;
403 compatible = "fsl,qoriq-core-mux-1.0";
404 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
405 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
406 clock-output-names = "cmux0";
407 };
408
409 mux1: mux1@20 {
410 #clock-cells = <0>;
411 reg = <0x20 0x4>;
412 compatible = "fsl,qoriq-core-mux-1.0";
413 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
414 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
415 clock-output-names = "cmux1";
416 };
417
418 mux2: mux2@40 {
419 #clock-cells = <0>;
420 reg = <0x40 0x4>;
421 compatible = "fsl,qoriq-core-mux-1.0";
422 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
423 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
424 clock-output-names = "cmux2";
425 };
426
427 mux3: mux3@60 {
428 #clock-cells = <0>;
429 reg = <0x60 0x4>;
430 compatible = "fsl,qoriq-core-mux-1.0";
431 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
432 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
433 clock-output-names = "cmux3";
434 };
435
436 mux4: mux4@80 {
437 #clock-cells = <0>;
438 reg = <0x80 0x4>;
439 compatible = "fsl,qoriq-core-mux-1.0";
440 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
441 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
442 clock-output-names = "cmux4";
443 };
444
445 mux5: mux5@a0 {
446 #clock-cells = <0>;
447 reg = <0xa0 0x4>;
448 compatible = "fsl,qoriq-core-mux-1.0";
449 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
450 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
451 clock-output-names = "cmux5";
452 };
453
454 mux6: mux6@c0 {
455 #clock-cells = <0>;
456 reg = <0xc0 0x4>;
457 compatible = "fsl,qoriq-core-mux-1.0";
458 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
459 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
460 clock-output-names = "cmux6";
461 };
462
463 mux7: mux7@e0 {
464 #clock-cells = <0>;
465 reg = <0xe0 0x4>;
466 compatible = "fsl,qoriq-core-mux-1.0";
467 clocks = <&pll2 0>, <&pll2 1>, <&pll3 0>, <&pll3 1>;
468 clock-names = "pll2", "pll2-div2", "pll3", "pll3-div2";
469 clock-output-names = "cmux7";
470 };
358 }; 471 };
359 472
360 rcpm: global-utilities@e2000 { 473 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
index 493d9a056b5c..0040b5a5379e 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-pre.dtsi
@@ -81,6 +81,7 @@
81 cpu0: PowerPC,e500mc@0 { 81 cpu0: PowerPC,e500mc@0 {
82 device_type = "cpu"; 82 device_type = "cpu";
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>;
84 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
85 L2_0: l2-cache { 86 L2_0: l2-cache {
86 next-level-cache = <&cpc>; 87 next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
89 cpu1: PowerPC,e500mc@1 { 90 cpu1: PowerPC,e500mc@1 {
90 device_type = "cpu"; 91 device_type = "cpu";
91 reg = <1>; 92 reg = <1>;
93 clocks = <&mux1>;
92 next-level-cache = <&L2_1>; 94 next-level-cache = <&L2_1>;
93 L2_1: l2-cache { 95 L2_1: l2-cache {
94 next-level-cache = <&cpc>; 96 next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
97 cpu2: PowerPC,e500mc@2 { 99 cpu2: PowerPC,e500mc@2 {
98 device_type = "cpu"; 100 device_type = "cpu";
99 reg = <2>; 101 reg = <2>;
102 clocks = <&mux2>;
100 next-level-cache = <&L2_2>; 103 next-level-cache = <&L2_2>;
101 L2_2: l2-cache { 104 L2_2: l2-cache {
102 next-level-cache = <&cpc>; 105 next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
105 cpu3: PowerPC,e500mc@3 { 108 cpu3: PowerPC,e500mc@3 {
106 device_type = "cpu"; 109 device_type = "cpu";
107 reg = <3>; 110 reg = <3>;
111 clocks = <&mux3>;
108 next-level-cache = <&L2_3>; 112 next-level-cache = <&L2_3>;
109 L2_3: l2-cache { 113 L2_3: l2-cache {
110 next-level-cache = <&cpc>; 114 next-level-cache = <&cpc>;
@@ -113,6 +117,7 @@
113 cpu4: PowerPC,e500mc@4 { 117 cpu4: PowerPC,e500mc@4 {
114 device_type = "cpu"; 118 device_type = "cpu";
115 reg = <4>; 119 reg = <4>;
120 clocks = <&mux4>;
116 next-level-cache = <&L2_4>; 121 next-level-cache = <&L2_4>;
117 L2_4: l2-cache { 122 L2_4: l2-cache {
118 next-level-cache = <&cpc>; 123 next-level-cache = <&cpc>;
@@ -121,6 +126,7 @@
121 cpu5: PowerPC,e500mc@5 { 126 cpu5: PowerPC,e500mc@5 {
122 device_type = "cpu"; 127 device_type = "cpu";
123 reg = <5>; 128 reg = <5>;
129 clocks = <&mux5>;
124 next-level-cache = <&L2_5>; 130 next-level-cache = <&L2_5>;
125 L2_5: l2-cache { 131 L2_5: l2-cache {
126 next-level-cache = <&cpc>; 132 next-level-cache = <&cpc>;
@@ -129,6 +135,7 @@
129 cpu6: PowerPC,e500mc@6 { 135 cpu6: PowerPC,e500mc@6 {
130 device_type = "cpu"; 136 device_type = "cpu";
131 reg = <6>; 137 reg = <6>;
138 clocks = <&mux6>;
132 next-level-cache = <&L2_6>; 139 next-level-cache = <&L2_6>;
133 L2_6: l2-cache { 140 L2_6: l2-cache {
134 next-level-cache = <&cpc>; 141 next-level-cache = <&cpc>;
@@ -137,6 +144,7 @@
137 cpu7: PowerPC,e500mc@7 { 144 cpu7: PowerPC,e500mc@7 {
138 device_type = "cpu"; 145 device_type = "cpu";
139 reg = <7>; 146 reg = <7>;
147 clocks = <&mux7>;
140 next-level-cache = <&L2_7>; 148 next-level-cache = <&L2_7>;
141 L2_7: l2-cache { 149 L2_7: l2-cache {
142 next-level-cache = <&cpc>; 150 next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index bc3ae5a2252f..2985de4ad6be 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -338,8 +338,51 @@
338 338
339 clockgen: global-utilities@e1000 { 339 clockgen: global-utilities@e1000 {
340 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0"; 340 compatible = "fsl,p5020-clockgen", "fsl,qoriq-clockgen-1.0";
341 ranges = <0x0 0xe1000 0x1000>;
341 reg = <0xe1000 0x1000>; 342 reg = <0xe1000 0x1000>;
342 clock-frequency = <0>; 343 clock-frequency = <0>;
344 #address-cells = <1>;
345 #size-cells = <1>;
346
347 sysclk: sysclk {
348 #clock-cells = <0>;
349 compatible = "fsl,qoriq-sysclk-1.0";
350 clock-output-names = "sysclk";
351 };
352
353 pll0: pll0@800 {
354 #clock-cells = <1>;
355 reg = <0x800 0x4>;
356 compatible = "fsl,qoriq-core-pll-1.0";
357 clocks = <&sysclk>;
358 clock-output-names = "pll0", "pll0-div2";
359 };
360
361 pll1: pll1@820 {
362 #clock-cells = <1>;
363 reg = <0x820 0x4>;
364 compatible = "fsl,qoriq-core-pll-1.0";
365 clocks = <&sysclk>;
366 clock-output-names = "pll1", "pll1-div2";
367 };
368
369 mux0: mux0@0 {
370 #clock-cells = <0>;
371 reg = <0x0 0x4>;
372 compatible = "fsl,qoriq-core-mux-1.0";
373 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
374 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
375 clock-output-names = "cmux0";
376 };
377
378 mux1: mux1@20 {
379 #clock-cells = <0>;
380 reg = <0x20 0x4>;
381 compatible = "fsl,qoriq-core-mux-1.0";
382 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
383 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
384 clock-output-names = "cmux1";
385 };
343 }; 386 };
344 387
345 rcpm: global-utilities@e2000 { 388 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
index 8df47fc45ab5..fe1a2e6613b4 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi
@@ -88,6 +88,7 @@
88 cpu0: PowerPC,e5500@0 { 88 cpu0: PowerPC,e5500@0 {
89 device_type = "cpu"; 89 device_type = "cpu";
90 reg = <0>; 90 reg = <0>;
91 clocks = <&mux0>;
91 next-level-cache = <&L2_0>; 92 next-level-cache = <&L2_0>;
92 L2_0: l2-cache { 93 L2_0: l2-cache {
93 next-level-cache = <&cpc>; 94 next-level-cache = <&cpc>;
@@ -96,6 +97,7 @@
96 cpu1: PowerPC,e5500@1 { 97 cpu1: PowerPC,e5500@1 {
97 device_type = "cpu"; 98 device_type = "cpu";
98 reg = <1>; 99 reg = <1>;
100 clocks = <&mux1>;
99 next-level-cache = <&L2_1>; 101 next-level-cache = <&L2_1>;
100 L2_1: l2-cache { 102 L2_1: l2-cache {
101 next-level-cache = <&cpc>; 103 next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index a91897f6af09..546a899efe20 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -298,8 +298,69 @@
298 298
299 clockgen: global-utilities@e1000 { 299 clockgen: global-utilities@e1000 {
300 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0"; 300 compatible = "fsl,p5040-clockgen", "fsl,qoriq-clockgen-1.0";
301 ranges = <0x0 0xe1000 0x1000>;
301 reg = <0xe1000 0x1000>; 302 reg = <0xe1000 0x1000>;
302 clock-frequency = <0>; 303 clock-frequency = <0>;
304 #address-cells = <1>;
305 #size-cells = <1>;
306
307 sysclk: sysclk {
308 #clock-cells = <0>;
309 compatible = "fsl,qoriq-sysclk-1.0";
310 clock-output-names = "sysclk";
311 };
312
313 pll0: pll0@800 {
314 #clock-cells = <1>;
315 reg = <0x800 0x4>;
316 compatible = "fsl,qoriq-core-pll-1.0";
317 clocks = <&sysclk>;
318 clock-output-names = "pll0", "pll0-div2";
319 };
320
321 pll1: pll1@820 {
322 #clock-cells = <1>;
323 reg = <0x820 0x4>;
324 compatible = "fsl,qoriq-core-pll-1.0";
325 clocks = <&sysclk>;
326 clock-output-names = "pll1", "pll1-div2";
327 };
328
329 mux0: mux0@0 {
330 #clock-cells = <0>;
331 reg = <0x0 0x4>;
332 compatible = "fsl,qoriq-core-mux-1.0";
333 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
334 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
335 clock-output-names = "cmux0";
336 };
337
338 mux1: mux1@20 {
339 #clock-cells = <0>;
340 reg = <0x20 0x4>;
341 compatible = "fsl,qoriq-core-mux-1.0";
342 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
343 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
344 clock-output-names = "cmux1";
345 };
346
347 mux2: mux2@40 {
348 #clock-cells = <0>;
349 reg = <0x40 0x4>;
350 compatible = "fsl,qoriq-core-mux-1.0";
351 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
352 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
353 clock-output-names = "cmux2";
354 };
355
356 mux3: mux3@60 {
357 #clock-cells = <0>;
358 reg = <0x60 0x4>;
359 compatible = "fsl,qoriq-core-mux-1.0";
360 clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
361 clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
362 clock-output-names = "cmux3";
363 };
303 }; 364 };
304 365
305 rcpm: global-utilities@e2000 { 366 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
index 40ca943f5d1c..3674686687cb 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-pre.dtsi
@@ -81,6 +81,7 @@
81 cpu0: PowerPC,e5500@0 { 81 cpu0: PowerPC,e5500@0 {
82 device_type = "cpu"; 82 device_type = "cpu";
83 reg = <0>; 83 reg = <0>;
84 clocks = <&mux0>;
84 next-level-cache = <&L2_0>; 85 next-level-cache = <&L2_0>;
85 L2_0: l2-cache { 86 L2_0: l2-cache {
86 next-level-cache = <&cpc>; 87 next-level-cache = <&cpc>;
@@ -89,6 +90,7 @@
89 cpu1: PowerPC,e5500@1 { 90 cpu1: PowerPC,e5500@1 {
90 device_type = "cpu"; 91 device_type = "cpu";
91 reg = <1>; 92 reg = <1>;
93 clocks = <&mux1>;
92 next-level-cache = <&L2_1>; 94 next-level-cache = <&L2_1>;
93 L2_1: l2-cache { 95 L2_1: l2-cache {
94 next-level-cache = <&cpc>; 96 next-level-cache = <&cpc>;
@@ -97,6 +99,7 @@
97 cpu2: PowerPC,e5500@2 { 99 cpu2: PowerPC,e5500@2 {
98 device_type = "cpu"; 100 device_type = "cpu";
99 reg = <2>; 101 reg = <2>;
102 clocks = <&mux2>;
100 next-level-cache = <&L2_2>; 103 next-level-cache = <&L2_2>;
101 L2_2: l2-cache { 104 L2_2: l2-cache {
102 next-level-cache = <&cpc>; 105 next-level-cache = <&cpc>;
@@ -105,6 +108,7 @@
105 cpu3: PowerPC,e5500@3 { 108 cpu3: PowerPC,e5500@3 {
106 device_type = "cpu"; 109 device_type = "cpu";
107 reg = <3>; 110 reg = <3>;
111 clocks = <&mux3>;
108 next-level-cache = <&L2_3>; 112 next-level-cache = <&L2_3>;
109 L2_3: l2-cache { 113 L2_3: l2-cache {
110 next-level-cache = <&cpc>; 114 next-level-cache = <&cpc>;
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index 4143a9733cd0..f99d74ff11b4 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -369,7 +369,93 @@
369 369
370 clockgen: global-utilities@e1000 { 370 clockgen: global-utilities@e1000 {
371 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0"; 371 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
372 ranges = <0x0 0xe1000 0x1000>;
372 reg = <0xe1000 0x1000>; 373 reg = <0xe1000 0x1000>;
374 #address-cells = <1>;
375 #size-cells = <1>;
376
377 sysclk: sysclk {
378 #clock-cells = <0>;
379 compatible = "fsl,qoriq-sysclk-2.0";
380 clock-output-names = "sysclk";
381 };
382
383 pll0: pll0@800 {
384 #clock-cells = <1>;
385 reg = <0x800 0x4>;
386 compatible = "fsl,qoriq-core-pll-2.0";
387 clocks = <&sysclk>;
388 clock-output-names = "pll0", "pll0-div2", "pll0-div4";
389 };
390
391 pll1: pll1@820 {
392 #clock-cells = <1>;
393 reg = <0x820 0x4>;
394 compatible = "fsl,qoriq-core-pll-2.0";
395 clocks = <&sysclk>;
396 clock-output-names = "pll1", "pll1-div2", "pll1-div4";
397 };
398
399 pll2: pll2@840 {
400 #clock-cells = <1>;
401 reg = <0x840 0x4>;
402 compatible = "fsl,qoriq-core-pll-2.0";
403 clocks = <&sysclk>;
404 clock-output-names = "pll2", "pll2-div2", "pll2-div4";
405 };
406
407 pll3: pll3@860 {
408 #clock-cells = <1>;
409 reg = <0x860 0x4>;
410 compatible = "fsl,qoriq-core-pll-2.0";
411 clocks = <&sysclk>;
412 clock-output-names = "pll3", "pll3-div2", "pll3-div4";
413 };
414
415 pll4: pll4@880 {
416 #clock-cells = <1>;
417 reg = <0x880 0x4>;
418 compatible = "fsl,qoriq-core-pll-2.0";
419 clocks = <&sysclk>;
420 clock-output-names = "pll4", "pll4-div2", "pll4-div4";
421 };
422
423 mux0: mux0@0 {
424 #clock-cells = <0>;
425 reg = <0x0 0x4>;
426 compatible = "fsl,qoriq-core-mux-2.0";
427 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
428 <&pll1 0>, <&pll1 1>, <&pll1 2>,
429 <&pll2 0>, <&pll2 1>, <&pll2 2>;
430 clock-names = "pll0", "pll0-div2", "pll0-div4",
431 "pll1", "pll1-div2", "pll1-div4",
432 "pll2", "pll2-div2", "pll2-div4";
433 clock-output-names = "cmux0";
434 };
435
436 mux1: mux1@20 {
437 #clock-cells = <0>;
438 reg = <0x20 0x4>;
439 compatible = "fsl,qoriq-core-mux-2.0";
440 clocks = <&pll0 0>, <&pll0 1>, <&pll0 2>,
441 <&pll1 0>, <&pll1 1>, <&pll1 2>,
442 <&pll2 0>, <&pll2 1>, <&pll2 2>;
443 clock-names = "pll0", "pll0-div2", "pll0-div4",
444 "pll1", "pll1-div2", "pll1-div4",
445 "pll2", "pll2-div2", "pll2-div4";
446 clock-output-names = "cmux1";
447 };
448
449 mux2: mux2@40 {
450 #clock-cells = <0>;
451 reg = <0x40 0x4>;
452 compatible = "fsl,qoriq-core-mux-2.0";
453 clocks = <&pll3 0>, <&pll3 1>, <&pll3 2>,
454 <&pll4 0>, <&pll4 1>, <&pll4 2>;
455 clock-names = "pll3", "pll3-div2", "pll3-div4",
456 "pll4", "pll4-div2", "pll4-div4";
457 clock-output-names = "cmux2";
458 };
373 }; 459 };
374 460
375 rcpm: global-utilities@e2000 { 461 rcpm: global-utilities@e2000 {
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
index a93c55a88560..0b8ccc5b4a46 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -67,61 +67,73 @@
67 cpu0: PowerPC,e6500@0 { 67 cpu0: PowerPC,e6500@0 {
68 device_type = "cpu"; 68 device_type = "cpu";
69 reg = <0 1>; 69 reg = <0 1>;
70 clocks = <&mux0>;
70 next-level-cache = <&L2_1>; 71 next-level-cache = <&L2_1>;
71 }; 72 };
72 cpu1: PowerPC,e6500@2 { 73 cpu1: PowerPC,e6500@2 {
73 device_type = "cpu"; 74 device_type = "cpu";
74 reg = <2 3>; 75 reg = <2 3>;
76 clocks = <&mux0>;
75 next-level-cache = <&L2_1>; 77 next-level-cache = <&L2_1>;
76 }; 78 };
77 cpu2: PowerPC,e6500@4 { 79 cpu2: PowerPC,e6500@4 {
78 device_type = "cpu"; 80 device_type = "cpu";
79 reg = <4 5>; 81 reg = <4 5>;
82 clocks = <&mux0>;
80 next-level-cache = <&L2_1>; 83 next-level-cache = <&L2_1>;
81 }; 84 };
82 cpu3: PowerPC,e6500@6 { 85 cpu3: PowerPC,e6500@6 {
83 device_type = "cpu"; 86 device_type = "cpu";
84 reg = <6 7>; 87 reg = <6 7>;
88 clocks = <&mux0>;
85 next-level-cache = <&L2_1>; 89 next-level-cache = <&L2_1>;
86 }; 90 };
87 cpu4: PowerPC,e6500@8 { 91 cpu4: PowerPC,e6500@8 {
88 device_type = "cpu"; 92 device_type = "cpu";
89 reg = <8 9>; 93 reg = <8 9>;
94 clocks = <&mux1>;
90 next-level-cache = <&L2_2>; 95 next-level-cache = <&L2_2>;
91 }; 96 };
92 cpu5: PowerPC,e6500@10 { 97 cpu5: PowerPC,e6500@10 {
93 device_type = "cpu"; 98 device_type = "cpu";
94 reg = <10 11>; 99 reg = <10 11>;
100 clocks = <&mux1>;
95 next-level-cache = <&L2_2>; 101 next-level-cache = <&L2_2>;
96 }; 102 };
97 cpu6: PowerPC,e6500@12 { 103 cpu6: PowerPC,e6500@12 {
98 device_type = "cpu"; 104 device_type = "cpu";
99 reg = <12 13>; 105 reg = <12 13>;
106 clocks = <&mux1>;
100 next-level-cache = <&L2_2>; 107 next-level-cache = <&L2_2>;
101 }; 108 };
102 cpu7: PowerPC,e6500@14 { 109 cpu7: PowerPC,e6500@14 {
103 device_type = "cpu"; 110 device_type = "cpu";
104 reg = <14 15>; 111 reg = <14 15>;
112 clocks = <&mux1>;
105 next-level-cache = <&L2_2>; 113 next-level-cache = <&L2_2>;
106 }; 114 };
107 cpu8: PowerPC,e6500@16 { 115 cpu8: PowerPC,e6500@16 {
108 device_type = "cpu"; 116 device_type = "cpu";
109 reg = <16 17>; 117 reg = <16 17>;
118 clocks = <&mux2>;
110 next-level-cache = <&L2_3>; 119 next-level-cache = <&L2_3>;
111 }; 120 };
112 cpu9: PowerPC,e6500@18 { 121 cpu9: PowerPC,e6500@18 {
113 device_type = "cpu"; 122 device_type = "cpu";
114 reg = <18 19>; 123 reg = <18 19>;
124 clocks = <&mux2>;
115 next-level-cache = <&L2_3>; 125 next-level-cache = <&L2_3>;
116 }; 126 };
117 cpu10: PowerPC,e6500@20 { 127 cpu10: PowerPC,e6500@20 {
118 device_type = "cpu"; 128 device_type = "cpu";
119 reg = <20 21>; 129 reg = <20 21>;
130 clocks = <&mux2>;
120 next-level-cache = <&L2_3>; 131 next-level-cache = <&L2_3>;
121 }; 132 };
122 cpu11: PowerPC,e6500@22 { 133 cpu11: PowerPC,e6500@22 {
123 device_type = "cpu"; 134 device_type = "cpu";
124 reg = <22 23>; 135 reg = <22 23>;
136 clocks = <&mux2>;
125 next-level-cache = <&L2_3>; 137 next-level-cache = <&L2_3>;
126 }; 138 };
127 }; 139 };
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 15:36:35 -0500