diff options
-rw-r--r-- | arch/arm/mach-imx/ehci-imx25.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-imx/ehci-imx35.c | 24 | ||||
-rw-r--r-- | arch/arm/mach-imx/ehci-imx5.c | 17 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mxc_ehci.h | 16 |
4 files changed, 67 insertions, 14 deletions
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c index 865daf0b09e9..05bb41d99728 100644 --- a/arch/arm/mach-imx/ehci-imx25.c +++ b/arch/arm/mach-imx/ehci-imx25.c | |||
@@ -24,14 +24,18 @@ | |||
24 | #define MX25_OTG_SIC_SHIFT 29 | 24 | #define MX25_OTG_SIC_SHIFT 29 |
25 | #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) | 25 | #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT) |
26 | #define MX25_OTG_PM_BIT (1 << 24) | 26 | #define MX25_OTG_PM_BIT (1 << 24) |
27 | #define MX25_OTG_PP_BIT (1 << 11) | ||
28 | #define MX25_OTG_OCPOL_BIT (1 << 3) | ||
27 | 29 | ||
28 | #define MX25_H1_SIC_SHIFT 21 | 30 | #define MX25_H1_SIC_SHIFT 21 |
29 | #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) | 31 | #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT) |
32 | #define MX25_H1_PP_BIT (1 << 18) | ||
30 | #define MX25_H1_PM_BIT (1 << 8) | 33 | #define MX25_H1_PM_BIT (1 << 8) |
31 | #define MX25_H1_IPPUE_UP_BIT (1 << 7) | 34 | #define MX25_H1_IPPUE_UP_BIT (1 << 7) |
32 | #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) | 35 | #define MX25_H1_IPPUE_DOWN_BIT (1 << 6) |
33 | #define MX25_H1_TLL_BIT (1 << 5) | 36 | #define MX25_H1_TLL_BIT (1 << 5) |
34 | #define MX25_H1_USBTE_BIT (1 << 4) | 37 | #define MX25_H1_USBTE_BIT (1 << 4) |
38 | #define MX25_H1_OCPOL_BIT (1 << 2) | ||
35 | 39 | ||
36 | int mx25_initialize_usb_hw(int port, unsigned int flags) | 40 | int mx25_initialize_usb_hw(int port, unsigned int flags) |
37 | { | 41 | { |
@@ -41,21 +45,35 @@ int mx25_initialize_usb_hw(int port, unsigned int flags) | |||
41 | 45 | ||
42 | switch (port) { | 46 | switch (port) { |
43 | case 0: /* OTG port */ | 47 | case 0: /* OTG port */ |
44 | v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT); | 48 | v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT | |
49 | MX25_OTG_OCPOL_BIT); | ||
45 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; | 50 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT; |
46 | 51 | ||
47 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 52 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
48 | v |= MX25_OTG_PM_BIT; | 53 | v |= MX25_OTG_PM_BIT; |
49 | 54 | ||
55 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
56 | v |= MX25_OTG_PP_BIT; | ||
57 | |||
58 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
59 | v |= MX25_OTG_OCPOL_BIT; | ||
60 | |||
50 | break; | 61 | break; |
51 | case 1: /* H1 port */ | 62 | case 1: /* H1 port */ |
52 | v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT | | 63 | v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT | |
53 | MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); | 64 | MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT | |
65 | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT); | ||
54 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; | 66 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT; |
55 | 67 | ||
56 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 68 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
57 | v |= MX25_H1_PM_BIT; | 69 | v |= MX25_H1_PM_BIT; |
58 | 70 | ||
71 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
72 | v |= MX25_H1_PP_BIT; | ||
73 | |||
74 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
75 | v |= MX25_H1_OCPOL_BIT; | ||
76 | |||
59 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | 77 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
60 | v |= MX25_H1_TLL_BIT; | 78 | v |= MX25_H1_TLL_BIT; |
61 | 79 | ||
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c index 001ec3971f5d..73574c30cf50 100644 --- a/arch/arm/mach-imx/ehci-imx35.c +++ b/arch/arm/mach-imx/ehci-imx35.c | |||
@@ -24,14 +24,18 @@ | |||
24 | #define MX35_OTG_SIC_SHIFT 29 | 24 | #define MX35_OTG_SIC_SHIFT 29 |
25 | #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) | 25 | #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT) |
26 | #define MX35_OTG_PM_BIT (1 << 24) | 26 | #define MX35_OTG_PM_BIT (1 << 24) |
27 | #define MX35_OTG_PP_BIT (1 << 11) | ||
28 | #define MX35_OTG_OCPOL_BIT (1 << 3) | ||
27 | 29 | ||
28 | #define MX35_H1_SIC_SHIFT 21 | 30 | #define MX35_H1_SIC_SHIFT 21 |
29 | #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) | 31 | #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) |
32 | #define MX35_H1_PP_BIT (1 << 18) | ||
30 | #define MX35_H1_PM_BIT (1 << 8) | 33 | #define MX35_H1_PM_BIT (1 << 8) |
31 | #define MX35_H1_IPPUE_UP_BIT (1 << 7) | 34 | #define MX35_H1_IPPUE_UP_BIT (1 << 7) |
32 | #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) | 35 | #define MX35_H1_IPPUE_DOWN_BIT (1 << 6) |
33 | #define MX35_H1_TLL_BIT (1 << 5) | 36 | #define MX35_H1_TLL_BIT (1 << 5) |
34 | #define MX35_H1_USBTE_BIT (1 << 4) | 37 | #define MX35_H1_USBTE_BIT (1 << 4) |
38 | #define MX35_H1_OCPOL_BIT (1 << 2) | ||
35 | 39 | ||
36 | int mx35_initialize_usb_hw(int port, unsigned int flags) | 40 | int mx35_initialize_usb_hw(int port, unsigned int flags) |
37 | { | 41 | { |
@@ -41,21 +45,35 @@ int mx35_initialize_usb_hw(int port, unsigned int flags) | |||
41 | 45 | ||
42 | switch (port) { | 46 | switch (port) { |
43 | case 0: /* OTG port */ | 47 | case 0: /* OTG port */ |
44 | v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT); | 48 | v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT | |
49 | MX35_OTG_OCPOL_BIT); | ||
45 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; | 50 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT; |
46 | 51 | ||
47 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 52 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
48 | v |= MX35_OTG_PM_BIT; | 53 | v |= MX35_OTG_PM_BIT; |
49 | 54 | ||
55 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
56 | v |= MX35_OTG_PP_BIT; | ||
57 | |||
58 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
59 | v |= MX35_OTG_OCPOL_BIT; | ||
60 | |||
50 | break; | 61 | break; |
51 | case 1: /* H1 port */ | 62 | case 1: /* H1 port */ |
52 | v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | | 63 | v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT | |
53 | MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); | 64 | MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT | |
65 | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); | ||
54 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; | 66 | v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT; |
55 | 67 | ||
56 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) | 68 | if (!(flags & MXC_EHCI_POWER_PINS_ENABLED)) |
57 | v |= MX35_H1_PM_BIT; | 69 | v |= MX35_H1_PM_BIT; |
58 | 70 | ||
71 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
72 | v |= MX35_H1_PP_BIT; | ||
73 | |||
74 | if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)) | ||
75 | v |= MX35_H1_OCPOL_BIT; | ||
76 | |||
59 | if (!(flags & MXC_EHCI_TTL_ENABLED)) | 77 | if (!(flags & MXC_EHCI_TTL_ENABLED)) |
60 | v |= MX35_H1_TLL_BIT; | 78 | v |= MX35_H1_TLL_BIT; |
61 | 79 | ||
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c index c17fa131728b..49e3b342758a 100644 --- a/arch/arm/mach-imx/ehci-imx5.c +++ b/arch/arm/mach-imx/ehci-imx5.c | |||
@@ -28,11 +28,14 @@ | |||
28 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ | 28 | #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ |
29 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ | 29 | #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ |
30 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ | 30 | #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ |
31 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ | 31 | #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ |
32 | 32 | ||
33 | /* USB_PHY_CTRL_FUNC */ | 33 | /* USB_PHY_CTRL_FUNC */ |
34 | #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ | ||
34 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ | 35 | #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ |
36 | #define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ | ||
35 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ | 37 | #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ |
38 | #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ | ||
36 | 39 | ||
37 | /* USBH2CTRL */ | 40 | /* USBH2CTRL */ |
38 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) | 41 | #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) |
@@ -80,6 +83,10 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
80 | if (flags & MXC_EHCI_INTERNAL_PHY) { | 83 | if (flags & MXC_EHCI_INTERNAL_PHY) { |
81 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 84 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
82 | 85 | ||
86 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
87 | v |= MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
88 | else | ||
89 | v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; | ||
83 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { | 90 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) { |
84 | /* OC/USBPWR is not used */ | 91 | /* OC/USBPWR is not used */ |
85 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; | 92 | v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; |
@@ -87,6 +94,10 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
87 | /* OC/USBPWR is used */ | 94 | /* OC/USBPWR is used */ |
88 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; | 95 | v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; |
89 | } | 96 | } |
97 | if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) | ||
98 | v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
99 | else | ||
100 | v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; | ||
90 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 101 | __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
91 | 102 | ||
92 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); | 103 | v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); |
@@ -119,6 +130,10 @@ int mx51_initialize_usb_hw(int port, unsigned int flags) | |||
119 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); | 130 | __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); |
120 | 131 | ||
121 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); | 132 | v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); |
133 | if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) | ||
134 | v |= MXC_H1_OC_POL_BIT; | ||
135 | else | ||
136 | v &= ~MXC_H1_OC_POL_BIT; | ||
122 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) | 137 | if (flags & MXC_EHCI_POWER_PINS_ENABLED) |
123 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ | 138 | v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ |
124 | else | 139 | else |
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h index 9ffd1bbe615f..7eb9d1329671 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h +++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h | |||
@@ -20,13 +20,15 @@ | |||
20 | #define MXC_EHCI_INTERFACE_MASK (0xf) | 20 | #define MXC_EHCI_INTERFACE_MASK (0xf) |
21 | 21 | ||
22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) | 22 | #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) |
23 | #define MXC_EHCI_TTL_ENABLED (1 << 6) | 23 | #define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) |
24 | 24 | #define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) | |
25 | #define MXC_EHCI_INTERNAL_PHY (1 << 7) | 25 | #define MXC_EHCI_TTL_ENABLED (1 << 8) |
26 | #define MXC_EHCI_IPPUE_DOWN (1 << 8) | 26 | |
27 | #define MXC_EHCI_IPPUE_UP (1 << 9) | 27 | #define MXC_EHCI_INTERNAL_PHY (1 << 9) |
28 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 10) | 28 | #define MXC_EHCI_IPPUE_DOWN (1 << 10) |
29 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 11) | 29 | #define MXC_EHCI_IPPUE_UP (1 << 11) |
30 | #define MXC_EHCI_WAKEUP_ENABLED (1 << 12) | ||
31 | #define MXC_EHCI_ITC_NO_THRESHOLD (1 << 13) | ||
30 | 32 | ||
31 | #define MXC_USBCTRL_OFFSET 0 | 33 | #define MXC_USBCTRL_OFFSET 0 |
32 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 | 34 | #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 |