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-rw-r--r--arch/microblaze/Kconfig7
-rw-r--r--arch/microblaze/include/asm/clinkage.h1
-rw-r--r--arch/microblaze/include/asm/io.h94
-rw-r--r--arch/microblaze/include/asm/page.h9
-rw-r--r--arch/microblaze/include/asm/pci.h2
-rw-r--r--arch/microblaze/include/asm/pgtable.h6
-rw-r--r--arch/microblaze/kernel/head.S14
-rw-r--r--arch/microblaze/kernel/hw_exception_handler.S61
-rw-r--r--arch/microblaze/kernel/reset.c21
-rw-r--r--arch/microblaze/kernel/setup.c15
-rw-r--r--arch/microblaze/kernel/signal.c8
-rw-r--r--arch/microblaze/kernel/timer.c24
12 files changed, 182 insertions, 80 deletions
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index ab9afcaa7f6a..6133bed2b855 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -243,14 +243,11 @@ choice
243config MICROBLAZE_4K_PAGES 243config MICROBLAZE_4K_PAGES
244 bool "4k page size" 244 bool "4k page size"
245 245
246config MICROBLAZE_8K_PAGES
247 bool "8k page size"
248
249config MICROBLAZE_16K_PAGES 246config MICROBLAZE_16K_PAGES
250 bool "16k page size" 247 bool "16k page size"
251 248
252config MICROBLAZE_32K_PAGES 249config MICROBLAZE_64K_PAGES
253 bool "32k page size" 250 bool "64k page size"
254 251
255endchoice 252endchoice
256 253
diff --git a/arch/microblaze/include/asm/clinkage.h b/arch/microblaze/include/asm/clinkage.h
deleted file mode 100644
index 9e218435a55c..000000000000
--- a/arch/microblaze/include/asm/clinkage.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <linux/linkage.h>
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 8cdac14b55b0..4fbfdc1ac7f8 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -35,6 +35,10 @@ extern resource_size_t isa_mem_base;
35 35
36#define IO_SPACE_LIMIT (0xFFFFFFFF) 36#define IO_SPACE_LIMIT (0xFFFFFFFF)
37 37
38/* the following is needed to support PCI with some drivers */
39
40#define mmiowb()
41
38static inline unsigned char __raw_readb(const volatile void __iomem *addr) 42static inline unsigned char __raw_readb(const volatile void __iomem *addr)
39{ 43{
40 return *(volatile unsigned char __force *)addr; 44 return *(volatile unsigned char __force *)addr;
@@ -248,4 +252,94 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
248#define ioport_map(port, nr) ((void __iomem *)(port)) 252#define ioport_map(port, nr) ((void __iomem *)(port))
249#define ioport_unmap(addr) 253#define ioport_unmap(addr)
250 254
255/* from asm-generic/io.h */
256#ifndef insb
257static inline void insb(unsigned long addr, void *buffer, int count)
258{
259 if (count) {
260 u8 *buf = buffer;
261 do {
262 u8 x = inb(addr);
263 *buf++ = x;
264 } while (--count);
265 }
266}
267#endif
268
269#ifndef insw
270static inline void insw(unsigned long addr, void *buffer, int count)
271{
272 if (count) {
273 u16 *buf = buffer;
274 do {
275 u16 x = inw(addr);
276 *buf++ = x;
277 } while (--count);
278 }
279}
280#endif
281
282#ifndef insl
283static inline void insl(unsigned long addr, void *buffer, int count)
284{
285 if (count) {
286 u32 *buf = buffer;
287 do {
288 u32 x = inl(addr);
289 *buf++ = x;
290 } while (--count);
291 }
292}
293#endif
294
295#ifndef outsb
296static inline void outsb(unsigned long addr, const void *buffer, int count)
297{
298 if (count) {
299 const u8 *buf = buffer;
300 do {
301 outb(*buf++, addr);
302 } while (--count);
303 }
304}
305#endif
306
307#ifndef outsw
308static inline void outsw(unsigned long addr, const void *buffer, int count)
309{
310 if (count) {
311 const u16 *buf = buffer;
312 do {
313 outw(*buf++, addr);
314 } while (--count);
315 }
316}
317#endif
318
319#ifndef outsl
320static inline void outsl(unsigned long addr, const void *buffer, int count)
321{
322 if (count) {
323 const u32 *buf = buffer;
324 do {
325 outl(*buf++, addr);
326 } while (--count);
327 }
328}
329#endif
330
331#define ioread8_rep(p, dst, count) \
332 insb((unsigned long) (p), (dst), (count))
333#define ioread16_rep(p, dst, count) \
334 insw((unsigned long) (p), (dst), (count))
335#define ioread32_rep(p, dst, count) \
336 insl((unsigned long) (p), (dst), (count))
337
338#define iowrite8_rep(p, src, count) \
339 outsb((unsigned long) (p), (src), (count))
340#define iowrite16_rep(p, src, count) \
341 outsw((unsigned long) (p), (src), (count))
342#define iowrite32_rep(p, src, count) \
343 outsl((unsigned long) (p), (src), (count))
344
251#endif /* _ASM_MICROBLAZE_IO_H */ 345#endif /* _ASM_MICROBLAZE_IO_H */
diff --git a/arch/microblaze/include/asm/page.h b/arch/microblaze/include/asm/page.h
index 287c5485d286..85a5ae8e9bd0 100644
--- a/arch/microblaze/include/asm/page.h
+++ b/arch/microblaze/include/asm/page.h
@@ -23,12 +23,10 @@
23#ifdef __KERNEL__ 23#ifdef __KERNEL__
24 24
25/* PAGE_SHIFT determines the page size */ 25/* PAGE_SHIFT determines the page size */
26#if defined(CONFIG_MICROBLAZE_32K_PAGES) 26#if defined(CONFIG_MICROBLAZE_64K_PAGES)
27#define PAGE_SHIFT 15 27#define PAGE_SHIFT 16
28#elif defined(CONFIG_MICROBLAZE_16K_PAGES) 28#elif defined(CONFIG_MICROBLAZE_16K_PAGES)
29#define PAGE_SHIFT 14 29#define PAGE_SHIFT 14
30#elif defined(CONFIG_MICROBLAZE_8K_PAGES)
31#define PAGE_SHIFT 13
32#else 30#else
33#define PAGE_SHIFT 12 31#define PAGE_SHIFT 12
34#endif 32#endif
@@ -37,6 +35,8 @@
37 35
38#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR)) 36#define LOAD_OFFSET ASM_CONST((CONFIG_KERNEL_START-CONFIG_KERNEL_BASE_ADDR))
39 37
38#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
39
40#ifndef __ASSEMBLY__ 40#ifndef __ASSEMBLY__
41 41
42/* MS be sure that SLAB allocates aligned objects */ 42/* MS be sure that SLAB allocates aligned objects */
@@ -71,7 +71,6 @@ extern unsigned int __page_offset;
71 * The basic type of a PTE - 32 bit physical addressing. 71 * The basic type of a PTE - 32 bit physical addressing.
72 */ 72 */
73typedef unsigned long pte_basic_t; 73typedef unsigned long pte_basic_t;
74#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
75#define PTE_FMT "%.8lx" 74#define PTE_FMT "%.8lx"
76 75
77#endif /* CONFIG_MMU */ 76#endif /* CONFIG_MMU */
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index a0da88bf70c5..41cc841091b0 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -22,6 +22,8 @@
22#include <asm/prom.h> 22#include <asm/prom.h>
23#include <asm/pci-bridge.h> 23#include <asm/pci-bridge.h>
24 24
25#include <asm-generic/pci-dma-compat.h>
26
25#define PCIBIOS_MIN_IO 0x1000 27#define PCIBIOS_MIN_IO 0x1000
26#define PCIBIOS_MIN_MEM 0x10000000 28#define PCIBIOS_MIN_MEM 0x10000000
27 29
diff --git a/arch/microblaze/include/asm/pgtable.h b/arch/microblaze/include/asm/pgtable.h
index 3ef7b9cafeca..a7311cd9dee0 100644
--- a/arch/microblaze/include/asm/pgtable.h
+++ b/arch/microblaze/include/asm/pgtable.h
@@ -234,12 +234,6 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
234#ifndef _PAGE_SHARED 234#ifndef _PAGE_SHARED
235#define _PAGE_SHARED 0 235#define _PAGE_SHARED 0
236#endif 236#endif
237#ifndef _PAGE_HWWRITE
238#define _PAGE_HWWRITE 0
239#endif
240#ifndef _PAGE_HWEXEC
241#define _PAGE_HWEXEC 0
242#endif
243#ifndef _PAGE_EXEC 237#ifndef _PAGE_EXEC
244#define _PAGE_EXEC 0 238#define _PAGE_EXEC 0
245#endif 239#endif
diff --git a/arch/microblaze/kernel/head.S b/arch/microblaze/kernel/head.S
index 98b17f9f904b..eef84de5e8c8 100644
--- a/arch/microblaze/kernel/head.S
+++ b/arch/microblaze/kernel/head.S
@@ -109,20 +109,24 @@ no_fdt_arg:
109#ifndef CONFIG_CMDLINE_BOOL 109#ifndef CONFIG_CMDLINE_BOOL
110/* 110/*
111 * handling command line 111 * handling command line
112 * copy command line to __init_end. There is space for storing command line. 112 * copy command line directly to cmd_line placed in data section.
113 */ 113 */
114 beqid r5, skip /* Skip if NULL pointer */
114 or r6, r0, r0 /* incremment */ 115 or r6, r0, r0 /* incremment */
115 ori r4, r0, __init_end /* load address of command line */ 116 ori r4, r0, cmd_line /* load address of command line */
116 tophys(r4,r4) /* convert to phys address */ 117 tophys(r4,r4) /* convert to phys address */
117 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */ 118 ori r3, r0, COMMAND_LINE_SIZE - 1 /* number of loops */
118_copy_command_line: 119_copy_command_line:
119 lbu r2, r5, r6 /* r2=r5+r6 - r5 contain pointer to command line */ 120 /* r2=r5+r6 - r5 contain pointer to command line */
120 sb r2, r4, r6 /* addr[r4+r6]= r2*/ 121 lbu r2, r5, r6
122 beqid r2, skip /* Skip if no data */
123 sb r2, r4, r6 /* addr[r4+r6]= r2*/
121 addik r6, r6, 1 /* increment counting */ 124 addik r6, r6, 1 /* increment counting */
122 bgtid r3, _copy_command_line /* loop for all entries */ 125 bgtid r3, _copy_command_line /* loop for all entries */
123 addik r3, r3, -1 /* descrement loop */ 126 addik r3, r3, -1 /* decrement loop */
124 addik r5, r4, 0 /* add new space for command line */ 127 addik r5, r4, 0 /* add new space for command line */
125 tovirt(r5,r5) 128 tovirt(r5,r5)
129skip:
126#endif /* CONFIG_CMDLINE_BOOL */ 130#endif /* CONFIG_CMDLINE_BOOL */
127 131
128#ifdef NOT_COMPILE 132#ifdef NOT_COMPILE
diff --git a/arch/microblaze/kernel/hw_exception_handler.S b/arch/microblaze/kernel/hw_exception_handler.S
index aa510f450ac6..61b3a1fed46f 100644
--- a/arch/microblaze/kernel/hw_exception_handler.S
+++ b/arch/microblaze/kernel/hw_exception_handler.S
@@ -75,6 +75,7 @@
75#include <asm/mmu.h> 75#include <asm/mmu.h>
76#include <asm/pgtable.h> 76#include <asm/pgtable.h>
77#include <asm/signal.h> 77#include <asm/signal.h>
78#include <asm/registers.h>
78#include <asm/asm-offsets.h> 79#include <asm/asm-offsets.h>
79 80
80#undef DEBUG 81#undef DEBUG
@@ -581,7 +582,7 @@ ex_handler_done:
581 * tried to access a kernel or read-protected page - always 582 * tried to access a kernel or read-protected page - always
582 * a SEGV). All other faults here must be stores, so no 583 * a SEGV). All other faults here must be stores, so no
583 * need to check ESR_S as well. */ 584 * need to check ESR_S as well. */
584 andi r4, r4, 0x800 /* ESR_Z - zone protection */ 585 andi r4, r4, ESR_DIZ /* ESR_Z - zone protection */
585 bnei r4, ex2 586 bnei r4, ex2
586 587
587 ori r4, r0, swapper_pg_dir 588 ori r4, r0, swapper_pg_dir
@@ -595,25 +596,25 @@ ex_handler_done:
595 * tried to access a kernel or read-protected page - always 596 * tried to access a kernel or read-protected page - always
596 * a SEGV). All other faults here must be stores, so no 597 * a SEGV). All other faults here must be stores, so no
597 * need to check ESR_S as well. */ 598 * need to check ESR_S as well. */
598 andi r4, r4, 0x800 /* ESR_Z */ 599 andi r4, r4, ESR_DIZ /* ESR_Z */
599 bnei r4, ex2 600 bnei r4, ex2
600 /* get current task address */ 601 /* get current task address */
601 addi r4 ,CURRENT_TASK, TOPHYS(0); 602 addi r4 ,CURRENT_TASK, TOPHYS(0);
602 lwi r4, r4, TASK_THREAD+PGDIR 603 lwi r4, r4, TASK_THREAD+PGDIR
603 ex4: 604 ex4:
604 tophys(r4,r4) 605 tophys(r4,r4)
605 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 606 /* Create L1 (pgdir/pmd) address */
606 andi r5, r5, 0xffc 607 BSRLI(r5,r3, PGDIR_SHIFT - 2)
608 andi r5, r5, PAGE_SIZE - 4
607/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 609/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
608 or r4, r4, r5 610 or r4, r4, r5
609 lwi r4, r4, 0 /* Get L1 entry */ 611 lwi r4, r4, 0 /* Get L1 entry */
610 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 612 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
611 beqi r5, ex2 /* Bail if no table */ 613 beqi r5, ex2 /* Bail if no table */
612 614
613 tophys(r5,r5) 615 tophys(r5,r5)
614 BSRLI(r6,r3,10) /* Compute PTE address */ 616 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
615 andi r6, r6, 0xffc 617 andi r6, r6, PAGE_SIZE - 4
616 andi r5, r5, 0xfffff003
617 or r5, r5, r6 618 or r5, r5, r6
618 lwi r4, r5, 0 /* Get Linux PTE */ 619 lwi r4, r5, 0 /* Get Linux PTE */
619 620
@@ -632,7 +633,9 @@ ex_handler_done:
632 * Many of these bits are software only. Bits we don't set 633 * Many of these bits are software only. Bits we don't set
633 * here we (properly should) assume have the appropriate value. 634 * here we (properly should) assume have the appropriate value.
634 */ 635 */
635 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 636/* Ignore memory coherent, just LSB on ZSEL is used + EX/WR */
637 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
638 TLB_ZSEL(1) | TLB_ATTR_MASK
636 ori r4, r4, _PAGE_HWEXEC /* make it executable */ 639 ori r4, r4, _PAGE_HWEXEC /* make it executable */
637 640
638 /* find the TLB index that caused the fault. It has to be here*/ 641 /* find the TLB index that caused the fault. It has to be here*/
@@ -701,18 +704,18 @@ ex_handler_done:
701 lwi r4, r4, TASK_THREAD+PGDIR 704 lwi r4, r4, TASK_THREAD+PGDIR
702 ex6: 705 ex6:
703 tophys(r4,r4) 706 tophys(r4,r4)
704 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 707 /* Create L1 (pgdir/pmd) address */
705 andi r5, r5, 0xffc 708 BSRLI(r5,r3, PGDIR_SHIFT - 2)
709 andi r5, r5, PAGE_SIZE - 4
706/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 710/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
707 or r4, r4, r5 711 or r4, r4, r5
708 lwi r4, r4, 0 /* Get L1 entry */ 712 lwi r4, r4, 0 /* Get L1 entry */
709 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 713 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
710 beqi r5, ex7 /* Bail if no table */ 714 beqi r5, ex7 /* Bail if no table */
711 715
712 tophys(r5,r5) 716 tophys(r5,r5)
713 BSRLI(r6,r3,10) /* Compute PTE address */ 717 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
714 andi r6, r6, 0xffc 718 andi r6, r6, PAGE_SIZE - 4
715 andi r5, r5, 0xfffff003
716 or r5, r5, r6 719 or r5, r5, r6
717 lwi r4, r5, 0 /* Get Linux PTE */ 720 lwi r4, r5, 0 /* Get Linux PTE */
718 721
@@ -731,7 +734,8 @@ ex_handler_done:
731 * here we (properly should) assume have the appropriate value. 734 * here we (properly should) assume have the appropriate value.
732 */ 735 */
733 brid finish_tlb_load 736 brid finish_tlb_load
734 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 737 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
738 TLB_ZSEL(1) | TLB_ATTR_MASK
735 ex7: 739 ex7:
736 /* The bailout. Restore registers to pre-exception conditions 740 /* The bailout. Restore registers to pre-exception conditions
737 * and call the heavyweights to help us out. 741 * and call the heavyweights to help us out.
@@ -771,18 +775,18 @@ ex_handler_done:
771 lwi r4, r4, TASK_THREAD+PGDIR 775 lwi r4, r4, TASK_THREAD+PGDIR
772 ex9: 776 ex9:
773 tophys(r4,r4) 777 tophys(r4,r4)
774 BSRLI(r5,r3,20) /* Create L1 (pgdir/pmd) address */ 778 /* Create L1 (pgdir/pmd) address */
775 andi r5, r5, 0xffc 779 BSRLI(r5,r3, PGDIR_SHIFT - 2)
780 andi r5, r5, PAGE_SIZE - 4
776/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */ 781/* Assume pgdir aligned on 4K boundary, no need for "andi r4,r4,0xfffff003" */
777 or r4, r4, r5 782 or r4, r4, r5
778 lwi r4, r4, 0 /* Get L1 entry */ 783 lwi r4, r4, 0 /* Get L1 entry */
779 andi r5, r4, 0xfffff000 /* Extract L2 (pte) base address */ 784 andi r5, r4, PAGE_MASK /* Extract L2 (pte) base address */
780 beqi r5, ex10 /* Bail if no table */ 785 beqi r5, ex10 /* Bail if no table */
781 786
782 tophys(r5,r5) 787 tophys(r5,r5)
783 BSRLI(r6,r3,10) /* Compute PTE address */ 788 BSRLI(r6,r3,PTE_SHIFT) /* Compute PTE address */
784 andi r6, r6, 0xffc 789 andi r6, r6, PAGE_SIZE - 4
785 andi r5, r5, 0xfffff003
786 or r5, r5, r6 790 or r5, r5, r6
787 lwi r4, r5, 0 /* Get Linux PTE */ 791 lwi r4, r5, 0 /* Get Linux PTE */
788 792
@@ -801,7 +805,8 @@ ex_handler_done:
801 * here we (properly should) assume have the appropriate value. 805 * here we (properly should) assume have the appropriate value.
802 */ 806 */
803 brid finish_tlb_load 807 brid finish_tlb_load
804 andni r4, r4, 0x0ce2 /* Make sure 20, 21 are zero */ 808 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
809 TLB_ZSEL(1) | TLB_ATTR_MASK
805 ex10: 810 ex10:
806 /* The bailout. Restore registers to pre-exception conditions 811 /* The bailout. Restore registers to pre-exception conditions
807 * and call the heavyweights to help us out. 812 * and call the heavyweights to help us out.
@@ -854,8 +859,14 @@ ex_handler_done:
854 * set of bits. These are size, valid, E, U0, and ensure 859 * set of bits. These are size, valid, E, U0, and ensure
855 * bits 20 and 21 are zero. 860 * bits 20 and 21 are zero.
856 */ 861 */
857 andi r3, r3, 0xfffff000 862 andi r3, r3, PAGE_MASK
858 ori r3, r3, 0x0c0 863#ifdef CONFIG_MICROBLAZE_64K_PAGES
864 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_64K)
865#elif CONFIG_MICROBLAZE_16K_PAGES
866 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_16K)
867#else
868 ori r3, r3, TLB_VALID | TLB_PAGESZ(PAGESZ_4K)
869#endif
859 mts rtlbhi, r3 /* Load TLB HI */ 870 mts rtlbhi, r3 /* Load TLB HI */
860 nop 871 nop
861 872
diff --git a/arch/microblaze/kernel/reset.c b/arch/microblaze/kernel/reset.c
index 88a01636f785..2e5079ab53d2 100644
--- a/arch/microblaze/kernel/reset.c
+++ b/arch/microblaze/kernel/reset.c
@@ -26,13 +26,14 @@ void of_platform_reset_gpio_probe(void)
26 "hard-reset-gpios", 0); 26 "hard-reset-gpios", 0);
27 27
28 if (!gpio_is_valid(handle)) { 28 if (!gpio_is_valid(handle)) {
29 printk(KERN_INFO "Skipping unavailable RESET gpio %d (%s)\n", 29 pr_info("Skipping unavailable RESET gpio %d (%s)\n",
30 handle, "reset"); 30 handle, "reset");
31 return;
31 } 32 }
32 33
33 ret = gpio_request(handle, "reset"); 34 ret = gpio_request(handle, "reset");
34 if (ret < 0) { 35 if (ret < 0) {
35 printk(KERN_INFO "GPIO pin is already allocated\n"); 36 pr_info("GPIO pin is already allocated\n");
36 return; 37 return;
37 } 38 }
38 39
@@ -49,7 +50,7 @@ void of_platform_reset_gpio_probe(void)
49 /* Setup output direction */ 50 /* Setup output direction */
50 gpio_set_value(handle, 0); 51 gpio_set_value(handle, 0);
51 52
52 printk(KERN_INFO "RESET: Registered gpio device: %d, current val: %d\n", 53 pr_info("RESET: Registered gpio device: %d, current val: %d\n",
53 handle, reset_val); 54 handle, reset_val);
54 return; 55 return;
55err: 56err:
@@ -60,7 +61,10 @@ err:
60 61
61static void gpio_system_reset(void) 62static void gpio_system_reset(void)
62{ 63{
63 gpio_set_value(handle, 1 - reset_val); 64 if (gpio_is_valid(handle))
65 gpio_set_value(handle, 1 - reset_val);
66 else
67 pr_notice("Reset GPIO unavailable - halting!\n");
64} 68}
65#else 69#else
66#define gpio_system_reset() do {} while (0) 70#define gpio_system_reset() do {} while (0)
@@ -72,30 +76,29 @@ void of_platform_reset_gpio_probe(void)
72 76
73void machine_restart(char *cmd) 77void machine_restart(char *cmd)
74{ 78{
75 printk(KERN_NOTICE "Machine restart...\n"); 79 pr_notice("Machine restart...\n");
76 gpio_system_reset(); 80 gpio_system_reset();
77 dump_stack();
78 while (1) 81 while (1)
79 ; 82 ;
80} 83}
81 84
82void machine_shutdown(void) 85void machine_shutdown(void)
83{ 86{
84 printk(KERN_NOTICE "Machine shutdown...\n"); 87 pr_notice("Machine shutdown...\n");
85 while (1) 88 while (1)
86 ; 89 ;
87} 90}
88 91
89void machine_halt(void) 92void machine_halt(void)
90{ 93{
91 printk(KERN_NOTICE "Machine halt...\n"); 94 pr_notice("Machine halt...\n");
92 while (1) 95 while (1)
93 ; 96 ;
94} 97}
95 98
96void machine_power_off(void) 99void machine_power_off(void)
97{ 100{
98 printk(KERN_NOTICE "Machine power off...\n"); 101 pr_notice("Machine power off...\n");
99 while (1) 102 while (1)
100 ; 103 ;
101} 104}
diff --git a/arch/microblaze/kernel/setup.c b/arch/microblaze/kernel/setup.c
index 4da971d4392f..954348f83505 100644
--- a/arch/microblaze/kernel/setup.c
+++ b/arch/microblaze/kernel/setup.c
@@ -40,7 +40,12 @@ DEFINE_PER_CPU(unsigned int, R11_SAVE); /* Temp variable for entry */
40DEFINE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */ 40DEFINE_PER_CPU(unsigned int, CURRENT_SAVE); /* Saved current pointer */
41 41
42unsigned int boot_cpuid; 42unsigned int boot_cpuid;
43char cmd_line[COMMAND_LINE_SIZE]; 43/*
44 * Placed cmd_line to .data section because can be initialized from
45 * ASM code. Default position is BSS section which is cleared
46 * in machine_early_init().
47 */
48char cmd_line[COMMAND_LINE_SIZE] __attribute__ ((section(".data")));
44 49
45void __init setup_arch(char **cmdline_p) 50void __init setup_arch(char **cmdline_p)
46{ 51{
@@ -64,7 +69,7 @@ void __init setup_arch(char **cmdline_p)
64 xilinx_pci_init(); 69 xilinx_pci_init();
65 70
66#if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER) 71#if defined(CONFIG_SELFMOD_INTC) || defined(CONFIG_SELFMOD_TIMER)
67 printk(KERN_NOTICE "Self modified code enable\n"); 72 pr_notice("Self modified code enable\n");
68#endif 73#endif
69 74
70#ifdef CONFIG_VT 75#ifdef CONFIG_VT
@@ -130,12 +135,6 @@ void __init machine_early_init(const char *cmdline, unsigned int ram,
130 memset(__bss_start, 0, __bss_stop-__bss_start); 135 memset(__bss_start, 0, __bss_stop-__bss_start);
131 memset(_ssbss, 0, _esbss-_ssbss); 136 memset(_ssbss, 0, _esbss-_ssbss);
132 137
133 /* Copy command line passed from bootloader */
134#ifndef CONFIG_CMDLINE_BOOL
135 if (cmdline && cmdline[0] != '\0')
136 strlcpy(cmd_line, cmdline, COMMAND_LINE_SIZE);
137#endif
138
139 lockdep_init(); 138 lockdep_init();
140 139
141/* initialize device tree for usage in early_printk */ 140/* initialize device tree for usage in early_printk */
diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c
index 76b9722557db..c1220dbf87cd 100644
--- a/arch/microblaze/kernel/signal.c
+++ b/arch/microblaze/kernel/signal.c
@@ -290,15 +290,7 @@ handle_restart(struct pt_regs *regs, struct k_sigaction *ka, int has_handler)
290 case -ERESTARTNOINTR: 290 case -ERESTARTNOINTR:
291do_restart: 291do_restart:
292 /* offset of 4 bytes to re-execute trap (brki) instruction */ 292 /* offset of 4 bytes to re-execute trap (brki) instruction */
293#ifndef CONFIG_MMU
294 regs->pc -= 4; 293 regs->pc -= 4;
295#else
296 /* offset of 8 bytes required = 4 for rtbd
297 offset, plus 4 for size of
298 "brki r14,8"
299 instruction. */
300 regs->pc -= 8;
301#endif
302 break; 294 break;
303 } 295 }
304} 296}
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index 522defa7d41f..aec5020a6e31 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -116,21 +116,21 @@ static void microblaze_timer_set_mode(enum clock_event_mode mode,
116{ 116{
117 switch (mode) { 117 switch (mode) {
118 case CLOCK_EVT_MODE_PERIODIC: 118 case CLOCK_EVT_MODE_PERIODIC:
119 printk(KERN_INFO "%s: periodic\n", __func__); 119 pr_info("%s: periodic\n", __func__);
120 microblaze_timer0_start_periodic(freq_div_hz); 120 microblaze_timer0_start_periodic(freq_div_hz);
121 break; 121 break;
122 case CLOCK_EVT_MODE_ONESHOT: 122 case CLOCK_EVT_MODE_ONESHOT:
123 printk(KERN_INFO "%s: oneshot\n", __func__); 123 pr_info("%s: oneshot\n", __func__);
124 break; 124 break;
125 case CLOCK_EVT_MODE_UNUSED: 125 case CLOCK_EVT_MODE_UNUSED:
126 printk(KERN_INFO "%s: unused\n", __func__); 126 pr_info("%s: unused\n", __func__);
127 break; 127 break;
128 case CLOCK_EVT_MODE_SHUTDOWN: 128 case CLOCK_EVT_MODE_SHUTDOWN:
129 printk(KERN_INFO "%s: shutdown\n", __func__); 129 pr_info("%s: shutdown\n", __func__);
130 microblaze_timer0_stop(); 130 microblaze_timer0_stop();
131 break; 131 break;
132 case CLOCK_EVT_MODE_RESUME: 132 case CLOCK_EVT_MODE_RESUME:
133 printk(KERN_INFO "%s: resume\n", __func__); 133 pr_info("%s: resume\n", __func__);
134 break; 134 break;
135 } 135 }
136} 136}
@@ -257,7 +257,15 @@ void __init time_init(void)
257 0 257 0
258 }; 258 };
259#endif 259#endif
260 timer = of_find_compatible_node(NULL, NULL, "xlnx,xps-timer-1.00.a"); 260 prop = of_get_property(of_chosen, "system-timer", NULL);
261 if (prop)
262 timer = of_find_node_by_phandle(be32_to_cpup(prop));
263 else
264 pr_info("No chosen timer found, using default\n");
265
266 if (!timer)
267 timer = of_find_compatible_node(NULL, NULL,
268 "xlnx,xps-timer-1.00.a");
261 BUG_ON(!timer); 269 BUG_ON(!timer);
262 270
263 timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL)); 271 timer_baseaddr = be32_to_cpup(of_get_property(timer, "reg", NULL));
@@ -266,14 +274,14 @@ void __init time_init(void)
266 timer_num = be32_to_cpup(of_get_property(timer, 274 timer_num = be32_to_cpup(of_get_property(timer,
267 "xlnx,one-timer-only", NULL)); 275 "xlnx,one-timer-only", NULL));
268 if (timer_num) { 276 if (timer_num) {
269 printk(KERN_EMERG "Please enable two timers in HW\n"); 277 pr_emerg("Please enable two timers in HW\n");
270 BUG(); 278 BUG();
271 } 279 }
272 280
273#ifdef CONFIG_SELFMOD_TIMER 281#ifdef CONFIG_SELFMOD_TIMER
274 selfmod_function((int *) arr_func, timer_baseaddr); 282 selfmod_function((int *) arr_func, timer_baseaddr);
275#endif 283#endif
276 printk(KERN_INFO "%s #0 at 0x%08x, irq=%d\n", 284 pr_info("%s #0 at 0x%08x, irq=%d\n",
277 timer->name, timer_baseaddr, irq); 285 timer->name, timer_baseaddr, irq);
278 286
279 /* If there is clock-frequency property than use it */ 287 /* If there is clock-frequency property than use it */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 00:00:48 -0500