diff options
| -rw-r--r-- | drivers/dma/shdma.c | 35 | ||||
| -rw-r--r-- | drivers/dma/shdma.h | 1 | ||||
| -rw-r--r-- | include/linux/sh_dma.h | 1 |
3 files changed, 29 insertions, 8 deletions
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c index 41a21b322960..40900c1cee9a 100644 --- a/drivers/dma/shdma.c +++ b/drivers/dma/shdma.c | |||
| @@ -78,6 +78,20 @@ static void dmaor_write(struct sh_dmae_device *shdev, u16 data) | |||
| 78 | __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); | 78 | __raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32)); |
| 79 | } | 79 | } |
| 80 | 80 | ||
| 81 | static void chcr_write(struct sh_dmae_chan *sh_dc, u32 data) | ||
| 82 | { | ||
| 83 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | ||
| 84 | |||
| 85 | __raw_writel(data, sh_dc->base + shdev->chcr_offset / sizeof(u32)); | ||
| 86 | } | ||
| 87 | |||
| 88 | static u32 chcr_read(struct sh_dmae_chan *sh_dc) | ||
| 89 | { | ||
| 90 | struct sh_dmae_device *shdev = to_sh_dev(sh_dc); | ||
| 91 | |||
| 92 | return __raw_readl(sh_dc->base + shdev->chcr_offset / sizeof(u32)); | ||
| 93 | } | ||
| 94 | |||
| 81 | /* | 95 | /* |
| 82 | * Reset DMA controller | 96 | * Reset DMA controller |
| 83 | * | 97 | * |
| @@ -120,7 +134,7 @@ static int sh_dmae_rst(struct sh_dmae_device *shdev) | |||
| 120 | 134 | ||
| 121 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) | 135 | static bool dmae_is_busy(struct sh_dmae_chan *sh_chan) |
| 122 | { | 136 | { |
| 123 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | 137 | u32 chcr = chcr_read(sh_chan); |
| 124 | 138 | ||
| 125 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) | 139 | if ((chcr & (CHCR_DE | CHCR_TE)) == CHCR_DE) |
| 126 | return true; /* working */ | 140 | return true; /* working */ |
| @@ -167,18 +181,18 @@ static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw) | |||
| 167 | 181 | ||
| 168 | static void dmae_start(struct sh_dmae_chan *sh_chan) | 182 | static void dmae_start(struct sh_dmae_chan *sh_chan) |
| 169 | { | 183 | { |
| 170 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | 184 | u32 chcr = chcr_read(sh_chan); |
| 171 | 185 | ||
| 172 | chcr |= CHCR_DE | CHCR_IE; | 186 | chcr |= CHCR_DE | CHCR_IE; |
| 173 | sh_dmae_writel(sh_chan, chcr & ~CHCR_TE, CHCR); | 187 | chcr_write(sh_chan, chcr & ~CHCR_TE); |
| 174 | } | 188 | } |
| 175 | 189 | ||
| 176 | static void dmae_halt(struct sh_dmae_chan *sh_chan) | 190 | static void dmae_halt(struct sh_dmae_chan *sh_chan) |
| 177 | { | 191 | { |
| 178 | u32 chcr = sh_dmae_readl(sh_chan, CHCR); | 192 | u32 chcr = chcr_read(sh_chan); |
| 179 | 193 | ||
| 180 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); | 194 | chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); |
| 181 | sh_dmae_writel(sh_chan, chcr, CHCR); | 195 | chcr_write(sh_chan, chcr); |
| 182 | } | 196 | } |
| 183 | 197 | ||
| 184 | static void dmae_init(struct sh_dmae_chan *sh_chan) | 198 | static void dmae_init(struct sh_dmae_chan *sh_chan) |
| @@ -190,7 +204,7 @@ static void dmae_init(struct sh_dmae_chan *sh_chan) | |||
| 190 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, | 204 | u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan, |
| 191 | LOG2_DEFAULT_XFER_SIZE); | 205 | LOG2_DEFAULT_XFER_SIZE); |
| 192 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); | 206 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr); |
| 193 | sh_dmae_writel(sh_chan, chcr, CHCR); | 207 | chcr_write(sh_chan, chcr); |
| 194 | } | 208 | } |
| 195 | 209 | ||
| 196 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) | 210 | static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) |
| @@ -200,7 +214,7 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val) | |||
| 200 | return -EBUSY; | 214 | return -EBUSY; |
| 201 | 215 | ||
| 202 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); | 216 | sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val); |
| 203 | sh_dmae_writel(sh_chan, val, CHCR); | 217 | chcr_write(sh_chan, val); |
| 204 | 218 | ||
| 205 | return 0; | 219 | return 0; |
| 206 | } | 220 | } |
| @@ -840,7 +854,7 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data) | |||
| 840 | 854 | ||
| 841 | spin_lock(&sh_chan->desc_lock); | 855 | spin_lock(&sh_chan->desc_lock); |
| 842 | 856 | ||
| 843 | chcr = sh_dmae_readl(sh_chan, CHCR); | 857 | chcr = chcr_read(sh_chan); |
| 844 | 858 | ||
| 845 | if (chcr & CHCR_TE) { | 859 | if (chcr & CHCR_TE) { |
| 846 | /* DMA stop */ | 860 | /* DMA stop */ |
| @@ -1138,6 +1152,11 @@ static int __init sh_dmae_probe(struct platform_device *pdev) | |||
| 1138 | /* platform data */ | 1152 | /* platform data */ |
| 1139 | shdev->pdata = pdata; | 1153 | shdev->pdata = pdata; |
| 1140 | 1154 | ||
| 1155 | if (pdata->chcr_offset) | ||
| 1156 | shdev->chcr_offset = pdata->chcr_offset; | ||
| 1157 | else | ||
| 1158 | shdev->chcr_offset = CHCR; | ||
| 1159 | |||
| 1141 | platform_set_drvdata(pdev, shdev); | 1160 | platform_set_drvdata(pdev, shdev); |
| 1142 | 1161 | ||
| 1143 | pm_runtime_enable(&pdev->dev); | 1162 | pm_runtime_enable(&pdev->dev); |
diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h index 6c73b654a5c3..6f064cad6c0f 100644 --- a/drivers/dma/shdma.h +++ b/drivers/dma/shdma.h | |||
| @@ -47,6 +47,7 @@ struct sh_dmae_device { | |||
| 47 | struct list_head node; | 47 | struct list_head node; |
| 48 | u32 __iomem *chan_reg; | 48 | u32 __iomem *chan_reg; |
| 49 | u16 __iomem *dmars; | 49 | u16 __iomem *dmars; |
| 50 | unsigned int chcr_offset; | ||
| 50 | }; | 51 | }; |
| 51 | 52 | ||
| 52 | #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common) | 53 | #define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common) |
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h index b08cd4efa15c..41fe4c2d6481 100644 --- a/include/linux/sh_dma.h +++ b/include/linux/sh_dma.h | |||
| @@ -62,6 +62,7 @@ struct sh_dmae_pdata { | |||
| 62 | const unsigned int *ts_shift; | 62 | const unsigned int *ts_shift; |
| 63 | int ts_shift_num; | 63 | int ts_shift_num; |
| 64 | u16 dmaor_init; | 64 | u16 dmaor_init; |
| 65 | unsigned int chcr_offset; | ||
| 65 | }; | 66 | }; |
| 66 | 67 | ||
| 67 | /* DMA register */ | 68 | /* DMA register */ |
