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-rw-r--r--drivers/gpu/drm/i915/i915_dma.c32
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c54
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h836
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c73
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1405
5 files changed, 1508 insertions, 892 deletions
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 28c812a0c634..4d56dfd25e04 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -40,11 +40,11 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
40{ 40{
41 drm_i915_private_t *dev_priv = dev->dev_private; 41 drm_i915_private_t *dev_priv = dev->dev_private;
42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 43 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
44 int i; 44 int i;
45 45
46 for (i = 0; i < 10000; i++) { 46 for (i = 0; i < 10000; i++) {
47 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 47 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
48 ring->space = ring->head - (ring->tail + 8); 48 ring->space = ring->head - (ring->tail + 8);
49 if (ring->space < 0) 49 if (ring->space < 0)
50 ring->space += ring->Size; 50 ring->space += ring->Size;
@@ -67,8 +67,8 @@ void i915_kernel_lost_context(struct drm_device * dev)
67 drm_i915_private_t *dev_priv = dev->dev_private; 67 drm_i915_private_t *dev_priv = dev->dev_private;
68 drm_i915_ring_buffer_t *ring = &(dev_priv->ring); 68 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
69 69
70 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR; 70 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
71 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR; 71 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
72 ring->space = ring->head - (ring->tail + 8); 72 ring->space = ring->head - (ring->tail + 8);
73 if (ring->space < 0) 73 if (ring->space < 0)
74 ring->space += ring->Size; 74 ring->space += ring->Size;
@@ -98,13 +98,13 @@ static int i915_dma_cleanup(struct drm_device * dev)
98 drm_pci_free(dev, dev_priv->status_page_dmah); 98 drm_pci_free(dev, dev_priv->status_page_dmah);
99 dev_priv->status_page_dmah = NULL; 99 dev_priv->status_page_dmah = NULL;
100 /* Need to rewrite hardware status page */ 100 /* Need to rewrite hardware status page */
101 I915_WRITE(0x02080, 0x1ffff000); 101 I915_WRITE(HWS_PGA, 0x1ffff000);
102 } 102 }
103 103
104 if (dev_priv->status_gfx_addr) { 104 if (dev_priv->status_gfx_addr) {
105 dev_priv->status_gfx_addr = 0; 105 dev_priv->status_gfx_addr = 0;
106 drm_core_ioremapfree(&dev_priv->hws_map, dev); 106 drm_core_ioremapfree(&dev_priv->hws_map, dev);
107 I915_WRITE(0x2080, 0x1ffff000); 107 I915_WRITE(HWS_PGA, 0x1ffff000);
108 } 108 }
109 109
110 return 0; 110 return 0;
@@ -170,7 +170,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
170 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr; 170 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
171 171
172 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 172 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
173 I915_WRITE(0x02080, dev_priv->dma_status_page); 173 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
174 } 174 }
175 DRM_DEBUG("Enabled hardware status page\n"); 175 DRM_DEBUG("Enabled hardware status page\n");
176 return 0; 176 return 0;
@@ -201,9 +201,9 @@ static int i915_dma_resume(struct drm_device * dev)
201 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page); 201 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
202 202
203 if (dev_priv->status_gfx_addr != 0) 203 if (dev_priv->status_gfx_addr != 0)
204 I915_WRITE(0x02080, dev_priv->status_gfx_addr); 204 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
205 else 205 else
206 I915_WRITE(0x02080, dev_priv->dma_status_page); 206 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
207 DRM_DEBUG("Enabled hardware status page\n"); 207 DRM_DEBUG("Enabled hardware status page\n");
208 208
209 return 0; 209 return 0;
@@ -402,8 +402,8 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
402 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; 402 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
403 403
404 BEGIN_LP_RING(4); 404 BEGIN_LP_RING(4);
405 OUT_RING(CMD_STORE_DWORD_IDX); 405 OUT_RING(MI_STORE_DWORD_INDEX);
406 OUT_RING(20); 406 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
407 OUT_RING(dev_priv->counter); 407 OUT_RING(dev_priv->counter);
408 OUT_RING(0); 408 OUT_RING(0);
409 ADVANCE_LP_RING(); 409 ADVANCE_LP_RING();
@@ -505,7 +505,7 @@ static int i915_dispatch_flip(struct drm_device * dev)
505 i915_kernel_lost_context(dev); 505 i915_kernel_lost_context(dev);
506 506
507 BEGIN_LP_RING(2); 507 BEGIN_LP_RING(2);
508 OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE); 508 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
509 OUT_RING(0); 509 OUT_RING(0);
510 ADVANCE_LP_RING(); 510 ADVANCE_LP_RING();
511 511
@@ -530,8 +530,8 @@ static int i915_dispatch_flip(struct drm_device * dev)
530 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++; 530 dev_priv->sarea_priv->last_enqueue = dev_priv->counter++;
531 531
532 BEGIN_LP_RING(4); 532 BEGIN_LP_RING(4);
533 OUT_RING(CMD_STORE_DWORD_IDX); 533 OUT_RING(MI_STORE_DWORD_INDEX);
534 OUT_RING(20); 534 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
535 OUT_RING(dev_priv->counter); 535 OUT_RING(dev_priv->counter);
536 OUT_RING(0); 536 OUT_RING(0);
537 ADVANCE_LP_RING(); 537 ADVANCE_LP_RING();
@@ -728,8 +728,8 @@ static int i915_set_status_page(struct drm_device *dev, void *data,
728 dev_priv->hw_status_page = dev_priv->hws_map.handle; 728 dev_priv->hw_status_page = dev_priv->hws_map.handle;
729 729
730 memset(dev_priv->hw_status_page, 0, PAGE_SIZE); 730 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
731 I915_WRITE(0x02080, dev_priv->status_gfx_addr); 731 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
732 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n", 732 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
733 dev_priv->status_gfx_addr); 733 dev_priv->status_gfx_addr);
734 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page); 734 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
735 return 0; 735 return 0;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 93aed1c38bd2..6c99aab12da3 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -279,13 +279,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
279 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE); 279 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
280 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE); 280 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
281 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS); 281 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
282 dev_priv->saveDSPABASE = I915_READ(DSPABASE); 282 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
283 if (IS_I965G(dev)) { 283 if (IS_I965G(dev)) {
284 dev_priv->saveDSPASURF = I915_READ(DSPASURF); 284 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
285 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF); 285 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
286 } 286 }
287 i915_save_palette(dev, PIPE_A); 287 i915_save_palette(dev, PIPE_A);
288 dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT); 288 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
289 289
290 /* Pipe & plane B info */ 290 /* Pipe & plane B info */
291 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF); 291 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
@@ -307,13 +307,13 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
307 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE); 307 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
308 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE); 308 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
309 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS); 309 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
310 dev_priv->saveDSPBBASE = I915_READ(DSPBBASE); 310 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
311 if (IS_I965GM(dev) || IS_IGD_GM(dev)) { 311 if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
312 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF); 312 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
313 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF); 313 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
314 } 314 }
315 i915_save_palette(dev, PIPE_B); 315 i915_save_palette(dev, PIPE_B);
316 dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT); 316 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
317 317
318 /* CRT state */ 318 /* CRT state */
319 dev_priv->saveADPA = I915_READ(ADPA); 319 dev_priv->saveADPA = I915_READ(ADPA);
@@ -328,9 +328,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
328 dev_priv->saveLVDS = I915_READ(LVDS); 328 dev_priv->saveLVDS = I915_READ(LVDS);
329 if (!IS_I830(dev) && !IS_845G(dev)) 329 if (!IS_I830(dev) && !IS_845G(dev))
330 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 330 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
331 dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON); 331 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
332 dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF); 332 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
333 dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE); 333 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
334 334
335 /* FIXME: save TV & SDVO state */ 335 /* FIXME: save TV & SDVO state */
336 336
@@ -341,19 +341,19 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
341 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL); 341 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
342 342
343 /* Interrupt state */ 343 /* Interrupt state */
344 dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R); 344 dev_priv->saveIIR = I915_READ(IIR);
345 dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R); 345 dev_priv->saveIER = I915_READ(IER);
346 dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R); 346 dev_priv->saveIMR = I915_READ(IMR);
347 347
348 /* VGA state */ 348 /* VGA state */
349 dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0); 349 dev_priv->saveVGA0 = I915_READ(VGA0);
350 dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1); 350 dev_priv->saveVGA1 = I915_READ(VGA1);
351 dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV); 351 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
352 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL); 352 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
353 353
354 /* Clock gating state */ 354 /* Clock gating state */
355 dev_priv->saveD_STATE = I915_READ(D_STATE); 355 dev_priv->saveD_STATE = I915_READ(D_STATE);
356 dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); 356 dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
357 357
358 /* Cache mode state */ 358 /* Cache mode state */
359 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); 359 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
@@ -363,7 +363,7 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
363 363
364 /* Scratch space */ 364 /* Scratch space */
365 for (i = 0; i < 16; i++) { 365 for (i = 0; i < 16; i++) {
366 dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2)); 366 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
367 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2)); 367 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
368 } 368 }
369 for (i = 0; i < 3; i++) 369 for (i = 0; i < 3; i++)
@@ -424,7 +424,7 @@ static int i915_resume(struct drm_device *dev)
424 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE); 424 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
425 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS); 425 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
426 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC); 426 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
427 I915_WRITE(DSPABASE, dev_priv->saveDSPABASE); 427 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
428 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE); 428 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
429 if (IS_I965G(dev)) { 429 if (IS_I965G(dev)) {
430 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF); 430 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
@@ -436,7 +436,7 @@ static int i915_resume(struct drm_device *dev)
436 i915_restore_palette(dev, PIPE_A); 436 i915_restore_palette(dev, PIPE_A);
437 /* Enable the plane */ 437 /* Enable the plane */
438 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR); 438 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
439 I915_WRITE(DSPABASE, I915_READ(DSPABASE)); 439 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
440 440
441 /* Pipe & plane B info */ 441 /* Pipe & plane B info */
442 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) { 442 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
@@ -466,7 +466,7 @@ static int i915_resume(struct drm_device *dev)
466 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE); 466 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
467 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS); 467 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
468 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC); 468 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
469 I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE); 469 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
470 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE); 470 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
471 if (IS_I965G(dev)) { 471 if (IS_I965G(dev)) {
472 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF); 472 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
@@ -478,7 +478,7 @@ static int i915_resume(struct drm_device *dev)
478 i915_restore_palette(dev, PIPE_B); 478 i915_restore_palette(dev, PIPE_B);
479 /* Enable the plane */ 479 /* Enable the plane */
480 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR); 480 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
481 I915_WRITE(DSPBBASE, I915_READ(DSPBBASE)); 481 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
482 482
483 /* CRT state */ 483 /* CRT state */
484 I915_WRITE(ADPA, dev_priv->saveADPA); 484 I915_WRITE(ADPA, dev_priv->saveADPA);
@@ -493,9 +493,9 @@ static int i915_resume(struct drm_device *dev)
493 493
494 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS); 494 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
495 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL); 495 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
496 I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON); 496 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
497 I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF); 497 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
498 I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE); 498 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
499 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL); 499 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
500 500
501 /* FIXME: restore TV & SDVO state */ 501 /* FIXME: restore TV & SDVO state */
@@ -508,14 +508,14 @@ static int i915_resume(struct drm_device *dev)
508 508
509 /* VGA state */ 509 /* VGA state */
510 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL); 510 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
511 I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0); 511 I915_WRITE(VGA0, dev_priv->saveVGA0);
512 I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1); 512 I915_WRITE(VGA1, dev_priv->saveVGA1);
513 I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV); 513 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
514 udelay(150); 514 udelay(150);
515 515
516 /* Clock gating state */ 516 /* Clock gating state */
517 I915_WRITE (D_STATE, dev_priv->saveD_STATE); 517 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
518 I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D); 518 I915_WRITE(CG_2D_DIS, dev_priv->saveCG_2D_DIS);
519 519
520 /* Cache mode state */ 520 /* Cache mode state */
521 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000); 521 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
@@ -524,7 +524,7 @@ static int i915_resume(struct drm_device *dev)
524 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000); 524 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
525 525
526 for (i = 0; i < 16; i++) { 526 for (i = 0; i < 16; i++) {
527 I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]); 527 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
528 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]); 528 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
529 } 529 }
530 for (i = 0; i < 3; i++) 530 for (i = 0; i < 3; i++)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2d441d37da99..afb51a390e17 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -30,6 +30,8 @@
30#ifndef _I915_DRV_H_ 30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_ 31#define _I915_DRV_H_
32 32
33#include "i915_reg.h"
34
33/* General customization: 35/* General customization:
34 */ 36 */
35 37
@@ -138,7 +140,7 @@ typedef struct drm_i915_private {
138 u32 saveDSPASTRIDE; 140 u32 saveDSPASTRIDE;
139 u32 saveDSPASIZE; 141 u32 saveDSPASIZE;
140 u32 saveDSPAPOS; 142 u32 saveDSPAPOS;
141 u32 saveDSPABASE; 143 u32 saveDSPAADDR;
142 u32 saveDSPASURF; 144 u32 saveDSPASURF;
143 u32 saveDSPATILEOFF; 145 u32 saveDSPATILEOFF;
144 u32 savePFIT_PGM_RATIOS; 146 u32 savePFIT_PGM_RATIOS;
@@ -159,24 +161,24 @@ typedef struct drm_i915_private {
159 u32 saveDSPBSTRIDE; 161 u32 saveDSPBSTRIDE;
160 u32 saveDSPBSIZE; 162 u32 saveDSPBSIZE;
161 u32 saveDSPBPOS; 163 u32 saveDSPBPOS;
162 u32 saveDSPBBASE; 164 u32 saveDSPBADDR;
163 u32 saveDSPBSURF; 165 u32 saveDSPBSURF;
164 u32 saveDSPBTILEOFF; 166 u32 saveDSPBTILEOFF;
165 u32 saveVCLK_DIVISOR_VGA0; 167 u32 saveVGA0;
166 u32 saveVCLK_DIVISOR_VGA1; 168 u32 saveVGA1;
167 u32 saveVCLK_POST_DIV; 169 u32 saveVGA_PD;
168 u32 saveVGACNTRL; 170 u32 saveVGACNTRL;
169 u32 saveADPA; 171 u32 saveADPA;
170 u32 saveLVDS; 172 u32 saveLVDS;
171 u32 saveLVDSPP_ON; 173 u32 savePP_ON_DELAYS;
172 u32 saveLVDSPP_OFF; 174 u32 savePP_OFF_DELAYS;
173 u32 saveDVOA; 175 u32 saveDVOA;
174 u32 saveDVOB; 176 u32 saveDVOB;
175 u32 saveDVOC; 177 u32 saveDVOC;
176 u32 savePP_ON; 178 u32 savePP_ON;
177 u32 savePP_OFF; 179 u32 savePP_OFF;
178 u32 savePP_CONTROL; 180 u32 savePP_CONTROL;
179 u32 savePP_CYCLE; 181 u32 savePP_DIVISOR;
180 u32 savePFIT_CONTROL; 182 u32 savePFIT_CONTROL;
181 u32 save_palette_a[256]; 183 u32 save_palette_a[256];
182 u32 save_palette_b[256]; 184 u32 save_palette_b[256];
@@ -189,7 +191,7 @@ typedef struct drm_i915_private {
189 u32 saveIMR; 191 u32 saveIMR;
190 u32 saveCACHE_MODE_0; 192 u32 saveCACHE_MODE_0;
191 u32 saveD_STATE; 193 u32 saveD_STATE;
192 u32 saveDSPCLK_GATE_D; 194 u32 saveCG_2D_DIS;
193 u32 saveMI_ARB_STATE; 195 u32 saveMI_ARB_STATE;
194 u32 saveSWF0[16]; 196 u32 saveSWF0[16];
195 u32 saveSWF1[16]; 197 u32 saveSWF1[16];
@@ -283,816 +285,26 @@ extern void i915_mem_release(struct drm_device * dev,
283 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 285 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
284 dev_priv->ring.tail = outring; \ 286 dev_priv->ring.tail = outring; \
285 dev_priv->ring.space -= outcount * 4; \ 287 dev_priv->ring.space -= outcount * 4; \
286 I915_WRITE(LP_RING + RING_TAIL, outring); \ 288 I915_WRITE(PRB0_TAIL, outring); \
287} while(0) 289} while(0)
288 290
289extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
290
291/* Extended config space */
292#define LBB 0xf4
293
294/* VGA stuff */
295
296#define VGA_ST01_MDA 0x3ba
297#define VGA_ST01_CGA 0x3da
298
299#define VGA_MSR_WRITE 0x3c2
300#define VGA_MSR_READ 0x3cc
301#define VGA_MSR_MEM_EN (1<<1)
302#define VGA_MSR_CGA_MODE (1<<0)
303
304#define VGA_SR_INDEX 0x3c4
305#define VGA_SR_DATA 0x3c5
306
307#define VGA_AR_INDEX 0x3c0
308#define VGA_AR_VID_EN (1<<5)
309#define VGA_AR_DATA_WRITE 0x3c0
310#define VGA_AR_DATA_READ 0x3c1
311
312#define VGA_GR_INDEX 0x3ce
313#define VGA_GR_DATA 0x3cf
314/* GR05 */
315#define VGA_GR_MEM_READ_MODE_SHIFT 3
316#define VGA_GR_MEM_READ_MODE_PLANE 1
317/* GR06 */
318#define VGA_GR_MEM_MODE_MASK 0xc
319#define VGA_GR_MEM_MODE_SHIFT 2
320#define VGA_GR_MEM_A0000_AFFFF 0
321#define VGA_GR_MEM_A0000_BFFFF 1
322#define VGA_GR_MEM_B0000_B7FFF 2
323#define VGA_GR_MEM_B0000_BFFFF 3
324
325#define VGA_DACMASK 0x3c6
326#define VGA_DACRX 0x3c7
327#define VGA_DACWX 0x3c8
328#define VGA_DACDATA 0x3c9
329
330#define VGA_CR_INDEX_MDA 0x3b4
331#define VGA_CR_DATA_MDA 0x3b5
332#define VGA_CR_INDEX_CGA 0x3d4
333#define VGA_CR_DATA_CGA 0x3d5
334
335#define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
336#define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
337#define CMD_REPORT_HEAD (7<<23)
338#define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
339#define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
340
341#define INST_PARSER_CLIENT 0x00000000
342#define INST_OP_FLUSH 0x02000000
343#define INST_FLUSH_MAP_CACHE 0x00000001
344
345#define BB1_START_ADDR_MASK (~0x7)
346#define BB1_PROTECTED (1<<0)
347#define BB1_UNPROTECTED (0<<0)
348#define BB2_END_ADDR_MASK (~0x7)
349
350/* Framebuffer compression */
351#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
352#define FBC_LL_BASE 0x03204 /* 4k page aligned */
353#define FBC_CONTROL 0x03208
354#define FBC_CTL_EN (1<<31)
355#define FBC_CTL_PERIODIC (1<<30)
356#define FBC_CTL_INTERVAL_SHIFT (16)
357#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
358#define FBC_CTL_STRIDE_SHIFT (5)
359#define FBC_CTL_FENCENO (1<<0)
360#define FBC_COMMAND 0x0320c
361#define FBC_CMD_COMPRESS (1<<0)
362#define FBC_STATUS 0x03210
363#define FBC_STAT_COMPRESSING (1<<31)
364#define FBC_STAT_COMPRESSED (1<<30)
365#define FBC_STAT_MODIFIED (1<<29)
366#define FBC_STAT_CURRENT_LINE (1<<0)
367#define FBC_CONTROL2 0x03214
368#define FBC_CTL_FENCE_DBL (0<<4)
369#define FBC_CTL_IDLE_IMM (0<<2)
370#define FBC_CTL_IDLE_FULL (1<<2)
371#define FBC_CTL_IDLE_LINE (2<<2)
372#define FBC_CTL_IDLE_DEBUG (3<<2)
373#define FBC_CTL_CPU_FENCE (1<<1)
374#define FBC_CTL_PLANEA (0<<0)
375#define FBC_CTL_PLANEB (1<<0)
376#define FBC_FENCE_OFF 0x0321b
377
378#define FBC_LL_SIZE (1536)
379#define FBC_LL_PAD (32)
380
381/* Interrupt bits:
382 */
383#define USER_INT_FLAG (1<<1)
384#define VSYNC_PIPEB_FLAG (1<<5)
385#define VSYNC_PIPEA_FLAG (1<<7)
386#define HWB_OOM_FLAG (1<<13) /* binner out of memory */
387
388#define I915REG_HWSTAM 0x02098
389#define I915REG_INT_IDENTITY_R 0x020a4
390#define I915REG_INT_MASK_R 0x020a8
391#define I915REG_INT_ENABLE_R 0x020a0
392
393#define I915REG_PIPEASTAT 0x70024
394#define I915REG_PIPEBSTAT 0x71024
395
396#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
397#define I915_VBLANK_CLEAR (1UL<<1)
398
399#define SRX_INDEX 0x3c4
400#define SRX_DATA 0x3c5
401#define SR01 1
402#define SR01_SCREEN_OFF (1<<5)
403
404#define PPCR 0x61204
405#define PPCR_ON (1<<0)
406
407#define DVOB 0x61140
408#define DVOB_ON (1<<31)
409#define DVOC 0x61160
410#define DVOC_ON (1<<31)
411#define LVDS 0x61180
412#define LVDS_ON (1<<31)
413
414#define ADPA 0x61100
415#define ADPA_DPMS_MASK (~(3<<10))
416#define ADPA_DPMS_ON (0<<10)
417#define ADPA_DPMS_SUSPEND (1<<10)
418#define ADPA_DPMS_STANDBY (2<<10)
419#define ADPA_DPMS_OFF (3<<10)
420
421#define NOPID 0x2094
422#define LP_RING 0x2030
423#define HP_RING 0x2040
424/* The binner has its own ring buffer:
425 */
426#define HWB_RING 0x2400
427
428#define RING_TAIL 0x00
429#define TAIL_ADDR 0x001FFFF8
430#define RING_HEAD 0x04
431#define HEAD_WRAP_COUNT 0xFFE00000
432#define HEAD_WRAP_ONE 0x00200000
433#define HEAD_ADDR 0x001FFFFC
434#define RING_START 0x08
435#define START_ADDR 0x0xFFFFF000
436#define RING_LEN 0x0C
437#define RING_NR_PAGES 0x001FF000
438#define RING_REPORT_MASK 0x00000006
439#define RING_REPORT_64K 0x00000002
440#define RING_REPORT_128K 0x00000004
441#define RING_NO_REPORT 0x00000000
442#define RING_VALID_MASK 0x00000001
443#define RING_VALID 0x00000001
444#define RING_INVALID 0x00000000
445
446/* Instruction parser error reg:
447 */
448#define IPEIR 0x2088
449
450/* Scratch pad debug 0 reg:
451 */
452#define SCPD0 0x209c
453
454/* Error status reg:
455 */
456#define ESR 0x20b8
457
458/* Secondary DMA fetch address debug reg:
459 */
460#define DMA_FADD_S 0x20d4
461
462/* Memory Interface Arbitration State
463 */
464#define MI_ARB_STATE 0x20e4
465
466/* Cache mode 0 reg.
467 * - Manipulating render cache behaviour is central
468 * to the concept of zone rendering, tuning this reg can help avoid
469 * unnecessary render cache reads and even writes (for z/stencil)
470 * at beginning and end of scene.
471 *
472 * - To change a bit, write to this reg with a mask bit set and the
473 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
474 */
475#define Cache_Mode_0 0x2120
476#define CACHE_MODE_0 0x2120
477#define CM0_MASK_SHIFT 16
478#define CM0_IZ_OPT_DISABLE (1<<6)
479#define CM0_ZR_OPT_DISABLE (1<<5)
480#define CM0_DEPTH_EVICT_DISABLE (1<<4)
481#define CM0_COLOR_EVICT_DISABLE (1<<3)
482#define CM0_DEPTH_WRITE_DISABLE (1<<1)
483#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
484
485
486/* Graphics flush control. A CPU write flushes the GWB of all writes.
487 * The data is discarded.
488 */
489#define GFX_FLSH_CNTL 0x2170
490
491/* Binner control. Defines the location of the bin pointer list:
492 */
493#define BINCTL 0x2420
494#define BC_MASK (1 << 9)
495
496/* Binned scene info.
497 */
498#define BINSCENE 0x2428
499#define BS_OP_LOAD (1 << 8)
500#define BS_MASK (1 << 22)
501
502/* Bin command parser debug reg:
503 */
504#define BCPD 0x2480
505
506/* Bin memory control debug reg:
507 */
508#define BMCD 0x2484
509
510/* Bin data cache debug reg:
511 */
512#define BDCD 0x2488
513
514/* Binner pointer cache debug reg:
515 */
516#define BPCD 0x248c
517
518/* Binner scratch pad debug reg:
519 */
520#define BINSKPD 0x24f0
521
522/* HWB scratch pad debug reg:
523 */
524#define HWBSKPD 0x24f4
525
526/* Binner memory pool reg:
527 */
528#define BMP_BUFFER 0x2430
529#define BMP_PAGE_SIZE_4K (0 << 10)
530#define BMP_BUFFER_SIZE_SHIFT 1
531#define BMP_ENABLE (1 << 0)
532
533/* Get/put memory from the binner memory pool:
534 */
535#define BMP_GET 0x2438
536#define BMP_PUT 0x2440
537#define BMP_OFFSET_SHIFT 5
538
539/* 3D state packets:
540 */
541#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
542
543#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
544#define SC_UPDATE_SCISSOR (0x1<<1)
545#define SC_ENABLE_MASK (0x1<<0)
546#define SC_ENABLE (0x1<<0)
547
548#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
549
550#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
551#define SCI_YMIN_MASK (0xffff<<16)
552#define SCI_XMIN_MASK (0xffff<<0)
553#define SCI_YMAX_MASK (0xffff<<16)
554#define SCI_XMAX_MASK (0xffff<<0)
555
556#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
557#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
558#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
559#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
560#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
561#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
562#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
563
564#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
565
566#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
567#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
568#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
569#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
570#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
571#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
572
573#define MI_BATCH_BUFFER ((0x30<<23)|1)
574#define MI_BATCH_BUFFER_START (0x31<<23)
575#define MI_BATCH_BUFFER_END (0xA<<23)
576#define MI_BATCH_NON_SECURE (1)
577#define MI_BATCH_NON_SECURE_I965 (1<<8)
578
579#define MI_WAIT_FOR_EVENT ((0x3<<23))
580#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
581#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
582#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
583
584#define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
585
586#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
587#define ASYNC_FLIP (1<<22)
588#define DISPLAY_PLANE_A (0<<20)
589#define DISPLAY_PLANE_B (1<<20)
590
591/* Display regs */
592#define DSPACNTR 0x70180
593#define DSPBCNTR 0x71180
594#define DISPPLANE_SEL_PIPE_MASK (1<<24)
595
596/* Define the region of interest for the binner:
597 */
598#define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
599
600#define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
601
602#define CMD_MI_FLUSH (0x04 << 23)
603#define MI_NO_WRITE_FLUSH (1 << 2)
604#define MI_READ_FLUSH (1 << 0)
605#define MI_EXE_FLUSH (1 << 1)
606#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
607#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
608
609#define BREADCRUMB_BITS 31
610#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
611
612#define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
613#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
614
615#define BLC_PWM_CTL 0x61254
616#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
617
618#define BLC_PWM_CTL2 0x61250
619/** 291/**
620 * This is the most significant 15 bits of the number of backlight cycles in a 292 * Reads a dword out of the status page, which is written to from the command
621 * complete cycle of the modulated backlight control. 293 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
294 * MI_STORE_DATA_IMM.
622 * 295 *
623 * The actual value is this field multiplied by two. 296 * The following dwords have a reserved meaning:
624 */ 297 * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
625#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17) 298 * 4: ring 0 head pointer
626#define BLM_LEGACY_MODE (1 << 16) 299 * 5: ring 1 head pointer (915-class)
627/** 300 * 6: ring 2 head pointer (915-class)
628 * This is the number of cycles out of the backlight modulation cycle for which
629 * the backlight is on.
630 * 301 *
631 * This field must be no greater than the number of cycles in the complete 302 * The area from dword 0x10 to 0x3ff is available for driver usage.
632 * backlight modulation cycle.
633 */
634#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
635#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
636
637#define I915_GCFGC 0xf0
638#define I915_LOW_FREQUENCY_ENABLE (1 << 7)
639#define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
640#define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
641#define I915_DISPLAY_CLOCK_MASK (7 << 4)
642
643#define I855_HPLLCC 0xc0
644#define I855_CLOCK_CONTROL_MASK (3 << 0)
645#define I855_CLOCK_133_200 (0 << 0)
646#define I855_CLOCK_100_200 (1 << 0)
647#define I855_CLOCK_100_133 (2 << 0)
648#define I855_CLOCK_166_250 (3 << 0)
649
650/* p317, 319
651 */ 303 */
652#define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */ 304#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
653#define VCLK2_VCO_N 0x600a 305#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
654#define VCLK2_VCO_DIV_SEL 0x6012
655
656#define VCLK_DIVISOR_VGA0 0x6000
657#define VCLK_DIVISOR_VGA1 0x6004
658#define VCLK_POST_DIV 0x6010
659/** Selects a post divisor of 4 instead of 2. */
660# define VGA1_PD_P2_DIV_4 (1 << 15)
661/** Overrides the p2 post divisor field */
662# define VGA1_PD_P1_DIV_2 (1 << 13)
663# define VGA1_PD_P1_SHIFT 8
664/** P1 value is 2 greater than this field */
665# define VGA1_PD_P1_MASK (0x1f << 8)
666/** Selects a post divisor of 4 instead of 2. */
667# define VGA0_PD_P2_DIV_4 (1 << 7)
668/** Overrides the p2 post divisor field */
669# define VGA0_PD_P1_DIV_2 (1 << 5)
670# define VGA0_PD_P1_SHIFT 0
671/** P1 value is 2 greater than this field */
672# define VGA0_PD_P1_MASK (0x1f << 0)
673
674/* PCI D state control register */
675#define D_STATE 0x6104
676#define DSPCLK_GATE_D 0x6200
677
678/* I830 CRTC registers */
679#define HTOTAL_A 0x60000
680#define HBLANK_A 0x60004
681#define HSYNC_A 0x60008
682#define VTOTAL_A 0x6000c
683#define VBLANK_A 0x60010
684#define VSYNC_A 0x60014
685#define PIPEASRC 0x6001c
686#define BCLRPAT_A 0x60020
687#define VSYNCSHIFT_A 0x60028
688
689#define HTOTAL_B 0x61000
690#define HBLANK_B 0x61004
691#define HSYNC_B 0x61008
692#define VTOTAL_B 0x6100c
693#define VBLANK_B 0x61010
694#define VSYNC_B 0x61014
695#define PIPEBSRC 0x6101c
696#define BCLRPAT_B 0x61020
697#define VSYNCSHIFT_B 0x61028
698
699#define PP_STATUS 0x61200
700# define PP_ON (1 << 31)
701/**
702 * Indicates that all dependencies of the panel are on:
703 *
704 * - PLL enabled
705 * - pipe enabled
706 * - LVDS/DVOB/DVOC on
707 */
708# define PP_READY (1 << 30)
709# define PP_SEQUENCE_NONE (0 << 28)
710# define PP_SEQUENCE_ON (1 << 28)
711# define PP_SEQUENCE_OFF (2 << 28)
712# define PP_SEQUENCE_MASK 0x30000000
713#define PP_CONTROL 0x61204
714# define POWER_TARGET_ON (1 << 0)
715
716#define LVDSPP_ON 0x61208
717#define LVDSPP_OFF 0x6120c
718#define PP_CYCLE 0x61210
719
720#define PFIT_CONTROL 0x61230
721# define PFIT_ENABLE (1 << 31)
722# define PFIT_PIPE_MASK (3 << 29)
723# define PFIT_PIPE_SHIFT 29
724# define VERT_INTERP_DISABLE (0 << 10)
725# define VERT_INTERP_BILINEAR (1 << 10)
726# define VERT_INTERP_MASK (3 << 10)
727# define VERT_AUTO_SCALE (1 << 9)
728# define HORIZ_INTERP_DISABLE (0 << 6)
729# define HORIZ_INTERP_BILINEAR (1 << 6)
730# define HORIZ_INTERP_MASK (3 << 6)
731# define HORIZ_AUTO_SCALE (1 << 5)
732# define PANEL_8TO6_DITHER_ENABLE (1 << 3)
733
734#define PFIT_PGM_RATIOS 0x61234
735# define PFIT_VERT_SCALE_MASK 0xfff00000
736# define PFIT_HORIZ_SCALE_MASK 0x0000fff0
737
738#define PFIT_AUTO_RATIOS 0x61238
739
740
741#define DPLL_A 0x06014
742#define DPLL_B 0x06018
743# define DPLL_VCO_ENABLE (1 << 31)
744# define DPLL_DVO_HIGH_SPEED (1 << 30)
745# define DPLL_SYNCLOCK_ENABLE (1 << 29)
746# define DPLL_VGA_MODE_DIS (1 << 28)
747# define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
748# define DPLLB_MODE_LVDS (2 << 26) /* i915 */
749# define DPLL_MODE_MASK (3 << 26)
750# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
751# define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
752# define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
753# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
754# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
755# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
756/**
757 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
758 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
759 */
760# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
761/**
762 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
763 * this field (only one bit may be set).
764 */
765# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
766# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
767# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
768# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
769# define PLL_REF_INPUT_DREFCLK (0 << 13)
770# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
771# define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
772# define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
773# define PLL_REF_INPUT_MASK (3 << 13)
774# define PLL_LOAD_PULSE_PHASE_SHIFT 9
775/*
776 * Parallel to Serial Load Pulse phase selection.
777 * Selects the phase for the 10X DPLL clock for the PCIe
778 * digital display port. The range is 4 to 13; 10 or more
779 * is just a flip delay. The default is 6
780 */
781# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
782# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
783
784/**
785 * SDVO multiplier for 945G/GM. Not used on 965.
786 *
787 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
788 */
789# define SDVO_MULTIPLIER_MASK 0x000000ff
790# define SDVO_MULTIPLIER_SHIFT_HIRES 4
791# define SDVO_MULTIPLIER_SHIFT_VGA 0
792
793/** @defgroup DPLL_MD
794 * @{
795 */
796/** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
797#define DPLL_A_MD 0x0601c
798/** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
799#define DPLL_B_MD 0x06020
800/**
801 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
802 *
803 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
804 */
805# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
806# define DPLL_MD_UDI_DIVIDER_SHIFT 24
807/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
808# define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
809# define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
810/**
811 * SDVO/UDI pixel multiplier.
812 *
813 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
814 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
815 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
816 * dummy bytes in the datastream at an increased clock rate, with both sides of
817 * the link knowing how many bytes are fill.
818 *
819 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
820 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
821 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
822 * through an SDVO command.
823 *
824 * This register field has values of multiplication factor minus 1, with
825 * a maximum multiplier of 5 for SDVO.
826 */
827# define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
828# define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
829/** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
830 * This best be set to the default value (3) or the CRT won't work. No,
831 * I don't entirely understand what this does...
832 */
833# define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
834# define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
835/** @} */
836
837#define DPLL_TEST 0x606c
838# define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
839# define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
840# define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
841# define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
842# define DPLLB_TEST_N_BYPASS (1 << 19)
843# define DPLLB_TEST_M_BYPASS (1 << 18)
844# define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
845# define DPLLA_TEST_N_BYPASS (1 << 3)
846# define DPLLA_TEST_M_BYPASS (1 << 2)
847# define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
848
849#define ADPA 0x61100
850#define ADPA_DAC_ENABLE (1<<31)
851#define ADPA_DAC_DISABLE 0
852#define ADPA_PIPE_SELECT_MASK (1<<30)
853#define ADPA_PIPE_A_SELECT 0
854#define ADPA_PIPE_B_SELECT (1<<30)
855#define ADPA_USE_VGA_HVPOLARITY (1<<15)
856#define ADPA_SETS_HVPOLARITY 0
857#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
858#define ADPA_VSYNC_CNTL_ENABLE 0
859#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
860#define ADPA_HSYNC_CNTL_ENABLE 0
861#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
862#define ADPA_VSYNC_ACTIVE_LOW 0
863#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
864#define ADPA_HSYNC_ACTIVE_LOW 0
865
866#define FPA0 0x06040
867#define FPA1 0x06044
868#define FPB0 0x06048
869#define FPB1 0x0604c
870# define FP_N_DIV_MASK 0x003f0000
871# define FP_N_DIV_SHIFT 16
872# define FP_M1_DIV_MASK 0x00003f00
873# define FP_M1_DIV_SHIFT 8
874# define FP_M2_DIV_MASK 0x0000003f
875# define FP_M2_DIV_SHIFT 0
876
877
878#define PORT_HOTPLUG_EN 0x61110
879# define SDVOB_HOTPLUG_INT_EN (1 << 26)
880# define SDVOC_HOTPLUG_INT_EN (1 << 25)
881# define TV_HOTPLUG_INT_EN (1 << 18)
882# define CRT_HOTPLUG_INT_EN (1 << 9)
883# define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
884
885#define PORT_HOTPLUG_STAT 0x61114
886# define CRT_HOTPLUG_INT_STATUS (1 << 11)
887# define TV_HOTPLUG_INT_STATUS (1 << 10)
888# define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
889# define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
890# define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
891# define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
892# define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
893# define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
894
895#define SDVOB 0x61140
896#define SDVOC 0x61160
897#define SDVO_ENABLE (1 << 31)
898#define SDVO_PIPE_B_SELECT (1 << 30)
899#define SDVO_STALL_SELECT (1 << 29)
900#define SDVO_INTERRUPT_ENABLE (1 << 26)
901/**
902 * 915G/GM SDVO pixel multiplier.
903 *
904 * Programmed value is multiplier - 1, up to 5x.
905 *
906 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
907 */
908#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
909#define SDVO_PORT_MULTIPLY_SHIFT 23
910#define SDVO_PHASE_SELECT_MASK (15 << 19)
911#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
912#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
913#define SDVOC_GANG_MODE (1 << 16)
914#define SDVO_BORDER_ENABLE (1 << 7)
915#define SDVOB_PCIE_CONCURRENCY (1 << 3)
916#define SDVO_DETECTED (1 << 2)
917/* Bits to be preserved when writing */
918#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
919#define SDVOC_PRESERVE_MASK (1 << 17)
920
921/** @defgroup LVDS
922 * @{
923 */
924/**
925 * This register controls the LVDS output enable, pipe selection, and data
926 * format selection.
927 *
928 * All of the clock/data pairs are force powered down by power sequencing.
929 */
930#define LVDS 0x61180
931/**
932 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
933 * the DPLL semantics change when the LVDS is assigned to that pipe.
934 */
935# define LVDS_PORT_EN (1 << 31)
936/** Selects pipe B for LVDS data. Must be set on pre-965. */
937# define LVDS_PIPEB_SELECT (1 << 30)
938
939/**
940 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
941 * pixel.
942 */
943# define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
944# define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
945# define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
946/**
947 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
948 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
949 * on.
950 */
951# define LVDS_A3_POWER_MASK (3 << 6)
952# define LVDS_A3_POWER_DOWN (0 << 6)
953# define LVDS_A3_POWER_UP (3 << 6)
954/**
955 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
956 * is set.
957 */
958# define LVDS_CLKB_POWER_MASK (3 << 4)
959# define LVDS_CLKB_POWER_DOWN (0 << 4)
960# define LVDS_CLKB_POWER_UP (3 << 4)
961
962/**
963 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
964 * setting for whether we are in dual-channel mode. The B3 pair will
965 * additionally only be powered up when LVDS_A3_POWER_UP is set.
966 */
967# define LVDS_B0B3_POWER_MASK (3 << 2)
968# define LVDS_B0B3_POWER_DOWN (0 << 2)
969# define LVDS_B0B3_POWER_UP (3 << 2)
970
971#define PIPEACONF 0x70008
972#define PIPEACONF_ENABLE (1<<31)
973#define PIPEACONF_DISABLE 0
974#define PIPEACONF_DOUBLE_WIDE (1<<30)
975#define I965_PIPECONF_ACTIVE (1<<30)
976#define PIPEACONF_SINGLE_WIDE 0
977#define PIPEACONF_PIPE_UNLOCKED 0
978#define PIPEACONF_PIPE_LOCKED (1<<25)
979#define PIPEACONF_PALETTE 0
980#define PIPEACONF_GAMMA (1<<24)
981#define PIPECONF_FORCE_BORDER (1<<25)
982#define PIPECONF_PROGRESSIVE (0 << 21)
983#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
984#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
985
986#define DSPARB 0x70030
987#define DSPARB_CSTART_MASK (0x7f << 7)
988#define DSPARB_CSTART_SHIFT 7
989#define DSPARB_BSTART_MASK (0x7f)
990#define DSPARB_BSTART_SHIFT 0
991
992#define PIPEBCONF 0x71008
993#define PIPEBCONF_ENABLE (1<<31)
994#define PIPEBCONF_DISABLE 0
995#define PIPEBCONF_DOUBLE_WIDE (1<<30)
996#define PIPEBCONF_DISABLE 0
997#define PIPEBCONF_GAMMA (1<<24)
998#define PIPEBCONF_PALETTE 0
999
1000#define PIPEBGCMAXRED 0x71010
1001#define PIPEBGCMAXGREEN 0x71014
1002#define PIPEBGCMAXBLUE 0x71018
1003#define PIPEBSTAT 0x71024
1004#define PIPEBFRAMEHIGH 0x71040
1005#define PIPEBFRAMEPIXEL 0x71044
1006
1007#define DSPACNTR 0x70180
1008#define DSPBCNTR 0x71180
1009#define DISPLAY_PLANE_ENABLE (1<<31)
1010#define DISPLAY_PLANE_DISABLE 0
1011#define DISPPLANE_GAMMA_ENABLE (1<<30)
1012#define DISPPLANE_GAMMA_DISABLE 0
1013#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1014#define DISPPLANE_8BPP (0x2<<26)
1015#define DISPPLANE_15_16BPP (0x4<<26)
1016#define DISPPLANE_16BPP (0x5<<26)
1017#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1018#define DISPPLANE_32BPP (0x7<<26)
1019#define DISPPLANE_STEREO_ENABLE (1<<25)
1020#define DISPPLANE_STEREO_DISABLE 0
1021#define DISPPLANE_SEL_PIPE_MASK (1<<24)
1022#define DISPPLANE_SEL_PIPE_A 0
1023#define DISPPLANE_SEL_PIPE_B (1<<24)
1024#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1025#define DISPPLANE_SRC_KEY_DISABLE 0
1026#define DISPPLANE_LINE_DOUBLE (1<<20)
1027#define DISPPLANE_NO_LINE_DOUBLE 0
1028#define DISPPLANE_STEREO_POLARITY_FIRST 0
1029#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1030/* plane B only */
1031#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1032#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1033#define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1034#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1035
1036#define DSPABASE 0x70184
1037#define DSPASTRIDE 0x70188
1038
1039#define DSPBBASE 0x71184
1040#define DSPBADDR DSPBBASE
1041#define DSPBSTRIDE 0x71188
1042
1043#define DSPAKEYVAL 0x70194
1044#define DSPAKEYMASK 0x70198
1045
1046#define DSPAPOS 0x7018C /* reserved */
1047#define DSPASIZE 0x70190
1048#define DSPBPOS 0x7118C
1049#define DSPBSIZE 0x71190
1050
1051#define DSPASURF 0x7019C
1052#define DSPATILEOFF 0x701A4
1053
1054#define DSPBSURF 0x7119C
1055#define DSPBTILEOFF 0x711A4
1056
1057#define VGACNTRL 0x71400
1058# define VGA_DISP_DISABLE (1 << 31)
1059# define VGA_2X_MODE (1 << 30)
1060# define VGA_PIPE_B_SELECT (1 << 29)
1061
1062/*
1063 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1064 * of video memory available to the BIOS in SWF1.
1065 */
1066
1067#define SWF0 0x71410
1068
1069/*
1070 * 855 scratch registers.
1071 */
1072#define SWF10 0x70410
1073
1074#define SWF30 0x72414
1075
1076/*
1077 * Overlay registers. These are overlay registers accessed via MMIO.
1078 * Those loaded via the overlay register page are defined in i830_video.c.
1079 */
1080#define OVADD 0x30000
1081
1082#define DOVSTA 0x30008
1083#define OC_BUF (0x3<<20)
1084 306
1085#define OGAMC5 0x30010 307extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1086#define OGAMC4 0x30014
1087#define OGAMC3 0x30018
1088#define OGAMC2 0x3001c
1089#define OGAMC1 0x30020
1090#define OGAMC0 0x30024
1091/*
1092 * Palette registers
1093 */
1094#define PALETTE_A 0x0a000
1095#define PALETTE_B 0x0a800
1096 308
1097#define IS_I830(dev) ((dev)->pci_device == 0x3577) 309#define IS_I830(dev) ((dev)->pci_device == 0x3577)
1098#define IS_845G(dev) ((dev)->pci_device == 0x2562) 310#define IS_845G(dev) ((dev)->pci_device == 0x2562)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index df036118b8b1..4a2de7897344 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -31,10 +31,6 @@
31#include "i915_drm.h" 31#include "i915_drm.h"
32#include "i915_drv.h" 32#include "i915_drv.h"
33 33
34#define USER_INT_FLAG (1<<1)
35#define VSYNC_PIPEB_FLAG (1<<5)
36#define VSYNC_PIPEA_FLAG (1<<7)
37
38#define MAX_NOPID ((u32)~0) 34#define MAX_NOPID ((u32)~0)
39 35
40/** 36/**
@@ -236,40 +232,43 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
236 u16 temp; 232 u16 temp;
237 u32 pipea_stats, pipeb_stats; 233 u32 pipea_stats, pipeb_stats;
238 234
239 pipea_stats = I915_READ(I915REG_PIPEASTAT); 235 pipea_stats = I915_READ(PIPEASTAT);
240 pipeb_stats = I915_READ(I915REG_PIPEBSTAT); 236 pipeb_stats = I915_READ(PIPEBSTAT);
241 237
242 temp = I915_READ16(I915REG_INT_IDENTITY_R); 238 temp = I915_READ16(IIR);
243 239
244 temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG); 240 temp &= (I915_USER_INTERRUPT |
241 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
242 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT);
245 243
246 DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp); 244 DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
247 245
248 if (temp == 0) 246 if (temp == 0)
249 return IRQ_NONE; 247 return IRQ_NONE;
250 248
251 I915_WRITE16(I915REG_INT_IDENTITY_R, temp); 249 I915_WRITE16(IIR, temp);
252 (void) I915_READ16(I915REG_INT_IDENTITY_R); 250 (void) I915_READ16(IIR);
253 DRM_READMEMORYBARRIER(); 251 DRM_READMEMORYBARRIER();
254 252
255 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); 253 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
256 254
257 if (temp & USER_INT_FLAG) 255 if (temp & I915_USER_INTERRUPT)
258 DRM_WAKEUP(&dev_priv->irq_queue); 256 DRM_WAKEUP(&dev_priv->irq_queue);
259 257
260 if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) { 258 if (temp & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
259 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)) {
261 int vblank_pipe = dev_priv->vblank_pipe; 260 int vblank_pipe = dev_priv->vblank_pipe;
262 261
263 if ((vblank_pipe & 262 if ((vblank_pipe &
264 (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) 263 (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
265 == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) { 264 == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
266 if (temp & VSYNC_PIPEA_FLAG) 265 if (temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
267 atomic_inc(&dev->vbl_received); 266 atomic_inc(&dev->vbl_received);
268 if (temp & VSYNC_PIPEB_FLAG) 267 if (temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
269 atomic_inc(&dev->vbl_received2); 268 atomic_inc(&dev->vbl_received2);
270 } else if (((temp & VSYNC_PIPEA_FLAG) && 269 } else if (((temp & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) &&
271 (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) || 270 (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
272 ((temp & VSYNC_PIPEB_FLAG) && 271 ((temp & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) &&
273 (vblank_pipe & DRM_I915_VBLANK_PIPE_B))) 272 (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
274 atomic_inc(&dev->vbl_received); 273 atomic_inc(&dev->vbl_received);
275 274
@@ -278,12 +277,12 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
278 277
279 if (dev_priv->swaps_pending > 0) 278 if (dev_priv->swaps_pending > 0)
280 drm_locked_tasklet(dev, i915_vblank_tasklet); 279 drm_locked_tasklet(dev, i915_vblank_tasklet);
281 I915_WRITE(I915REG_PIPEASTAT, 280 I915_WRITE(PIPEASTAT,
282 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE| 281 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
283 I915_VBLANK_CLEAR); 282 PIPE_VBLANK_INTERRUPT_STATUS);
284 I915_WRITE(I915REG_PIPEBSTAT, 283 I915_WRITE(PIPEBSTAT,
285 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE| 284 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
286 I915_VBLANK_CLEAR); 285 PIPE_VBLANK_INTERRUPT_STATUS);
287 } 286 }
288 287
289 return IRQ_HANDLED; 288 return IRQ_HANDLED;
@@ -304,12 +303,12 @@ static int i915_emit_irq(struct drm_device * dev)
304 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1; 303 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
305 304
306 BEGIN_LP_RING(6); 305 BEGIN_LP_RING(6);
307 OUT_RING(CMD_STORE_DWORD_IDX); 306 OUT_RING(MI_STORE_DWORD_INDEX);
308 OUT_RING(20); 307 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
309 OUT_RING(dev_priv->counter); 308 OUT_RING(dev_priv->counter);
310 OUT_RING(0); 309 OUT_RING(0);
311 OUT_RING(0); 310 OUT_RING(0);
312 OUT_RING(GFX_OP_USER_INTERRUPT); 311 OUT_RING(MI_USER_INTERRUPT);
313 ADVANCE_LP_RING(); 312 ADVANCE_LP_RING();
314 313
315 return dev_priv->counter; 314 return dev_priv->counter;
@@ -421,11 +420,11 @@ static void i915_enable_interrupt (struct drm_device *dev)
421 420
422 flag = 0; 421 flag = 0;
423 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A) 422 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
424 flag |= VSYNC_PIPEA_FLAG; 423 flag |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
425 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B) 424 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
426 flag |= VSYNC_PIPEB_FLAG; 425 flag |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
427 426
428 I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag); 427 I915_WRITE16(IER, I915_USER_INTERRUPT | flag);
429} 428}
430 429
431/* Set the vblank monitor pipe 430/* Set the vblank monitor pipe
@@ -465,11 +464,11 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
465 return -EINVAL; 464 return -EINVAL;
466 } 465 }
467 466
468 flag = I915_READ(I915REG_INT_ENABLE_R); 467 flag = I915_READ(IER);
469 pipe->pipe = 0; 468 pipe->pipe = 0;
470 if (flag & VSYNC_PIPEA_FLAG) 469 if (flag & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
471 pipe->pipe |= DRM_I915_VBLANK_PIPE_A; 470 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
472 if (flag & VSYNC_PIPEB_FLAG) 471 if (flag & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
473 pipe->pipe |= DRM_I915_VBLANK_PIPE_B; 472 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
474 473
475 return 0; 474 return 0;
@@ -587,9 +586,9 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
587{ 586{
588 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; 587 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
589 588
590 I915_WRITE16(I915REG_HWSTAM, 0xfffe); 589 I915_WRITE16(HWSTAM, 0xfffe);
591 I915_WRITE16(I915REG_INT_MASK_R, 0x0); 590 I915_WRITE16(IMR, 0x0);
592 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); 591 I915_WRITE16(IER, 0x0);
593} 592}
594 593
595void i915_driver_irq_postinstall(struct drm_device * dev) 594void i915_driver_irq_postinstall(struct drm_device * dev)
@@ -614,10 +613,10 @@ void i915_driver_irq_uninstall(struct drm_device * dev)
614 if (!dev_priv) 613 if (!dev_priv)
615 return; 614 return;
616 615
617 I915_WRITE16(I915REG_HWSTAM, 0xffff); 616 I915_WRITE16(HWSTAM, 0xffff);
618 I915_WRITE16(I915REG_INT_MASK_R, 0xffff); 617 I915_WRITE16(IMR, 0xffff);
619 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0); 618 I915_WRITE16(IER, 0x0);
620 619
621 temp = I915_READ16(I915REG_INT_IDENTITY_R); 620 temp = I915_READ16(IIR);
622 I915_WRITE16(I915REG_INT_IDENTITY_R, temp); 621 I915_WRITE16(IIR, temp);
623} 622}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
new file mode 100644
index 000000000000..477c64e6ba2d
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -0,0 +1,1405 @@
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28/* MCH MMIO space */
29/** 915-945 and GM965 MCH register controlling DRAM channel access */
30#define DCC 0x200
31#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
32#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
33#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
34#define DCC_ADDRESSING_MODE_MASK (3 << 0)
35#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
36
37/** 965 MCH register controlling DRAM channel configuration */
38#define CHDECMISC 0x111
39#define CHDECMISC_FLEXMEMORY (1 << 1)
40
41/*
42 * The Bridge device's PCI config space has information about the
43 * fb aperture size and the amount of pre-reserved memory.
44 */
45#define INTEL_GMCH_CTRL 0x52
46#define INTEL_GMCH_ENABLED 0x4
47#define INTEL_GMCH_MEM_MASK 0x1
48#define INTEL_GMCH_MEM_64M 0x1
49#define INTEL_GMCH_MEM_128M 0
50
51#define INTEL_855_GMCH_GMS_MASK (0x7 << 4)
52#define INTEL_855_GMCH_GMS_DISABLED (0x0 << 4)
53#define INTEL_855_GMCH_GMS_STOLEN_1M (0x1 << 4)
54#define INTEL_855_GMCH_GMS_STOLEN_4M (0x2 << 4)
55#define INTEL_855_GMCH_GMS_STOLEN_8M (0x3 << 4)
56#define INTEL_855_GMCH_GMS_STOLEN_16M (0x4 << 4)
57#define INTEL_855_GMCH_GMS_STOLEN_32M (0x5 << 4)
58
59#define INTEL_915G_GMCH_GMS_STOLEN_48M (0x6 << 4)
60#define INTEL_915G_GMCH_GMS_STOLEN_64M (0x7 << 4)
61
62/* PCI config space */
63
64#define HPLLCC 0xc0 /* 855 only */
65#define GC_CLOCK_CONTROL_MASK (3 << 0)
66#define GC_CLOCK_133_200 (0 << 0)
67#define GC_CLOCK_100_200 (1 << 0)
68#define GC_CLOCK_100_133 (2 << 0)
69#define GC_CLOCK_166_250 (3 << 0)
70#define GCFGC 0xf0 /* 915+ only */
71#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
72#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
73#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
74#define GC_DISPLAY_CLOCK_MASK (7 << 4)
75#define LBB 0xf4
76
77/* VGA stuff */
78
79#define VGA_ST01_MDA 0x3ba
80#define VGA_ST01_CGA 0x3da
81
82#define VGA_MSR_WRITE 0x3c2
83#define VGA_MSR_READ 0x3cc
84#define VGA_MSR_MEM_EN (1<<1)
85#define VGA_MSR_CGA_MODE (1<<0)
86
87#define VGA_SR_INDEX 0x3c4
88#define VGA_SR_DATA 0x3c5
89
90#define VGA_AR_INDEX 0x3c0
91#define VGA_AR_VID_EN (1<<5)
92#define VGA_AR_DATA_WRITE 0x3c0
93#define VGA_AR_DATA_READ 0x3c1
94
95#define VGA_GR_INDEX 0x3ce
96#define VGA_GR_DATA 0x3cf
97/* GR05 */
98#define VGA_GR_MEM_READ_MODE_SHIFT 3
99#define VGA_GR_MEM_READ_MODE_PLANE 1
100/* GR06 */
101#define VGA_GR_MEM_MODE_MASK 0xc
102#define VGA_GR_MEM_MODE_SHIFT 2
103#define VGA_GR_MEM_A0000_AFFFF 0
104#define VGA_GR_MEM_A0000_BFFFF 1
105#define VGA_GR_MEM_B0000_B7FFF 2
106#define VGA_GR_MEM_B0000_BFFFF 3
107
108#define VGA_DACMASK 0x3c6
109#define VGA_DACRX 0x3c7
110#define VGA_DACWX 0x3c8
111#define VGA_DACDATA 0x3c9
112
113#define VGA_CR_INDEX_MDA 0x3b4
114#define VGA_CR_DATA_MDA 0x3b5
115#define VGA_CR_INDEX_CGA 0x3d4
116#define VGA_CR_DATA_CGA 0x3d5
117
118/*
119 * Memory interface instructions used by the kernel
120 */
121#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
122
123#define MI_NOOP MI_INSTR(0, 0)
124#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
125#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
126#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
127#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
128#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
129#define MI_FLUSH MI_INSTR(0x04, 0)
130#define MI_READ_FLUSH (1 << 0)
131#define MI_EXE_FLUSH (1 << 1)
132#define MI_NO_WRITE_FLUSH (1 << 2)
133#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
134#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
135#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
136#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
137#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
138#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
139#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
140#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
141#define MI_STORE_DWORD_INDEX_SHIFT 2
142#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 1)
143#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
144#define MI_BATCH_NON_SECURE (1)
145#define MI_BATCH_NON_SECURE_I965 (1<<8)
146#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
147
148/*
149 * 3D instructions used by the kernel
150 */
151#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
152
153#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
154#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
155#define SC_UPDATE_SCISSOR (0x1<<1)
156#define SC_ENABLE_MASK (0x1<<0)
157#define SC_ENABLE (0x1<<0)
158#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
159#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
160#define SCI_YMIN_MASK (0xffff<<16)
161#define SCI_XMIN_MASK (0xffff<<0)
162#define SCI_YMAX_MASK (0xffff<<16)
163#define SCI_XMAX_MASK (0xffff<<0)
164#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
165#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
166#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
167#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
168#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
169#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
170#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
171#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
172#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
173#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
174#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
175#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
176#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
177#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
178#define BLT_DEPTH_8 (0<<24)
179#define BLT_DEPTH_16_565 (1<<24)
180#define BLT_DEPTH_16_1555 (2<<24)
181#define BLT_DEPTH_32 (3<<24)
182#define BLT_ROP_GXCOPY (0xcc<<16)
183#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
184#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
185#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
186#define ASYNC_FLIP (1<<22)
187#define DISPLAY_PLANE_A (0<<20)
188#define DISPLAY_PLANE_B (1<<20)
189
190/*
191 * Instruction and interrupt control regs
192 */
193
194#define PRB0_TAIL 0x02030
195#define PRB0_HEAD 0x02034
196#define PRB0_START 0x02038
197#define PRB0_CTL 0x0203c
198#define TAIL_ADDR 0x001FFFF8
199#define HEAD_WRAP_COUNT 0xFFE00000
200#define HEAD_WRAP_ONE 0x00200000
201#define HEAD_ADDR 0x001FFFFC
202#define RING_NR_PAGES 0x001FF000
203#define RING_REPORT_MASK 0x00000006
204#define RING_REPORT_64K 0x00000002
205#define RING_REPORT_128K 0x00000004
206#define RING_NO_REPORT 0x00000000
207#define RING_VALID_MASK 0x00000001
208#define RING_VALID 0x00000001
209#define RING_INVALID 0x00000000
210#define PRB1_TAIL 0x02040 /* 915+ only */
211#define PRB1_HEAD 0x02044 /* 915+ only */
212#define PRB1_START 0x02048 /* 915+ only */
213#define PRB1_CTL 0x0204c /* 915+ only */
214#define ACTHD_I965 0x02074
215#define HWS_PGA 0x02080
216#define HWS_ADDRESS_MASK 0xfffff000
217#define HWS_START_ADDRESS_SHIFT 4
218#define IPEIR 0x02088
219#define NOPID 0x02094
220#define HWSTAM 0x02098
221#define SCPD0 0x0209c /* 915+ only */
222#define IER 0x020a0
223#define IIR 0x020a4
224#define IMR 0x020a8
225#define ISR 0x020ac
226#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
227#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
228#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
229#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
230#define I915_HWB_OOM_INTERRUPT (1<<13)
231#define I915_SYNC_STATUS_INTERRUPT (1<<12)
232#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
233#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
234#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
235#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
236#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
237#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
238#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
239#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
240#define I915_DEBUG_INTERRUPT (1<<2)
241#define I915_USER_INTERRUPT (1<<1)
242#define I915_ASLE_INTERRUPT (1<<0)
243#define EIR 0x020b0
244#define EMR 0x020b4
245#define ESR 0x020b8
246#define INSTPM 0x020c0
247#define ACTHD 0x020c8
248#define FW_BLC 0x020d8
249#define FW_BLC_SELF 0x020e0 /* 915+ only */
250#define MI_ARB_STATE 0x020e4 /* 915+ only */
251#define CACHE_MODE_0 0x02120 /* 915+ only */
252#define CM0_MASK_SHIFT 16
253#define CM0_IZ_OPT_DISABLE (1<<6)
254#define CM0_ZR_OPT_DISABLE (1<<5)
255#define CM0_DEPTH_EVICT_DISABLE (1<<4)
256#define CM0_COLOR_EVICT_DISABLE (1<<3)
257#define CM0_DEPTH_WRITE_DISABLE (1<<1)
258#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
259#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
260
261/*
262 * Framebuffer compression (915+ only)
263 */
264
265#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
266#define FBC_LL_BASE 0x03204 /* 4k page aligned */
267#define FBC_CONTROL 0x03208
268#define FBC_CTL_EN (1<<31)
269#define FBC_CTL_PERIODIC (1<<30)
270#define FBC_CTL_INTERVAL_SHIFT (16)
271#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
272#define FBC_CTL_STRIDE_SHIFT (5)
273#define FBC_CTL_FENCENO (1<<0)
274#define FBC_COMMAND 0x0320c
275#define FBC_CMD_COMPRESS (1<<0)
276#define FBC_STATUS 0x03210
277#define FBC_STAT_COMPRESSING (1<<31)
278#define FBC_STAT_COMPRESSED (1<<30)
279#define FBC_STAT_MODIFIED (1<<29)
280#define FBC_STAT_CURRENT_LINE (1<<0)
281#define FBC_CONTROL2 0x03214
282#define FBC_CTL_FENCE_DBL (0<<4)
283#define FBC_CTL_IDLE_IMM (0<<2)
284#define FBC_CTL_IDLE_FULL (1<<2)
285#define FBC_CTL_IDLE_LINE (2<<2)
286#define FBC_CTL_IDLE_DEBUG (3<<2)
287#define FBC_CTL_CPU_FENCE (1<<1)
288#define FBC_CTL_PLANEA (0<<0)
289#define FBC_CTL_PLANEB (1<<0)
290#define FBC_FENCE_OFF 0x0321b
291
292#define FBC_LL_SIZE (1536)
293
294/*
295 * GPIO regs
296 */
297#define GPIOA 0x5010
298#define GPIOB 0x5014
299#define GPIOC 0x5018
300#define GPIOD 0x501c
301#define GPIOE 0x5020
302#define GPIOF 0x5024
303#define GPIOG 0x5028
304#define GPIOH 0x502c
305# define GPIO_CLOCK_DIR_MASK (1 << 0)
306# define GPIO_CLOCK_DIR_IN (0 << 1)
307# define GPIO_CLOCK_DIR_OUT (1 << 1)
308# define GPIO_CLOCK_VAL_MASK (1 << 2)
309# define GPIO_CLOCK_VAL_OUT (1 << 3)
310# define GPIO_CLOCK_VAL_IN (1 << 4)
311# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
312# define GPIO_DATA_DIR_MASK (1 << 8)
313# define GPIO_DATA_DIR_IN (0 << 9)
314# define GPIO_DATA_DIR_OUT (1 << 9)
315# define GPIO_DATA_VAL_MASK (1 << 10)
316# define GPIO_DATA_VAL_OUT (1 << 11)
317# define GPIO_DATA_VAL_IN (1 << 12)
318# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
319
320/*
321 * Clock control & power management
322 */
323
324#define VGA0 0x6000
325#define VGA1 0x6004
326#define VGA_PD 0x6010
327#define VGA0_PD_P2_DIV_4 (1 << 7)
328#define VGA0_PD_P1_DIV_2 (1 << 5)
329#define VGA0_PD_P1_SHIFT 0
330#define VGA0_PD_P1_MASK (0x1f << 0)
331#define VGA1_PD_P2_DIV_4 (1 << 15)
332#define VGA1_PD_P1_DIV_2 (1 << 13)
333#define VGA1_PD_P1_SHIFT 8
334#define VGA1_PD_P1_MASK (0x1f << 8)
335#define DPLL_A 0x06014
336#define DPLL_B 0x06018
337#define DPLL_VCO_ENABLE (1 << 31)
338#define DPLL_DVO_HIGH_SPEED (1 << 30)
339#define DPLL_SYNCLOCK_ENABLE (1 << 29)
340#define DPLL_VGA_MODE_DIS (1 << 28)
341#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
342#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
343#define DPLL_MODE_MASK (3 << 26)
344#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
345#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
346#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
347#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
348#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
349#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
350
351#define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
352#define I915_CRC_ERROR_ENABLE (1UL<<29)
353#define I915_CRC_DONE_ENABLE (1UL<<28)
354#define I915_GMBUS_EVENT_ENABLE (1UL<<27)
355#define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
356#define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
357#define I915_DPST_EVENT_ENABLE (1UL<<23)
358#define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
359#define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
360#define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
361#define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
362#define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
363#define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
364#define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
365#define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
366#define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
367#define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
368#define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
369#define I915_DPST_EVENT_STATUS (1UL<<7)
370#define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
371#define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
372#define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
373#define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
374#define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
375#define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
376
377#define SRX_INDEX 0x3c4
378#define SRX_DATA 0x3c5
379#define SR01 1
380#define SR01_SCREEN_OFF (1<<5)
381
382#define PPCR 0x61204
383#define PPCR_ON (1<<0)
384
385#define DVOB 0x61140
386#define DVOB_ON (1<<31)
387#define DVOC 0x61160
388#define DVOC_ON (1<<31)
389#define LVDS 0x61180
390#define LVDS_ON (1<<31)
391
392#define ADPA 0x61100
393#define ADPA_DPMS_MASK (~(3<<10))
394#define ADPA_DPMS_ON (0<<10)
395#define ADPA_DPMS_SUSPEND (1<<10)
396#define ADPA_DPMS_STANDBY (2<<10)
397#define ADPA_DPMS_OFF (3<<10)
398
399#define RING_TAIL 0x00
400#define TAIL_ADDR 0x001FFFF8
401#define RING_HEAD 0x04
402#define HEAD_WRAP_COUNT 0xFFE00000
403#define HEAD_WRAP_ONE 0x00200000
404#define HEAD_ADDR 0x001FFFFC
405#define RING_START 0x08
406#define START_ADDR 0xFFFFF000
407#define RING_LEN 0x0C
408#define RING_NR_PAGES 0x001FF000
409#define RING_REPORT_MASK 0x00000006
410#define RING_REPORT_64K 0x00000002
411#define RING_REPORT_128K 0x00000004
412#define RING_NO_REPORT 0x00000000
413#define RING_VALID_MASK 0x00000001
414#define RING_VALID 0x00000001
415#define RING_INVALID 0x00000000
416
417/* Scratch pad debug 0 reg:
418 */
419#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
420/*
421 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
422 * this field (only one bit may be set).
423 */
424#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
425#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
426/* i830, required in DVO non-gang */
427#define PLL_P2_DIVIDE_BY_4 (1 << 23)
428#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
429#define PLL_REF_INPUT_DREFCLK (0 << 13)
430#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
431#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
432#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
433#define PLL_REF_INPUT_MASK (3 << 13)
434#define PLL_LOAD_PULSE_PHASE_SHIFT 9
435/*
436 * Parallel to Serial Load Pulse phase selection.
437 * Selects the phase for the 10X DPLL clock for the PCIe
438 * digital display port. The range is 4 to 13; 10 or more
439 * is just a flip delay. The default is 6
440 */
441#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
442#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
443/*
444 * SDVO multiplier for 945G/GM. Not used on 965.
445 */
446#define SDVO_MULTIPLIER_MASK 0x000000ff
447#define SDVO_MULTIPLIER_SHIFT_HIRES 4
448#define SDVO_MULTIPLIER_SHIFT_VGA 0
449#define DPLL_A_MD 0x0601c /* 965+ only */
450/*
451 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
452 *
453 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
454 */
455#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
456#define DPLL_MD_UDI_DIVIDER_SHIFT 24
457/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
458#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
459#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
460/*
461 * SDVO/UDI pixel multiplier.
462 *
463 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
464 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
465 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
466 * dummy bytes in the datastream at an increased clock rate, with both sides of
467 * the link knowing how many bytes are fill.
468 *
469 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
470 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
471 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
472 * through an SDVO command.
473 *
474 * This register field has values of multiplication factor minus 1, with
475 * a maximum multiplier of 5 for SDVO.
476 */
477#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
478#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
479/*
480 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
481 * This best be set to the default value (3) or the CRT won't work. No,
482 * I don't entirely understand what this does...
483 */
484#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
485#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
486#define DPLL_B_MD 0x06020 /* 965+ only */
487#define FPA0 0x06040
488#define FPA1 0x06044
489#define FPB0 0x06048
490#define FPB1 0x0604c
491#define FP_N_DIV_MASK 0x003f0000
492#define FP_N_DIV_SHIFT 16
493#define FP_M1_DIV_MASK 0x00003f00
494#define FP_M1_DIV_SHIFT 8
495#define FP_M2_DIV_MASK 0x0000003f
496#define FP_M2_DIV_SHIFT 0
497#define DPLL_TEST 0x606c
498#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
499#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
500#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
501#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
502#define DPLLB_TEST_N_BYPASS (1 << 19)
503#define DPLLB_TEST_M_BYPASS (1 << 18)
504#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
505#define DPLLA_TEST_N_BYPASS (1 << 3)
506#define DPLLA_TEST_M_BYPASS (1 << 2)
507#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
508#define D_STATE 0x6104
509#define CG_2D_DIS 0x6200
510#define CG_3D_DIS 0x6204
511
512/*
513 * Palette regs
514 */
515
516#define PALETTE_A 0x0a000
517#define PALETTE_B 0x0a800
518
519/*
520 * Overlay regs
521 */
522
523#define OVADD 0x30000
524#define DOVSTA 0x30008
525#define OC_BUF (0x3<<20)
526#define OGAMC5 0x30010
527#define OGAMC4 0x30014
528#define OGAMC3 0x30018
529#define OGAMC2 0x3001c
530#define OGAMC1 0x30020
531#define OGAMC0 0x30024
532
533/*
534 * Display engine regs
535 */
536
537/* Pipe A timing regs */
538#define HTOTAL_A 0x60000
539#define HBLANK_A 0x60004
540#define HSYNC_A 0x60008
541#define VTOTAL_A 0x6000c
542#define VBLANK_A 0x60010
543#define VSYNC_A 0x60014
544#define PIPEASRC 0x6001c
545#define BCLRPAT_A 0x60020
546
547/* Pipe B timing regs */
548#define HTOTAL_B 0x61000
549#define HBLANK_B 0x61004
550#define HSYNC_B 0x61008
551#define VTOTAL_B 0x6100c
552#define VBLANK_B 0x61010
553#define VSYNC_B 0x61014
554#define PIPEBSRC 0x6101c
555#define BCLRPAT_B 0x61020
556
557/* VGA port control */
558#define ADPA 0x61100
559#define ADPA_DAC_ENABLE (1<<31)
560#define ADPA_DAC_DISABLE 0
561#define ADPA_PIPE_SELECT_MASK (1<<30)
562#define ADPA_PIPE_A_SELECT 0
563#define ADPA_PIPE_B_SELECT (1<<30)
564#define ADPA_USE_VGA_HVPOLARITY (1<<15)
565#define ADPA_SETS_HVPOLARITY 0
566#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
567#define ADPA_VSYNC_CNTL_ENABLE 0
568#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
569#define ADPA_HSYNC_CNTL_ENABLE 0
570#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
571#define ADPA_VSYNC_ACTIVE_LOW 0
572#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
573#define ADPA_HSYNC_ACTIVE_LOW 0
574#define ADPA_DPMS_MASK (~(3<<10))
575#define ADPA_DPMS_ON (0<<10)
576#define ADPA_DPMS_SUSPEND (1<<10)
577#define ADPA_DPMS_STANDBY (2<<10)
578#define ADPA_DPMS_OFF (3<<10)
579
580/* Hotplug control (945+ only) */
581#define PORT_HOTPLUG_EN 0x61110
582#define SDVOB_HOTPLUG_INT_EN (1 << 26)
583#define SDVOC_HOTPLUG_INT_EN (1 << 25)
584#define TV_HOTPLUG_INT_EN (1 << 18)
585#define CRT_HOTPLUG_INT_EN (1 << 9)
586#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
587
588#define PORT_HOTPLUG_STAT 0x61114
589#define CRT_HOTPLUG_INT_STATUS (1 << 11)
590#define TV_HOTPLUG_INT_STATUS (1 << 10)
591#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
592#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
593#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
594#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
595#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
596#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
597
598/* SDVO port control */
599#define SDVOB 0x61140
600#define SDVOC 0x61160
601#define SDVO_ENABLE (1 << 31)
602#define SDVO_PIPE_B_SELECT (1 << 30)
603#define SDVO_STALL_SELECT (1 << 29)
604#define SDVO_INTERRUPT_ENABLE (1 << 26)
605/**
606 * 915G/GM SDVO pixel multiplier.
607 *
608 * Programmed value is multiplier - 1, up to 5x.
609 *
610 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
611 */
612#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
613#define SDVO_PORT_MULTIPLY_SHIFT 23
614#define SDVO_PHASE_SELECT_MASK (15 << 19)
615#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
616#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
617#define SDVOC_GANG_MODE (1 << 16)
618#define SDVO_BORDER_ENABLE (1 << 7)
619#define SDVOB_PCIE_CONCURRENCY (1 << 3)
620#define SDVO_DETECTED (1 << 2)
621/* Bits to be preserved when writing */
622#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
623#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
624
625/* DVO port control */
626#define DVOA 0x61120
627#define DVOB 0x61140
628#define DVOC 0x61160
629#define DVO_ENABLE (1 << 31)
630#define DVO_PIPE_B_SELECT (1 << 30)
631#define DVO_PIPE_STALL_UNUSED (0 << 28)
632#define DVO_PIPE_STALL (1 << 28)
633#define DVO_PIPE_STALL_TV (2 << 28)
634#define DVO_PIPE_STALL_MASK (3 << 28)
635#define DVO_USE_VGA_SYNC (1 << 15)
636#define DVO_DATA_ORDER_I740 (0 << 14)
637#define DVO_DATA_ORDER_FP (1 << 14)
638#define DVO_VSYNC_DISABLE (1 << 11)
639#define DVO_HSYNC_DISABLE (1 << 10)
640#define DVO_VSYNC_TRISTATE (1 << 9)
641#define DVO_HSYNC_TRISTATE (1 << 8)
642#define DVO_BORDER_ENABLE (1 << 7)
643#define DVO_DATA_ORDER_GBRG (1 << 6)
644#define DVO_DATA_ORDER_RGGB (0 << 6)
645#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
646#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
647#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
648#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
649#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
650#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
651#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
652#define DVO_PRESERVE_MASK (0x7<<24)
653#define DVOA_SRCDIM 0x61124
654#define DVOB_SRCDIM 0x61144
655#define DVOC_SRCDIM 0x61164
656#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
657#define DVO_SRCDIM_VERTICAL_SHIFT 0
658
659/* LVDS port control */
660#define LVDS 0x61180
661/*
662 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
663 * the DPLL semantics change when the LVDS is assigned to that pipe.
664 */
665#define LVDS_PORT_EN (1 << 31)
666/* Selects pipe B for LVDS data. Must be set on pre-965. */
667#define LVDS_PIPEB_SELECT (1 << 30)
668/*
669 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
670 * pixel.
671 */
672#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
673#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
674#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
675/*
676 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
677 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
678 * on.
679 */
680#define LVDS_A3_POWER_MASK (3 << 6)
681#define LVDS_A3_POWER_DOWN (0 << 6)
682#define LVDS_A3_POWER_UP (3 << 6)
683/*
684 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
685 * is set.
686 */
687#define LVDS_CLKB_POWER_MASK (3 << 4)
688#define LVDS_CLKB_POWER_DOWN (0 << 4)
689#define LVDS_CLKB_POWER_UP (3 << 4)
690/*
691 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
692 * setting for whether we are in dual-channel mode. The B3 pair will
693 * additionally only be powered up when LVDS_A3_POWER_UP is set.
694 */
695#define LVDS_B0B3_POWER_MASK (3 << 2)
696#define LVDS_B0B3_POWER_DOWN (0 << 2)
697#define LVDS_B0B3_POWER_UP (3 << 2)
698
699/* Panel power sequencing */
700#define PP_STATUS 0x61200
701#define PP_ON (1 << 31)
702/*
703 * Indicates that all dependencies of the panel are on:
704 *
705 * - PLL enabled
706 * - pipe enabled
707 * - LVDS/DVOB/DVOC on
708 */
709#define PP_READY (1 << 30)
710#define PP_SEQUENCE_NONE (0 << 28)
711#define PP_SEQUENCE_ON (1 << 28)
712#define PP_SEQUENCE_OFF (2 << 28)
713#define PP_SEQUENCE_MASK 0x30000000
714#define PP_CONTROL 0x61204
715#define POWER_TARGET_ON (1 << 0)
716#define PP_ON_DELAYS 0x61208
717#define PP_OFF_DELAYS 0x6120c
718#define PP_DIVISOR 0x61210
719
720/* Panel fitting */
721#define PFIT_CONTROL 0x61230
722#define PFIT_ENABLE (1 << 31)
723#define PFIT_PIPE_MASK (3 << 29)
724#define PFIT_PIPE_SHIFT 29
725#define VERT_INTERP_DISABLE (0 << 10)
726#define VERT_INTERP_BILINEAR (1 << 10)
727#define VERT_INTERP_MASK (3 << 10)
728#define VERT_AUTO_SCALE (1 << 9)
729#define HORIZ_INTERP_DISABLE (0 << 6)
730#define HORIZ_INTERP_BILINEAR (1 << 6)
731#define HORIZ_INTERP_MASK (3 << 6)
732#define HORIZ_AUTO_SCALE (1 << 5)
733#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
734#define PFIT_PGM_RATIOS 0x61234
735#define PFIT_VERT_SCALE_MASK 0xfff00000
736#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
737#define PFIT_AUTO_RATIOS 0x61238
738
739/* Backlight control */
740#define BLC_PWM_CTL 0x61254
741#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
742#define BLC_PWM_CTL2 0x61250 /* 965+ only */
743/*
744 * This is the most significant 15 bits of the number of backlight cycles in a
745 * complete cycle of the modulated backlight control.
746 *
747 * The actual value is this field multiplied by two.
748 */
749#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
750#define BLM_LEGACY_MODE (1 << 16)
751/*
752 * This is the number of cycles out of the backlight modulation cycle for which
753 * the backlight is on.
754 *
755 * This field must be no greater than the number of cycles in the complete
756 * backlight modulation cycle.
757 */
758#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
759#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
760
761/* TV port control */
762#define TV_CTL 0x68000
763/** Enables the TV encoder */
764# define TV_ENC_ENABLE (1 << 31)
765/** Sources the TV encoder input from pipe B instead of A. */
766# define TV_ENC_PIPEB_SELECT (1 << 30)
767/** Outputs composite video (DAC A only) */
768# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
769/** Outputs SVideo video (DAC B/C) */
770# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
771/** Outputs Component video (DAC A/B/C) */
772# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
773/** Outputs Composite and SVideo (DAC A/B/C) */
774# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
775# define TV_TRILEVEL_SYNC (1 << 21)
776/** Enables slow sync generation (945GM only) */
777# define TV_SLOW_SYNC (1 << 20)
778/** Selects 4x oversampling for 480i and 576p */
779# define TV_OVERSAMPLE_4X (0 << 18)
780/** Selects 2x oversampling for 720p and 1080i */
781# define TV_OVERSAMPLE_2X (1 << 18)
782/** Selects no oversampling for 1080p */
783# define TV_OVERSAMPLE_NONE (2 << 18)
784/** Selects 8x oversampling */
785# define TV_OVERSAMPLE_8X (3 << 18)
786/** Selects progressive mode rather than interlaced */
787# define TV_PROGRESSIVE (1 << 17)
788/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
789# define TV_PAL_BURST (1 << 16)
790/** Field for setting delay of Y compared to C */
791# define TV_YC_SKEW_MASK (7 << 12)
792/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
793# define TV_ENC_SDP_FIX (1 << 11)
794/**
795 * Enables a fix for the 915GM only.
796 *
797 * Not sure what it does.
798 */
799# define TV_ENC_C0_FIX (1 << 10)
800/** Bits that must be preserved by software */
801# define TV_CTL_SAVE ((3 << 8) | (3 << 6))
802# define TV_FUSE_STATE_MASK (3 << 4)
803/** Read-only state that reports all features enabled */
804# define TV_FUSE_STATE_ENABLED (0 << 4)
805/** Read-only state that reports that Macrovision is disabled in hardware*/
806# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
807/** Read-only state that reports that TV-out is disabled in hardware. */
808# define TV_FUSE_STATE_DISABLED (2 << 4)
809/** Normal operation */
810# define TV_TEST_MODE_NORMAL (0 << 0)
811/** Encoder test pattern 1 - combo pattern */
812# define TV_TEST_MODE_PATTERN_1 (1 << 0)
813/** Encoder test pattern 2 - full screen vertical 75% color bars */
814# define TV_TEST_MODE_PATTERN_2 (2 << 0)
815/** Encoder test pattern 3 - full screen horizontal 75% color bars */
816# define TV_TEST_MODE_PATTERN_3 (3 << 0)
817/** Encoder test pattern 4 - random noise */
818# define TV_TEST_MODE_PATTERN_4 (4 << 0)
819/** Encoder test pattern 5 - linear color ramps */
820# define TV_TEST_MODE_PATTERN_5 (5 << 0)
821/**
822 * This test mode forces the DACs to 50% of full output.
823 *
824 * This is used for load detection in combination with TVDAC_SENSE_MASK
825 */
826# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
827# define TV_TEST_MODE_MASK (7 << 0)
828
829#define TV_DAC 0x68004
830/**
831 * Reports that DAC state change logic has reported change (RO).
832 *
833 * This gets cleared when TV_DAC_STATE_EN is cleared
834*/
835# define TVDAC_STATE_CHG (1 << 31)
836# define TVDAC_SENSE_MASK (7 << 28)
837/** Reports that DAC A voltage is above the detect threshold */
838# define TVDAC_A_SENSE (1 << 30)
839/** Reports that DAC B voltage is above the detect threshold */
840# define TVDAC_B_SENSE (1 << 29)
841/** Reports that DAC C voltage is above the detect threshold */
842# define TVDAC_C_SENSE (1 << 28)
843/**
844 * Enables DAC state detection logic, for load-based TV detection.
845 *
846 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
847 * to off, for load detection to work.
848 */
849# define TVDAC_STATE_CHG_EN (1 << 27)
850/** Sets the DAC A sense value to high */
851# define TVDAC_A_SENSE_CTL (1 << 26)
852/** Sets the DAC B sense value to high */
853# define TVDAC_B_SENSE_CTL (1 << 25)
854/** Sets the DAC C sense value to high */
855# define TVDAC_C_SENSE_CTL (1 << 24)
856/** Overrides the ENC_ENABLE and DAC voltage levels */
857# define DAC_CTL_OVERRIDE (1 << 7)
858/** Sets the slew rate. Must be preserved in software */
859# define ENC_TVDAC_SLEW_FAST (1 << 6)
860# define DAC_A_1_3_V (0 << 4)
861# define DAC_A_1_1_V (1 << 4)
862# define DAC_A_0_7_V (2 << 4)
863# define DAC_A_OFF (3 << 4)
864# define DAC_B_1_3_V (0 << 2)
865# define DAC_B_1_1_V (1 << 2)
866# define DAC_B_0_7_V (2 << 2)
867# define DAC_B_OFF (3 << 2)
868# define DAC_C_1_3_V (0 << 0)
869# define DAC_C_1_1_V (1 << 0)
870# define DAC_C_0_7_V (2 << 0)
871# define DAC_C_OFF (3 << 0)
872
873/**
874 * CSC coefficients are stored in a floating point format with 9 bits of
875 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
876 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
877 * -1 (0x3) being the only legal negative value.
878 */
879#define TV_CSC_Y 0x68010
880# define TV_RY_MASK 0x07ff0000
881# define TV_RY_SHIFT 16
882# define TV_GY_MASK 0x00000fff
883# define TV_GY_SHIFT 0
884
885#define TV_CSC_Y2 0x68014
886# define TV_BY_MASK 0x07ff0000
887# define TV_BY_SHIFT 16
888/**
889 * Y attenuation for component video.
890 *
891 * Stored in 1.9 fixed point.
892 */
893# define TV_AY_MASK 0x000003ff
894# define TV_AY_SHIFT 0
895
896#define TV_CSC_U 0x68018
897# define TV_RU_MASK 0x07ff0000
898# define TV_RU_SHIFT 16
899# define TV_GU_MASK 0x000007ff
900# define TV_GU_SHIFT 0
901
902#define TV_CSC_U2 0x6801c
903# define TV_BU_MASK 0x07ff0000
904# define TV_BU_SHIFT 16
905/**
906 * U attenuation for component video.
907 *
908 * Stored in 1.9 fixed point.
909 */
910# define TV_AU_MASK 0x000003ff
911# define TV_AU_SHIFT 0
912
913#define TV_CSC_V 0x68020
914# define TV_RV_MASK 0x0fff0000
915# define TV_RV_SHIFT 16
916# define TV_GV_MASK 0x000007ff
917# define TV_GV_SHIFT 0
918
919#define TV_CSC_V2 0x68024
920# define TV_BV_MASK 0x07ff0000
921# define TV_BV_SHIFT 16
922/**
923 * V attenuation for component video.
924 *
925 * Stored in 1.9 fixed point.
926 */
927# define TV_AV_MASK 0x000007ff
928# define TV_AV_SHIFT 0
929
930#define TV_CLR_KNOBS 0x68028
931/** 2s-complement brightness adjustment */
932# define TV_BRIGHTNESS_MASK 0xff000000
933# define TV_BRIGHTNESS_SHIFT 24
934/** Contrast adjustment, as a 2.6 unsigned floating point number */
935# define TV_CONTRAST_MASK 0x00ff0000
936# define TV_CONTRAST_SHIFT 16
937/** Saturation adjustment, as a 2.6 unsigned floating point number */
938# define TV_SATURATION_MASK 0x0000ff00
939# define TV_SATURATION_SHIFT 8
940/** Hue adjustment, as an integer phase angle in degrees */
941# define TV_HUE_MASK 0x000000ff
942# define TV_HUE_SHIFT 0
943
944#define TV_CLR_LEVEL 0x6802c
945/** Controls the DAC level for black */
946# define TV_BLACK_LEVEL_MASK 0x01ff0000
947# define TV_BLACK_LEVEL_SHIFT 16
948/** Controls the DAC level for blanking */
949# define TV_BLANK_LEVEL_MASK 0x000001ff
950# define TV_BLANK_LEVEL_SHIFT 0
951
952#define TV_H_CTL_1 0x68030
953/** Number of pixels in the hsync. */
954# define TV_HSYNC_END_MASK 0x1fff0000
955# define TV_HSYNC_END_SHIFT 16
956/** Total number of pixels minus one in the line (display and blanking). */
957# define TV_HTOTAL_MASK 0x00001fff
958# define TV_HTOTAL_SHIFT 0
959
960#define TV_H_CTL_2 0x68034
961/** Enables the colorburst (needed for non-component color) */
962# define TV_BURST_ENA (1 << 31)
963/** Offset of the colorburst from the start of hsync, in pixels minus one. */
964# define TV_HBURST_START_SHIFT 16
965# define TV_HBURST_START_MASK 0x1fff0000
966/** Length of the colorburst */
967# define TV_HBURST_LEN_SHIFT 0
968# define TV_HBURST_LEN_MASK 0x0001fff
969
970#define TV_H_CTL_3 0x68038
971/** End of hblank, measured in pixels minus one from start of hsync */
972# define TV_HBLANK_END_SHIFT 16
973# define TV_HBLANK_END_MASK 0x1fff0000
974/** Start of hblank, measured in pixels minus one from start of hsync */
975# define TV_HBLANK_START_SHIFT 0
976# define TV_HBLANK_START_MASK 0x0001fff
977
978#define TV_V_CTL_1 0x6803c
979/** XXX */
980# define TV_NBR_END_SHIFT 16
981# define TV_NBR_END_MASK 0x07ff0000
982/** XXX */
983# define TV_VI_END_F1_SHIFT 8
984# define TV_VI_END_F1_MASK 0x00003f00
985/** XXX */
986# define TV_VI_END_F2_SHIFT 0
987# define TV_VI_END_F2_MASK 0x0000003f
988
989#define TV_V_CTL_2 0x68040
990/** Length of vsync, in half lines */
991# define TV_VSYNC_LEN_MASK 0x07ff0000
992# define TV_VSYNC_LEN_SHIFT 16
993/** Offset of the start of vsync in field 1, measured in one less than the
994 * number of half lines.
995 */
996# define TV_VSYNC_START_F1_MASK 0x00007f00
997# define TV_VSYNC_START_F1_SHIFT 8
998/**
999 * Offset of the start of vsync in field 2, measured in one less than the
1000 * number of half lines.
1001 */
1002# define TV_VSYNC_START_F2_MASK 0x0000007f
1003# define TV_VSYNC_START_F2_SHIFT 0
1004
1005#define TV_V_CTL_3 0x68044
1006/** Enables generation of the equalization signal */
1007# define TV_EQUAL_ENA (1 << 31)
1008/** Length of vsync, in half lines */
1009# define TV_VEQ_LEN_MASK 0x007f0000
1010# define TV_VEQ_LEN_SHIFT 16
1011/** Offset of the start of equalization in field 1, measured in one less than
1012 * the number of half lines.
1013 */
1014# define TV_VEQ_START_F1_MASK 0x0007f00
1015# define TV_VEQ_START_F1_SHIFT 8
1016/**
1017 * Offset of the start of equalization in field 2, measured in one less than
1018 * the number of half lines.
1019 */
1020# define TV_VEQ_START_F2_MASK 0x000007f
1021# define TV_VEQ_START_F2_SHIFT 0
1022
1023#define TV_V_CTL_4 0x68048
1024/**
1025 * Offset to start of vertical colorburst, measured in one less than the
1026 * number of lines from vertical start.
1027 */
1028# define TV_VBURST_START_F1_MASK 0x003f0000
1029# define TV_VBURST_START_F1_SHIFT 16
1030/**
1031 * Offset to the end of vertical colorburst, measured in one less than the
1032 * number of lines from the start of NBR.
1033 */
1034# define TV_VBURST_END_F1_MASK 0x000000ff
1035# define TV_VBURST_END_F1_SHIFT 0
1036
1037#define TV_V_CTL_5 0x6804c
1038/**
1039 * Offset to start of vertical colorburst, measured in one less than the
1040 * number of lines from vertical start.
1041 */
1042# define TV_VBURST_START_F2_MASK 0x003f0000
1043# define TV_VBURST_START_F2_SHIFT 16
1044/**
1045 * Offset to the end of vertical colorburst, measured in one less than the
1046 * number of lines from the start of NBR.
1047 */
1048# define TV_VBURST_END_F2_MASK 0x000000ff
1049# define TV_VBURST_END_F2_SHIFT 0
1050
1051#define TV_V_CTL_6 0x68050
1052/**
1053 * Offset to start of vertical colorburst, measured in one less than the
1054 * number of lines from vertical start.
1055 */
1056# define TV_VBURST_START_F3_MASK 0x003f0000
1057# define TV_VBURST_START_F3_SHIFT 16
1058/**
1059 * Offset to the end of vertical colorburst, measured in one less than the
1060 * number of lines from the start of NBR.
1061 */
1062# define TV_VBURST_END_F3_MASK 0x000000ff
1063# define TV_VBURST_END_F3_SHIFT 0
1064
1065#define TV_V_CTL_7 0x68054
1066/**
1067 * Offset to start of vertical colorburst, measured in one less than the
1068 * number of lines from vertical start.
1069 */
1070# define TV_VBURST_START_F4_MASK 0x003f0000
1071# define TV_VBURST_START_F4_SHIFT 16
1072/**
1073 * Offset to the end of vertical colorburst, measured in one less than the
1074 * number of lines from the start of NBR.
1075 */
1076# define TV_VBURST_END_F4_MASK 0x000000ff
1077# define TV_VBURST_END_F4_SHIFT 0
1078
1079#define TV_SC_CTL_1 0x68060
1080/** Turns on the first subcarrier phase generation DDA */
1081# define TV_SC_DDA1_EN (1 << 31)
1082/** Turns on the first subcarrier phase generation DDA */
1083# define TV_SC_DDA2_EN (1 << 30)
1084/** Turns on the first subcarrier phase generation DDA */
1085# define TV_SC_DDA3_EN (1 << 29)
1086/** Sets the subcarrier DDA to reset frequency every other field */
1087# define TV_SC_RESET_EVERY_2 (0 << 24)
1088/** Sets the subcarrier DDA to reset frequency every fourth field */
1089# define TV_SC_RESET_EVERY_4 (1 << 24)
1090/** Sets the subcarrier DDA to reset frequency every eighth field */
1091# define TV_SC_RESET_EVERY_8 (2 << 24)
1092/** Sets the subcarrier DDA to never reset the frequency */
1093# define TV_SC_RESET_NEVER (3 << 24)
1094/** Sets the peak amplitude of the colorburst.*/
1095# define TV_BURST_LEVEL_MASK 0x00ff0000
1096# define TV_BURST_LEVEL_SHIFT 16
1097/** Sets the increment of the first subcarrier phase generation DDA */
1098# define TV_SCDDA1_INC_MASK 0x00000fff
1099# define TV_SCDDA1_INC_SHIFT 0
1100
1101#define TV_SC_CTL_2 0x68064
1102/** Sets the rollover for the second subcarrier phase generation DDA */
1103# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1104# define TV_SCDDA2_SIZE_SHIFT 16
1105/** Sets the increent of the second subcarrier phase generation DDA */
1106# define TV_SCDDA2_INC_MASK 0x00007fff
1107# define TV_SCDDA2_INC_SHIFT 0
1108
1109#define TV_SC_CTL_3 0x68068
1110/** Sets the rollover for the third subcarrier phase generation DDA */
1111# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1112# define TV_SCDDA3_SIZE_SHIFT 16
1113/** Sets the increent of the third subcarrier phase generation DDA */
1114# define TV_SCDDA3_INC_MASK 0x00007fff
1115# define TV_SCDDA3_INC_SHIFT 0
1116
1117#define TV_WIN_POS 0x68070
1118/** X coordinate of the display from the start of horizontal active */
1119# define TV_XPOS_MASK 0x1fff0000
1120# define TV_XPOS_SHIFT 16
1121/** Y coordinate of the display from the start of vertical active (NBR) */
1122# define TV_YPOS_MASK 0x00000fff
1123# define TV_YPOS_SHIFT 0
1124
1125#define TV_WIN_SIZE 0x68074
1126/** Horizontal size of the display window, measured in pixels*/
1127# define TV_XSIZE_MASK 0x1fff0000
1128# define TV_XSIZE_SHIFT 16
1129/**
1130 * Vertical size of the display window, measured in pixels.
1131 *
1132 * Must be even for interlaced modes.
1133 */
1134# define TV_YSIZE_MASK 0x00000fff
1135# define TV_YSIZE_SHIFT 0
1136
1137#define TV_FILTER_CTL_1 0x68080
1138/**
1139 * Enables automatic scaling calculation.
1140 *
1141 * If set, the rest of the registers are ignored, and the calculated values can
1142 * be read back from the register.
1143 */
1144# define TV_AUTO_SCALE (1 << 31)
1145/**
1146 * Disables the vertical filter.
1147 *
1148 * This is required on modes more than 1024 pixels wide */
1149# define TV_V_FILTER_BYPASS (1 << 29)
1150/** Enables adaptive vertical filtering */
1151# define TV_VADAPT (1 << 28)
1152# define TV_VADAPT_MODE_MASK (3 << 26)
1153/** Selects the least adaptive vertical filtering mode */
1154# define TV_VADAPT_MODE_LEAST (0 << 26)
1155/** Selects the moderately adaptive vertical filtering mode */
1156# define TV_VADAPT_MODE_MODERATE (1 << 26)
1157/** Selects the most adaptive vertical filtering mode */
1158# define TV_VADAPT_MODE_MOST (3 << 26)
1159/**
1160 * Sets the horizontal scaling factor.
1161 *
1162 * This should be the fractional part of the horizontal scaling factor divided
1163 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
1164 *
1165 * (src width - 1) / ((oversample * dest width) - 1)
1166 */
1167# define TV_HSCALE_FRAC_MASK 0x00003fff
1168# define TV_HSCALE_FRAC_SHIFT 0
1169
1170#define TV_FILTER_CTL_2 0x68084
1171/**
1172 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1173 *
1174 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
1175 */
1176# define TV_VSCALE_INT_MASK 0x00038000
1177# define TV_VSCALE_INT_SHIFT 15
1178/**
1179 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1180 *
1181 * \sa TV_VSCALE_INT_MASK
1182 */
1183# define TV_VSCALE_FRAC_MASK 0x00007fff
1184# define TV_VSCALE_FRAC_SHIFT 0
1185
1186#define TV_FILTER_CTL_3 0x68088
1187/**
1188 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
1189 *
1190 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
1191 *
1192 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1193 */
1194# define TV_VSCALE_IP_INT_MASK 0x00038000
1195# define TV_VSCALE_IP_INT_SHIFT 15
1196/**
1197 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
1198 *
1199 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
1200 *
1201 * \sa TV_VSCALE_IP_INT_MASK
1202 */
1203# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
1204# define TV_VSCALE_IP_FRAC_SHIFT 0
1205
1206#define TV_CC_CONTROL 0x68090
1207# define TV_CC_ENABLE (1 << 31)
1208/**
1209 * Specifies which field to send the CC data in.
1210 *
1211 * CC data is usually sent in field 0.
1212 */
1213# define TV_CC_FID_MASK (1 << 27)
1214# define TV_CC_FID_SHIFT 27
1215/** Sets the horizontal position of the CC data. Usually 135. */
1216# define TV_CC_HOFF_MASK 0x03ff0000
1217# define TV_CC_HOFF_SHIFT 16
1218/** Sets the vertical position of the CC data. Usually 21 */
1219# define TV_CC_LINE_MASK 0x0000003f
1220# define TV_CC_LINE_SHIFT 0
1221
1222#define TV_CC_DATA 0x68094
1223# define TV_CC_RDY (1 << 31)
1224/** Second word of CC data to be transmitted. */
1225# define TV_CC_DATA_2_MASK 0x007f0000
1226# define TV_CC_DATA_2_SHIFT 16
1227/** First word of CC data to be transmitted. */
1228# define TV_CC_DATA_1_MASK 0x0000007f
1229# define TV_CC_DATA_1_SHIFT 0
1230
1231#define TV_H_LUMA_0 0x68100
1232#define TV_H_LUMA_59 0x681ec
1233#define TV_H_CHROMA_0 0x68200
1234#define TV_H_CHROMA_59 0x682ec
1235#define TV_V_LUMA_0 0x68300
1236#define TV_V_LUMA_42 0x683a8
1237#define TV_V_CHROMA_0 0x68400
1238#define TV_V_CHROMA_42 0x684a8
1239
1240/* Display & cursor control */
1241
1242/* Pipe A */
1243#define PIPEADSL 0x70000
1244#define PIPEACONF 0x70008
1245#define PIPEACONF_ENABLE (1<<31)
1246#define PIPEACONF_DISABLE 0
1247#define PIPEACONF_DOUBLE_WIDE (1<<30)
1248#define I965_PIPECONF_ACTIVE (1<<30)
1249#define PIPEACONF_SINGLE_WIDE 0
1250#define PIPEACONF_PIPE_UNLOCKED 0
1251#define PIPEACONF_PIPE_LOCKED (1<<25)
1252#define PIPEACONF_PALETTE 0
1253#define PIPEACONF_GAMMA (1<<24)
1254#define PIPECONF_FORCE_BORDER (1<<25)
1255#define PIPECONF_PROGRESSIVE (0 << 21)
1256#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1257#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1258#define PIPEASTAT 0x70024
1259#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
1260#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
1261#define PIPE_CRC_DONE_ENABLE (1UL<<28)
1262#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
1263#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
1264#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
1265#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
1266#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
1267#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
1268#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
1269#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
1270#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
1271#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
1272#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
1273#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
1274#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
1275#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
1276#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
1277#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
1278#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
1279#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
1280#define PIPE_DPST_EVENT_STATUS (1UL<<7)
1281#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
1282#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
1283#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
1284#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
1285#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
1286#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
1287#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
1288
1289#define DSPARB 0x70030
1290#define DSPARB_CSTART_MASK (0x7f << 7)
1291#define DSPARB_CSTART_SHIFT 7
1292#define DSPARB_BSTART_MASK (0x7f)
1293#define DSPARB_BSTART_SHIFT 0
1294/*
1295 * The two pipe frame counter registers are not synchronized, so
1296 * reading a stable value is somewhat tricky. The following code
1297 * should work:
1298 *
1299 * do {
1300 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1301 * PIPE_FRAME_HIGH_SHIFT;
1302 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
1303 * PIPE_FRAME_LOW_SHIFT);
1304 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
1305 * PIPE_FRAME_HIGH_SHIFT);
1306 * } while (high1 != high2);
1307 * frame = (high1 << 8) | low1;
1308 */
1309#define PIPEAFRAMEHIGH 0x70040
1310#define PIPE_FRAME_HIGH_MASK 0x0000ffff
1311#define PIPE_FRAME_HIGH_SHIFT 0
1312#define PIPEAFRAMEPIXEL 0x70044
1313#define PIPE_FRAME_LOW_MASK 0xff000000
1314#define PIPE_FRAME_LOW_SHIFT 24
1315#define PIPE_PIXEL_MASK 0x00ffffff
1316#define PIPE_PIXEL_SHIFT 0
1317
1318/* Cursor A & B regs */
1319#define CURACNTR 0x70080
1320#define CURSOR_MODE_DISABLE 0x00
1321#define CURSOR_MODE_64_32B_AX 0x07
1322#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
1323#define MCURSOR_GAMMA_ENABLE (1 << 26)
1324#define CURABASE 0x70084
1325#define CURAPOS 0x70088
1326#define CURSOR_POS_MASK 0x007FF
1327#define CURSOR_POS_SIGN 0x8000
1328#define CURSOR_X_SHIFT 0
1329#define CURSOR_Y_SHIFT 16
1330#define CURBCNTR 0x700c0
1331#define CURBBASE 0x700c4
1332#define CURBPOS 0x700c8
1333
1334/* Display A control */
1335#define DSPACNTR 0x70180
1336#define DISPLAY_PLANE_ENABLE (1<<31)
1337#define DISPLAY_PLANE_DISABLE 0
1338#define DISPPLANE_GAMMA_ENABLE (1<<30)
1339#define DISPPLANE_GAMMA_DISABLE 0
1340#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1341#define DISPPLANE_8BPP (0x2<<26)
1342#define DISPPLANE_15_16BPP (0x4<<26)
1343#define DISPPLANE_16BPP (0x5<<26)
1344#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1345#define DISPPLANE_32BPP (0x7<<26)
1346#define DISPPLANE_STEREO_ENABLE (1<<25)
1347#define DISPPLANE_STEREO_DISABLE 0
1348#define DISPPLANE_SEL_PIPE_MASK (1<<24)
1349#define DISPPLANE_SEL_PIPE_A 0
1350#define DISPPLANE_SEL_PIPE_B (1<<24)
1351#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1352#define DISPPLANE_SRC_KEY_DISABLE 0
1353#define DISPPLANE_LINE_DOUBLE (1<<20)
1354#define DISPPLANE_NO_LINE_DOUBLE 0
1355#define DISPPLANE_STEREO_POLARITY_FIRST 0
1356#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1357#define DSPAADDR 0x70184
1358#define DSPASTRIDE 0x70188
1359#define DSPAPOS 0x7018C /* reserved */
1360#define DSPASIZE 0x70190
1361#define DSPASURF 0x7019C /* 965+ only */
1362#define DSPATILEOFF 0x701A4 /* 965+ only */
1363
1364/* VBIOS flags */
1365#define SWF00 0x71410
1366#define SWF01 0x71414
1367#define SWF02 0x71418
1368#define SWF03 0x7141c
1369#define SWF04 0x71420
1370#define SWF05 0x71424
1371#define SWF06 0x71428
1372#define SWF10 0x70410
1373#define SWF11 0x70414
1374#define SWF14 0x71420
1375#define SWF30 0x72414
1376#define SWF31 0x72418
1377#define SWF32 0x7241c
1378
1379/* Pipe B */
1380#define PIPEBDSL 0x71000
1381#define PIPEBCONF 0x71008
1382#define PIPEBSTAT 0x71024
1383#define PIPEBFRAMEHIGH 0x71040
1384#define PIPEBFRAMEPIXEL 0x71044
1385
1386/* Display B control */
1387#define DSPBCNTR 0x71180
1388#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1389#define DISPPLANE_ALPHA_TRANS_DISABLE 0
1390#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
1391#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1392#define DSPBADDR 0x71184
1393#define DSPBSTRIDE 0x71188
1394#define DSPBPOS 0x7118C
1395#define DSPBSIZE 0x71190
1396#define DSPBSURF 0x7119C
1397#define DSPBTILEOFF 0x711A4
1398
1399/* VBIOS regs */
1400#define VGACNTRL 0x71400
1401# define VGA_DISP_DISABLE (1 << 31)
1402# define VGA_2X_MODE (1 << 30)
1403# define VGA_PIPE_B_SELECT (1 << 29)
1404
1405#endif /* _I915_REG_H_ */
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