diff options
-rw-r--r-- | arch/arm/mach-imx/mach-pcm038.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-mx3/mach-mx31_3ds.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-mx3/mach-mx31moboard.c | 4 | ||||
-rw-r--r-- | drivers/regulator/mc13783-regulator.c | 30 | ||||
-rw-r--r-- | include/linux/mfd/mc13783.h | 67 |
5 files changed, 55 insertions, 54 deletions
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c index f667a262dfc1..505614803bc6 100644 --- a/arch/arm/mach-imx/mach-pcm038.c +++ b/arch/arm/mach-imx/mach-pcm038.c | |||
@@ -254,10 +254,10 @@ static struct regulator_init_data cam_data = { | |||
254 | 254 | ||
255 | static struct mc13783_regulator_init_data pcm038_regulators[] = { | 255 | static struct mc13783_regulator_init_data pcm038_regulators[] = { |
256 | { | 256 | { |
257 | .id = MC13783_REGU_VCAM, | 257 | .id = MC13783_REG_VCAM, |
258 | .init_data = &cam_data, | 258 | .init_data = &cam_data, |
259 | }, { | 259 | }, { |
260 | .id = MC13783_REGU_VMMC1, | 260 | .id = MC13783_REG_VMMC1, |
261 | .init_data = &sdhc1_data, | 261 | .init_data = &sdhc1_data, |
262 | }, | 262 | }, |
263 | }; | 263 | }; |
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c index 4e516b49a901..899a969e92fa 100644 --- a/arch/arm/mach-mx3/mach-mx31_3ds.c +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c | |||
@@ -140,10 +140,10 @@ static struct regulator_init_data gpo_init = { | |||
140 | 140 | ||
141 | static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { | 141 | static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { |
142 | { | 142 | { |
143 | .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */ | 143 | .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */ |
144 | .init_data = &pwgtx_init, | 144 | .init_data = &pwgtx_init, |
145 | }, { | 145 | }, { |
146 | .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */ | 146 | .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */ |
147 | .init_data = &pwgtx_init, | 147 | .init_data = &pwgtx_init, |
148 | }, { | 148 | }, { |
149 | 149 | ||
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c index 203d21a510aa..1aa8d65fccbb 100644 --- a/arch/arm/mach-mx3/mach-mx31moboard.c +++ b/arch/arm/mach-mx3/mach-mx31moboard.c | |||
@@ -216,11 +216,11 @@ static struct regulator_init_data cam_vreg_data = { | |||
216 | 216 | ||
217 | static struct mc13783_regulator_init_data moboard_regulators[] = { | 217 | static struct mc13783_regulator_init_data moboard_regulators[] = { |
218 | { | 218 | { |
219 | .id = MC13783_REGU_VMMC1, | 219 | .id = MC13783_REG_VMMC1, |
220 | .init_data = &sdhc_vreg_data, | 220 | .init_data = &sdhc_vreg_data, |
221 | }, | 221 | }, |
222 | { | 222 | { |
223 | .id = MC13783_REGU_VCAM, | 223 | .id = MC13783_REG_VCAM, |
224 | .init_data = &cam_vreg_data, | 224 | .init_data = &cam_vreg_data, |
225 | }, | 225 | }, |
226 | }; | 226 | }; |
diff --git a/drivers/regulator/mc13783-regulator.c b/drivers/regulator/mc13783-regulator.c index e99917a63ed4..6a6e1d63d86f 100644 --- a/drivers/regulator/mc13783-regulator.c +++ b/drivers/regulator/mc13783-regulator.c | |||
@@ -228,15 +228,15 @@ static struct regulator_ops mc13783_gpo_regulator_ops; | |||
228 | } | 228 | } |
229 | 229 | ||
230 | #define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \ | 230 | #define MC13783_DEFINE_SW(_name, _reg, _vsel_reg, _voltages) \ |
231 | MC13783_DEFINE(SW, _name, _reg, _vsel_reg, _voltages) | 231 | MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages) |
232 | #define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \ | 232 | #define MC13783_DEFINE_REGU(_name, _reg, _vsel_reg, _voltages) \ |
233 | MC13783_DEFINE(REGU, _name, _reg, _vsel_reg, _voltages) | 233 | MC13783_DEFINE(REG, _name, _reg, _vsel_reg, _voltages) |
234 | 234 | ||
235 | static struct mc13783_regulator mc13783_regulators[] = { | 235 | static struct mc13783_regulator mc13783_regulators[] = { |
236 | MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val), | 236 | MC13783_DEFINE_SW(SW3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val), |
237 | 237 | ||
238 | MC13783_FIXED_DEFINE(REGU, VAUDIO, REGULATORMODE0, mc13783_vaudio_val), | 238 | MC13783_FIXED_DEFINE(REG, VAUDIO, REGULATORMODE0, mc13783_vaudio_val), |
239 | MC13783_FIXED_DEFINE(REGU, VIOHI, REGULATORMODE0, mc13783_viohi_val), | 239 | MC13783_FIXED_DEFINE(REG, VIOHI, REGULATORMODE0, mc13783_viohi_val), |
240 | MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0, \ | 240 | MC13783_DEFINE_REGU(VIOLO, REGULATORMODE0, REGULATORSETTING0, \ |
241 | mc13783_violo_val), | 241 | mc13783_violo_val), |
242 | MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \ | 242 | MC13783_DEFINE_REGU(VDIG, REGULATORMODE0, REGULATORSETTING0, \ |
@@ -255,7 +255,7 @@ static struct mc13783_regulator mc13783_regulators[] = { | |||
255 | mc13783_vesim_val), | 255 | mc13783_vesim_val), |
256 | MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \ | 256 | MC13783_DEFINE_REGU(VCAM, REGULATORMODE1, REGULATORSETTING0, \ |
257 | mc13783_vcam_val), | 257 | mc13783_vcam_val), |
258 | MC13783_FIXED_DEFINE(REGU, VRFBG, REGULATORMODE1, mc13783_vrfbg_val), | 258 | MC13783_FIXED_DEFINE(REG, VRFBG, REGULATORMODE1, mc13783_vrfbg_val), |
259 | MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1, \ | 259 | MC13783_DEFINE_REGU(VVIB, REGULATORMODE1, REGULATORSETTING1, \ |
260 | mc13783_vvib_val), | 260 | mc13783_vvib_val), |
261 | MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1, \ | 261 | MC13783_DEFINE_REGU(VRF1, REGULATORMODE1, REGULATORSETTING1, \ |
@@ -266,12 +266,12 @@ static struct mc13783_regulator mc13783_regulators[] = { | |||
266 | mc13783_vmmc_val), | 266 | mc13783_vmmc_val), |
267 | MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1, \ | 267 | MC13783_DEFINE_REGU(VMMC2, REGULATORMODE1, REGULATORSETTING1, \ |
268 | mc13783_vmmc_val), | 268 | mc13783_vmmc_val), |
269 | MC13783_GPO_DEFINE(REGU, GPO1, POWERMISC, mc13783_gpo_val), | 269 | MC13783_GPO_DEFINE(REG, GPO1, POWERMISC, mc13783_gpo_val), |
270 | MC13783_GPO_DEFINE(REGU, GPO2, POWERMISC, mc13783_gpo_val), | 270 | MC13783_GPO_DEFINE(REG, GPO2, POWERMISC, mc13783_gpo_val), |
271 | MC13783_GPO_DEFINE(REGU, GPO3, POWERMISC, mc13783_gpo_val), | 271 | MC13783_GPO_DEFINE(REG, GPO3, POWERMISC, mc13783_gpo_val), |
272 | MC13783_GPO_DEFINE(REGU, GPO4, POWERMISC, mc13783_gpo_val), | 272 | MC13783_GPO_DEFINE(REG, GPO4, POWERMISC, mc13783_gpo_val), |
273 | MC13783_GPO_DEFINE(REGU, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val), | 273 | MC13783_GPO_DEFINE(REG, PWGT1SPI, POWERMISC, mc13783_pwgtdrv_val), |
274 | MC13783_GPO_DEFINE(REGU, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val), | 274 | MC13783_GPO_DEFINE(REG, PWGT2SPI, POWERMISC, mc13783_pwgtdrv_val), |
275 | }; | 275 | }; |
276 | 276 | ||
277 | struct mc13783_regulator_priv { | 277 | struct mc13783_regulator_priv { |
@@ -508,8 +508,8 @@ static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev) | |||
508 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); | 508 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); |
509 | 509 | ||
510 | /* Power Gate enable value is 0 */ | 510 | /* Power Gate enable value is 0 */ |
511 | if (id == MC13783_REGU_PWGT1SPI || | 511 | if (id == MC13783_REG_PWGT1SPI || |
512 | id == MC13783_REGU_PWGT2SPI) | 512 | id == MC13783_REG_PWGT2SPI) |
513 | en_val = 0; | 513 | en_val = 0; |
514 | 514 | ||
515 | mc13783_lock(priv->mc13783); | 515 | mc13783_lock(priv->mc13783); |
@@ -530,8 +530,8 @@ static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev) | |||
530 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); | 530 | dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id); |
531 | 531 | ||
532 | /* Power Gate disable value is 1 */ | 532 | /* Power Gate disable value is 1 */ |
533 | if (id == MC13783_REGU_PWGT1SPI || | 533 | if (id == MC13783_REG_PWGT1SPI || |
534 | id == MC13783_REGU_PWGT2SPI) | 534 | id == MC13783_REG_PWGT2SPI) |
535 | dis_val = mc13783_regulators[id].enable_bit; | 535 | dis_val = mc13783_regulators[id].enable_bit; |
536 | 536 | ||
537 | mc13783_lock(priv->mc13783); | 537 | mc13783_lock(priv->mc13783); |
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h index b4c741e352c2..7d0f3d6a0002 100644 --- a/include/linux/mfd/mc13783.h +++ b/include/linux/mfd/mc13783.h | |||
@@ -1,4 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright 2010 Yong Shen <yong.shen@linaro.org> | ||
2 | * Copyright 2009-2010 Pengutronix | 3 | * Copyright 2009-2010 Pengutronix |
3 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | 4 | * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> |
4 | * | 5 | * |
@@ -122,39 +123,39 @@ int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode, | |||
122 | unsigned int channel, unsigned int *sample); | 123 | unsigned int channel, unsigned int *sample); |
123 | 124 | ||
124 | 125 | ||
125 | #define MC13783_SW_SW1A 0 | 126 | #define MC13783_REG_SW1A 0 |
126 | #define MC13783_SW_SW1B 1 | 127 | #define MC13783_REG_SW1B 1 |
127 | #define MC13783_SW_SW2A 2 | 128 | #define MC13783_REG_SW2A 2 |
128 | #define MC13783_SW_SW2B 3 | 129 | #define MC13783_REG_SW2B 3 |
129 | #define MC13783_SW_SW3 4 | 130 | #define MC13783_REG_SW3 4 |
130 | #define MC13783_SW_PLL 5 | 131 | #define MC13783_REG_PLL 5 |
131 | #define MC13783_REGU_VAUDIO 6 | 132 | #define MC13783_REG_VAUDIO 6 |
132 | #define MC13783_REGU_VIOHI 7 | 133 | #define MC13783_REG_VIOHI 7 |
133 | #define MC13783_REGU_VIOLO 8 | 134 | #define MC13783_REG_VIOLO 8 |
134 | #define MC13783_REGU_VDIG 9 | 135 | #define MC13783_REG_VDIG 9 |
135 | #define MC13783_REGU_VGEN 10 | 136 | #define MC13783_REG_VGEN 10 |
136 | #define MC13783_REGU_VRFDIG 11 | 137 | #define MC13783_REG_VRFDIG 11 |
137 | #define MC13783_REGU_VRFREF 12 | 138 | #define MC13783_REG_VRFREF 12 |
138 | #define MC13783_REGU_VRFCP 13 | 139 | #define MC13783_REG_VRFCP 13 |
139 | #define MC13783_REGU_VSIM 14 | 140 | #define MC13783_REG_VSIM 14 |
140 | #define MC13783_REGU_VESIM 15 | 141 | #define MC13783_REG_VESIM 15 |
141 | #define MC13783_REGU_VCAM 16 | 142 | #define MC13783_REG_VCAM 16 |
142 | #define MC13783_REGU_VRFBG 17 | 143 | #define MC13783_REG_VRFBG 17 |
143 | #define MC13783_REGU_VVIB 18 | 144 | #define MC13783_REG_VVIB 18 |
144 | #define MC13783_REGU_VRF1 19 | 145 | #define MC13783_REG_VRF1 19 |
145 | #define MC13783_REGU_VRF2 20 | 146 | #define MC13783_REG_VRF2 20 |
146 | #define MC13783_REGU_VMMC1 21 | 147 | #define MC13783_REG_VMMC1 21 |
147 | #define MC13783_REGU_VMMC2 22 | 148 | #define MC13783_REG_VMMC2 22 |
148 | #define MC13783_REGU_GPO1 23 | 149 | #define MC13783_REG_GPO1 23 |
149 | #define MC13783_REGU_GPO2 24 | 150 | #define MC13783_REG_GPO2 24 |
150 | #define MC13783_REGU_GPO3 25 | 151 | #define MC13783_REG_GPO3 25 |
151 | #define MC13783_REGU_GPO4 26 | 152 | #define MC13783_REG_GPO4 26 |
152 | #define MC13783_REGU_V1 27 | 153 | #define MC13783_REG_V1 27 |
153 | #define MC13783_REGU_V2 28 | 154 | #define MC13783_REG_V2 28 |
154 | #define MC13783_REGU_V3 29 | 155 | #define MC13783_REG_V3 29 |
155 | #define MC13783_REGU_V4 30 | 156 | #define MC13783_REG_V4 30 |
156 | #define MC13783_REGU_PWGT1SPI 31 | 157 | #define MC13783_REG_PWGT1SPI 31 |
157 | #define MC13783_REGU_PWGT2SPI 32 | 158 | #define MC13783_REG_PWGT2SPI 32 |
158 | 159 | ||
159 | #define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE | 160 | #define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE |
160 | #define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE | 161 | #define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE |