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-rw-r--r--arch/blackfin/mach-bf548/gpio.c189
-rw-r--r--include/asm-blackfin/gpio.h50
-rw-r--r--include/asm-blackfin/mach-bf533/portmux.h65
-rw-r--r--include/asm-blackfin/mach-bf537/portmux.h109
-rw-r--r--include/asm-blackfin/mach-bf548/portmux.h270
-rw-r--r--include/asm-blackfin/mach-bf561/portmux.h87
-rw-r--r--include/asm-blackfin/portmux.h1133
7 files changed, 1874 insertions, 29 deletions
diff --git a/arch/blackfin/mach-bf548/gpio.c b/arch/blackfin/mach-bf548/gpio.c
index 9b1a00aabf28..0da5f0003b8c 100644
--- a/arch/blackfin/mach-bf548/gpio.c
+++ b/arch/blackfin/mach-bf548/gpio.c
@@ -31,38 +31,64 @@
31#include <linux/err.h> 31#include <linux/err.h>
32#include <asm/blackfin.h> 32#include <asm/blackfin.h>
33#include <asm/gpio.h> 33#include <asm/gpio.h>
34#include <asm/portmux.h>
34#include <linux/irq.h> 35#include <linux/irq.h>
35 36
36static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = { 37static struct gpio_port_t *gpio_array[gpio_bank(MAX_BLACKFIN_GPIOS)] = {
37 (struct gpio_port_t *) PORTA_FER, 38 (struct gpio_port_t *)PORTA_FER,
38 (struct gpio_port_t *) PORTB_FER, 39 (struct gpio_port_t *)PORTB_FER,
39 (struct gpio_port_t *) PORTC_FER, 40 (struct gpio_port_t *)PORTC_FER,
40 (struct gpio_port_t *) PORTD_FER, 41 (struct gpio_port_t *)PORTD_FER,
41 (struct gpio_port_t *) PORTE_FER, 42 (struct gpio_port_t *)PORTE_FER,
42 (struct gpio_port_t *) PORTF_FER, 43 (struct gpio_port_t *)PORTF_FER,
43 (struct gpio_port_t *) PORTG_FER, 44 (struct gpio_port_t *)PORTG_FER,
44 (struct gpio_port_t *) PORTH_FER, 45 (struct gpio_port_t *)PORTH_FER,
45 (struct gpio_port_t *) PORTI_FER, 46 (struct gpio_port_t *)PORTI_FER,
46 (struct gpio_port_t *) PORTJ_FER, 47 (struct gpio_port_t *)PORTJ_FER,
47}; 48};
48 49
49static unsigned short reserved_map[gpio_bank(MAX_BLACKFIN_GPIOS)]; 50static unsigned short reserved_gpio_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
51static unsigned short reserved_peri_map[gpio_bank(MAX_BLACKFIN_GPIOS)];
50 52
51inline int check_gpio(unsigned short gpio) 53inline int check_gpio(unsigned short gpio)
52{ 54{
53 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15 \ 55 if (gpio == GPIO_PB15 || gpio == GPIO_PC14 || gpio == GPIO_PC15
54 || gpio == GPIO_PH14 || gpio == GPIO_PH15 \ 56 || gpio == GPIO_PH14 || gpio == GPIO_PH15
55 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15 \ 57 || gpio == GPIO_PJ14 || gpio == GPIO_PJ15
56 || gpio > MAX_BLACKFIN_GPIOS) 58 || gpio > MAX_BLACKFIN_GPIOS)
57 return -EINVAL; 59 return -EINVAL;
58 return 0; 60 return 0;
59} 61}
60 62
63inline void portmux_setup(unsigned short portno, unsigned short function)
64{
65 u32 pmux;
66
67 pmux = gpio_array[gpio_bank(portno)]->port_mux;
68
69 pmux &= ~(0x3 << (2 * gpio_sub_n(portno)));
70 pmux |= (function & 0x3) << (2 * gpio_sub_n(portno));
71
72 gpio_array[gpio_bank(portno)]->port_mux = pmux;
73
74}
75
76inline u16 get_portmux(unsigned short portno)
77{
78 u32 pmux;
79
80 pmux = gpio_array[gpio_bank(portno)]->port_mux;
81
82 return (pmux >> (2 * gpio_sub_n(portno)) & 0x3);
83
84}
85
61static void port_setup(unsigned short gpio, unsigned short usage) 86static void port_setup(unsigned short gpio, unsigned short usage)
62{ 87{
63 if (usage == GPIO_USAGE) { 88 if (usage == GPIO_USAGE) {
64 if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio)) 89 if (gpio_array[gpio_bank(gpio)]->port_fer & gpio_bit(gpio))
65 printk(KERN_WARNING "bfin-gpio: Possible Conflict with Peripheral " 90 printk(KERN_WARNING
91 "bfin-gpio: Possible Conflict with Peripheral "
66 "usage and GPIO %d detected!\n", gpio); 92 "usage and GPIO %d detected!\n", gpio);
67 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio); 93 gpio_array[gpio_bank(gpio)]->port_fer &= ~gpio_bit(gpio);
68 } else 94 } else
@@ -72,18 +98,116 @@ static void port_setup(unsigned short gpio, unsigned short usage)
72 98
73static int __init bfin_gpio_init(void) 99static int __init bfin_gpio_init(void)
74{ 100{
75 int i;
76
77 printk(KERN_INFO "Blackfin GPIO Controller\n"); 101 printk(KERN_INFO "Blackfin GPIO Controller\n");
78 102
79 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE)
80 reserved_map[gpio_bank(i)] = 0;
81
82 return 0; 103 return 0;
83} 104}
84 105
85arch_initcall(bfin_gpio_init); 106arch_initcall(bfin_gpio_init);
86 107
108int peripheral_request(unsigned short per, const char *label)
109{
110 unsigned long flags;
111 unsigned short ident = P_IDENT(per);
112
113 if (!(per & P_DEFINED))
114 return -ENODEV;
115
116 if (check_gpio(ident) < 0)
117 return -EINVAL;
118
119 local_irq_save(flags);
120
121 if (unlikely(reserved_gpio_map[gpio_bank(ident)] & gpio_bit(ident))) {
122 printk(KERN_ERR
123 "%s: Peripheral %d is already reserved as GPIO!\n",
124 __FUNCTION__, per);
125 dump_stack();
126 local_irq_restore(flags);
127 return -EBUSY;
128 }
129
130 if (unlikely(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident))) {
131
132 u16 funct = get_portmux(ident);
133
134 if (!((per & P_MAYSHARE) && (funct == P_FUNCT2MUX(per)))) {
135 printk(KERN_ERR
136 "%s: Peripheral %d is already reserved!\n",
137 __FUNCTION__, per);
138 dump_stack();
139 local_irq_restore(flags);
140 return -EBUSY;
141 }
142 }
143
144 reserved_peri_map[gpio_bank(ident)] |= gpio_bit(ident);
145
146 portmux_setup(ident, P_FUNCT2MUX(per));
147 port_setup(ident, PERIPHERAL_USAGE);
148
149 local_irq_restore(flags);
150
151 return 0;
152}
153EXPORT_SYMBOL(peripheral_request);
154
155int peripheral_request_list(unsigned short per[], const char *label)
156{
157
158 u16 cnt;
159 int ret;
160
161 for (cnt = 0; per[cnt] != 0; cnt++) {
162 ret = peripheral_request(per[cnt], label);
163 if (ret < 0)
164 return ret;
165 }
166
167 return 0;
168}
169EXPORT_SYMBOL(peripheral_request_list);
170
171void peripheral_free(unsigned short per)
172{
173 unsigned long flags;
174 unsigned short ident = P_IDENT(per);
175
176 if (!(per & P_DEFINED))
177 return;
178
179 if (check_gpio(ident) < 0)
180 return;
181
182 local_irq_save(flags);
183
184 if (unlikely(!(reserved_peri_map[gpio_bank(ident)] & gpio_bit(ident)))) {
185 printk(KERN_ERR "bfin-gpio: Peripheral %d wasn't reserved!\n", per);
186 dump_stack();
187 local_irq_restore(flags);
188 return;
189 }
190
191 if (!(per & P_MAYSHARE)) {
192 port_setup(ident, GPIO_USAGE);
193 }
194
195 reserved_peri_map[gpio_bank(ident)] &= ~gpio_bit(ident);
196
197 local_irq_restore(flags);
198}
199EXPORT_SYMBOL(peripheral_free);
200
201void peripheral_free_list(unsigned short per[])
202{
203 u16 cnt;
204
205 for (cnt = 0; per[cnt] != 0; cnt++) {
206 peripheral_free(per[cnt]);
207 }
208
209}
210EXPORT_SYMBOL(peripheral_free_list);
87 211
88/*********************************************************** 212/***********************************************************
89* 213*
@@ -109,13 +233,22 @@ int gpio_request(unsigned short gpio, const char *label)
109 233
110 local_irq_save(flags); 234 local_irq_save(flags);
111 235
112 if (unlikely(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))) { 236 if (unlikely(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
113 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio); 237 printk(KERN_ERR "bfin-gpio: GPIO %d is already reserved!\n", gpio);
114 dump_stack(); 238 dump_stack();
115 local_irq_restore(flags); 239 local_irq_restore(flags);
116 return -EBUSY; 240 return -EBUSY;
117 } 241 }
118 reserved_map[gpio_bank(gpio)] |= gpio_bit(gpio); 242
243 if (unlikely(reserved_peri_map[gpio_bank(gpio)] & gpio_bit(gpio))) {
244 printk(KERN_ERR
245 "bfin-gpio: GPIO %d is already reserved as Peripheral!\n", gpio);
246 dump_stack();
247 local_irq_restore(flags);
248 return -EBUSY;
249 }
250
251 reserved_gpio_map[gpio_bank(gpio)] |= gpio_bit(gpio);
119 252
120 local_irq_restore(flags); 253 local_irq_restore(flags);
121 254
@@ -125,7 +258,6 @@ int gpio_request(unsigned short gpio, const char *label)
125} 258}
126EXPORT_SYMBOL(gpio_request); 259EXPORT_SYMBOL(gpio_request);
127 260
128
129void gpio_free(unsigned short gpio) 261void gpio_free(unsigned short gpio)
130{ 262{
131 unsigned long flags; 263 unsigned long flags;
@@ -135,25 +267,24 @@ void gpio_free(unsigned short gpio)
135 267
136 local_irq_save(flags); 268 local_irq_save(flags);
137 269
138 if (unlikely(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio)))) { 270 if (unlikely(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)))) {
139 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio); 271 printk(KERN_ERR "bfin-gpio: GPIO %d wasn't reserved!\n", gpio);
140 dump_stack(); 272 dump_stack();
141 local_irq_restore(flags); 273 local_irq_restore(flags);
142 return; 274 return;
143 } 275 }
144 276
145 reserved_map[gpio_bank(gpio)] &= ~gpio_bit(gpio); 277 reserved_gpio_map[gpio_bank(gpio)] &= ~gpio_bit(gpio);
146 278
147 local_irq_restore(flags); 279 local_irq_restore(flags);
148} 280}
149EXPORT_SYMBOL(gpio_free); 281EXPORT_SYMBOL(gpio_free);
150 282
151
152void gpio_direction_input(unsigned short gpio) 283void gpio_direction_input(unsigned short gpio)
153{ 284{
154 unsigned long flags; 285 unsigned long flags;
155 286
156 BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))); 287 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
157 288
158 local_irq_save(flags); 289 local_irq_save(flags);
159 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio); 290 gpio_array[gpio_bank(gpio)]->port_dir_clear = gpio_bit(gpio);
@@ -166,7 +297,7 @@ void gpio_direction_output(unsigned short gpio)
166{ 297{
167 unsigned long flags; 298 unsigned long flags;
168 299
169 BUG_ON(!(reserved_map[gpio_bank(gpio)] & gpio_bit(gpio))); 300 BUG_ON(!(reserved_gpio_map[gpio_bank(gpio)] & gpio_bit(gpio)));
170 301
171 local_irq_save(flags); 302 local_irq_save(flags);
172 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio); 303 gpio_array[gpio_bank(gpio)]->port_inen &= ~gpio_bit(gpio);
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
index e679703f7ae5..7480cfa7e2d6 100644
--- a/include/asm-blackfin/gpio.h
+++ b/include/asm-blackfin/gpio.h
@@ -210,6 +210,56 @@
210 210
211#ifdef BF561_FAMILY 211#ifdef BF561_FAMILY
212#define MAX_BLACKFIN_GPIOS 48 212#define MAX_BLACKFIN_GPIOS 48
213
214#define GPIO_PF0 0
215#define GPIO_PF1 1
216#define GPIO_PF2 2
217#define GPIO_PF3 3
218#define GPIO_PF4 4
219#define GPIO_PF5 5
220#define GPIO_PF6 6
221#define GPIO_PF7 7
222#define GPIO_PF8 8
223#define GPIO_PF9 9
224#define GPIO_PF10 10
225#define GPIO_PF11 11
226#define GPIO_PF12 12
227#define GPIO_PF13 13
228#define GPIO_PF14 14
229#define GPIO_PF15 15
230#define GPIO_PF16 16
231#define GPIO_PF17 17
232#define GPIO_PF18 18
233#define GPIO_PF19 19
234#define GPIO_PF20 20
235#define GPIO_PF21 21
236#define GPIO_PF22 22
237#define GPIO_PF23 23
238#define GPIO_PF24 24
239#define GPIO_PF25 25
240#define GPIO_PF26 26
241#define GPIO_PF27 27
242#define GPIO_PF28 28
243#define GPIO_PF29 29
244#define GPIO_PF30 30
245#define GPIO_PF31 31
246#define GPIO_PF32 32
247#define GPIO_PF33 33
248#define GPIO_PF34 34
249#define GPIO_PF35 35
250#define GPIO_PF36 36
251#define GPIO_PF37 37
252#define GPIO_PF38 38
253#define GPIO_PF39 39
254#define GPIO_PF40 40
255#define GPIO_PF41 41
256#define GPIO_PF42 42
257#define GPIO_PF43 43
258#define GPIO_PF44 44
259#define GPIO_PF45 45
260#define GPIO_PF46 46
261#define GPIO_PF47 47
262
213#define PORT_FIO0 GPIO_0 263#define PORT_FIO0 GPIO_0
214#define PORT_FIO1 GPIO_16 264#define PORT_FIO1 GPIO_16
215#define PORT_FIO2 GPIO_32 265#define PORT_FIO2 GPIO_32
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
new file mode 100644
index 000000000000..b88d7a03ee3e
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/portmux.h
@@ -0,0 +1,65 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE)
7#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF3))
8#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF4))
9#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF5))
10#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF6))
11#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF7))
12#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF8))
13#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF9))
14#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF10))
15#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF11))
16#define P_PPI0_D0 (P_DONTCARE)
17#define P_PPI0_D1 (P_DONTCARE)
18#define P_PPI0_D2 (P_DONTCARE)
19#define P_PPI0_D3 (P_DONTCARE)
20#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF15))
21#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF14))
22#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF13))
23#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF12))
24
25#define P_SPORT1_TSCLK (P_DONTCARE)
26#define P_SPORT1_RSCLK (P_DONTCARE)
27#define P_SPORT0_TSCLK (P_DONTCARE)
28#define P_SPORT0_RSCLK (P_DONTCARE)
29#define P_UART0_RX (P_DONTCARE)
30#define P_UART0_TX (P_DONTCARE)
31#define P_SPORT1_DRSEC (P_DONTCARE)
32#define P_SPORT1_RFS (P_DONTCARE)
33#define P_SPORT1_DTPRI (P_DONTCARE)
34#define P_SPORT1_DTSEC (P_DONTCARE)
35#define P_SPORT1_TFS (P_DONTCARE)
36#define P_SPORT1_DRPRI (P_DONTCARE)
37#define P_SPORT0_DRSEC (P_DONTCARE)
38#define P_SPORT0_RFS (P_DONTCARE)
39#define P_SPORT0_DTPRI (P_DONTCARE)
40#define P_SPORT0_DTSEC (P_DONTCARE)
41#define P_SPORT0_TFS (P_DONTCARE)
42#define P_SPORT0_DRPRI (P_DONTCARE)
43
44#define P_SPI0_MOSI (P_DONTCARE)
45#define P_SPI0_MIS0 (P_DONTCARE)
46#define P_SPI0_SCK (P_DONTCARE)
47#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
48#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
49#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
50#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
51#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
52#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
53#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
54#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
55
56#define P_TMR2 (P_DONTCARE)
57#define P_TMR1 (P_DONTCARE)
58#define P_TMR0 (P_DONTCARE)
59#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF1))
60
61
62
63
64
65#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
new file mode 100644
index 000000000000..23e13c5abc4d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -0,0 +1,109 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
5#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
6#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
7#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
8#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
9#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
10#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
11#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
12#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
13#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
14#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
15#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
16#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
17#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
18#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
19#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
20#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
21#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
22#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
23#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
24#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
25#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
26#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
27#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
28#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
29#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
30#define P_TACLK0 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
31#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
32
33#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
34#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
35#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
36#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
37#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
38#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
39#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
40#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
41#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
42#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
43#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
44#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
45#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
46#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
47#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
48#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
49#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
50#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
51#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
52#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
53#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
54#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
55#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
56#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
57
58#define P_MII0_ETxD0 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
59#define P_MII0_ETxD1 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
60#define P_MII0_ETxD2 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
61#define P_MII0_ETxD3 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
62#define P_MII0_ETxEN (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
63#define P_MII0_TxCLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
64#define P_MII0_PHYINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
65#define P_MII0_COL (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
66#define P_MII0_ERxD0 (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
67#define P_MII0_ERxD1 (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
68#define P_MII0_ERxD2 (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
69#define P_MII0_ERxD3 (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
70#define P_MII0_ERxDV (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
71#define P_MII0_ERxCLK (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
72#define P_MII0_ERxER (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
73#define P_MII0_CRS (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
74#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
75#define P_RMII0_MDINT (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
76#define P_RMII0_CRS_DV (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
77
78#define PORT_PJ0 (GPIO_PH15 + 1)
79#define PORT_PJ1 (GPIO_PH15 + 2)
80#define PORT_PJ2 (GPIO_PH15 + 3)
81#define PORT_PJ3 (GPIO_PH15 + 4)
82#define PORT_PJ4 (GPIO_PH15 + 5)
83#define PORT_PJ5 (GPIO_PH15 + 6)
84#define PORT_PJ6 (GPIO_PH15 + 7)
85#define PORT_PJ7 (GPIO_PH15 + 8)
86#define PORT_PJ8 (GPIO_PH15 + 9)
87#define PORT_PJ9 (GPIO_PH15 + 10)
88#define PORT_PJ10 (GPIO_PH15 + 11)
89#define PORT_PJ11 (GPIO_PH15 + 12)
90
91#define P_MDC (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
92#define P_MDIO (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
93#define P_TWI0_SCL (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
94#define P_TWI0_SDA (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
95#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
96#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
97#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
98#define P_SPORT0_RFS (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
99#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
100#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
101#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
102#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
103#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
104#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
105#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
106#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
107#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
108
109#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
new file mode 100644
index 000000000000..b382deb501a7
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/portmux.h
@@ -0,0 +1,270 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_SPORT2_TFS (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
5#define P_SPORT2_DTSEC (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
6#define P_SPORT2_DTPRI (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
7#define P_SPORT2_TSCLK (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
8#define P_SPORT2_RFS (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
9#define P_SPORT2_DRSEC (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
10#define P_SPORT2_DRPRI (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
11#define P_SPORT2_RSCLK (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
12#define P_SPORT3_TFS (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
13#define P_SPORT3_DTSEC (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
14#define P_SPORT3_DTPRI (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
15#define P_SPORT3_TSCLK (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
16#define P_SPORT3_RFS (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
17#define P_SPORT3_DRSEC (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
18#define P_SPORT3_DRPRI (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
19#define P_SPORT3_RSCLK (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
20#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
21#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
22#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
23#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
24
25#define P_TWI1_SCL (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
26#define P_TWI1_SDA (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
27#define P_UART3_RTS (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
28#define P_UART3_CTS (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
29#define P_UART2_TX (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
30#define P_UART2_RX (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
31#define P_UART3_TX (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
32#define P_UART3_RX (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
33#define P_SPI2_SS (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
34#define P_SPI2_SSEL1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
35#define P_SPI2_SSEL2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
36#define P_SPI2_SSEL3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
37#define P_SPI2_SCK (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
38#define P_SPI2_MOSI (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
39#define P_SPI2_MISO (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
40#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
41#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
42#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
43#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
44
45#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
46#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
47#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
48#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
49#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
50#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
51#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
52#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
53#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
54#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
55#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
56#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
57#define P_SD_CLK (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
58#define P_SD_CMD (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
59#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
60#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
61
62#define P_PPI1_D0 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
63#define P_PPI1_D1 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
64#define P_PPI1_D2 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
65#define P_PPI1_D3 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
66#define P_PPI1_D4 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
67#define P_PPI1_D5 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
68#define P_PPI1_D6 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
69#define P_PPI1_D7 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
70#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
71#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
72#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
73#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
74#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
75#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
76#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
77#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
78
79#define P_HOST_D8 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
80#define P_HOST_D9 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
81#define P_HOST_D10 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
82#define P_HOST_D11 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
83#define P_HOST_D12 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
84#define P_HOST_D13 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
85#define P_HOST_D14 (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
86#define P_HOST_D15 (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
87#define P_HOST_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
88#define P_HOST_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
89#define P_HOST_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
90#define P_HOST_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
91#define P_HOST_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
92#define P_HOST_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
93#define P_HOST_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
94#define P_HOST_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
95#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
96#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
97#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
98#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
99#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
100#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
101#define P_SPORT1_DRPRI (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
102#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
103#define P_PPI2_D0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
104#define P_PPI2_D1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
105#define P_PPI2_D2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
106#define P_PPI2_D3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
107#define P_PPI2_D4 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
108#define P_PPI2_D5 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
109#define P_PPI2_D6 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
110#define P_PPI2_D7 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
111#define P_PPI0_D18 (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
112#define P_PPI0_D19 (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
113#define P_PPI0_D20 (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
114#define P_PPI0_D21 (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
115#define P_PPI0_D22 (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
116#define P_PPI0_D23 (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
117#define P_KEY_ROW0 (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
118#define P_KEY_ROW1 (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
119#define P_KEY_ROW2 (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
120#define P_KEY_ROW3 (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
121#define P_KEY_COL0 (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
122#define P_KEY_COL1 (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
123#define P_KEY_COL2 (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
124#define P_KEY_COL3 (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
125
126#define P_SPI0_SCK (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
127#define P_SPI0_MISO (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
128#define P_SPI0_MOSI (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
129#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
130#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
131#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
132#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
133#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
134#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
135#define P_UART1_RTS (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
136#define P_UART1_CTS (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
137#define P_PPI1_CLK (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
138#define P_PPI1_FS1 (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
139#define P_PPI1_FS2 (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
140#define P_TWI0_SCL (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
141#define P_TWI0_SDA (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
142#define P_KEY_COL7 (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
143#define P_KEY_ROW6 (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
144#define P_KEY_COL6 (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
145#define P_KEY_ROW5 (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
146#define P_KEY_COL5 (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
147#define P_KEY_ROW4 (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
148#define P_KEY_COL4 (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
149#define P_KEY_ROW7 (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
150
151#define P_PPI0_D0 (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
152#define P_PPI0_D1 (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
153#define P_PPI0_D2 (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
154#define P_PPI0_D3 (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
155#define P_PPI0_D4 (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
156#define P_PPI0_D5 (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
157#define P_PPI0_D6 (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
158#define P_PPI0_D7 (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
159#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
160#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
161#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
162#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
163#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
164#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
165#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
166#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
167#define P_ATAPI_D0A (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
168#define P_ATAPI_D1A (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
169#define P_ATAPI_D2A (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
170#define P_ATAPI_D3A (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
171#define P_ATAPI_D4A (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
172#define P_ATAPI_D5A (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
173#define P_ATAPI_D6A (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
174#define P_ATAPI_D7A (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
175#define P_ATAPI_D8A (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
176#define P_ATAPI_D9A (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
177#define P_ATAPI_D10A (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
178#define P_ATAPI_D11A (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
179#define P_ATAPI_D12A (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
180#define P_ATAPI_D13A (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
181#define P_ATAPI_D14A (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
182#define P_ATAPI_D15A (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
183
184#define P_PPI0_CLK (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
185#define P_PPI0_FS1 (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
186#define P_PPI0_FS2 (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
187#define P_PPI0_D16 (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
188#define P_PPI0_D17 (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
189#define P_SPI1_SSEL1 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
190#define P_SPI1_SSEL2 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
191#define P_SPI1_SSEL3 (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
192#define P_SPI1_SCK (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
193#define P_SPI1_MISO (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
194#define P_SPI1_MOSI (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
195#define P_SPI1_SS (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
196#define P_CAN0_TX (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
197#define P_CAN0_RX (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
198#define P_CAN1_TX (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
199#define P_CAN1_RX (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
200#define P_ATAPI_A0A (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
201#define P_ATAPI_A1A (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
202#define P_ATAPI_A2A (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
203#define P_HOST_CE (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
204#define P_HOST_RD (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
205#define P_HOST_WR (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
206#define P_MTXONB (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
207#define P_PPI2_FS2 (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
208#define P_PPI2_FS1 (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
209#define P_PPI2_CLK (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
210#define P_CNT_CZM (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
211
212#define P_UART1_TX (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
213#define P_UART1_RX (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
214#define P_ATAPI_RESET (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
215#define P_HOST_ADDR (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
216#define P_HOST_ACK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
217#define P_MTX (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
218#define P_MRX (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
219#define P_MRXONB (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
220#define P_A4 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
221#define P_A5 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
222#define P_A6 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
223#define P_A7 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
224#define P_A8 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
225#define P_A9 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
226#define P_PPI1_FS3 (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
227#define P_PPI2_FS3 (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
228#define P_TMR8 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
229#define P_TMR9 (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
230#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
231#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
232#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
233#define P_PPI0_FS3 (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
234#define P_CNT_CDG (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
235#define P_CNT_CUD (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
236
237#define P_A10 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
238#define P_A11 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
239#define P_A12 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
240#define P_A13 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
241#define P_A14 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
242#define P_A15 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
243#define P_A16 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
244#define P_A17 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
245#define P_A18 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
246#define P_A19 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
247#define P_A20 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
248#define P_A21 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
249#define P_A22 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
250#define P_A23 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
251#define P_A24 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
252#define P_A25 (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
253#define P_NOR_CLK (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
254
255#define P_AMC_ARDY_NOR_WAIT (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
256#define P_NAND_CE (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
257#define P_NAND_RB (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
258#define P_ATAPI_DIOR (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
259#define P_ATAPI_DIOW (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
260#define P_ATAPI_CS0 (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
261#define P_ATAPI_CS1 (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
262#define P_ATAPI_DMACK (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
263#define P_ATAPI_DMARQ (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
264#define P_ATAPI_INTRQ (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
265#define P_ATAPI_IORDY (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
266#define P_AMC_BR (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
267#define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
268#define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
269
270#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
new file mode 100644
index 000000000000..10d11d5ffe23
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/portmux.h
@@ -0,0 +1,87 @@
1#ifndef _MACH_PORTMUX_H_
2#define _MACH_PORTMUX_H_
3
4#define P_PPI0_CLK (P_DONTCARE)
5#define P_PPI0_FS1 (P_DONTCARE)
6#define P_PPI0_FS2 (P_DONTCARE)
7#define P_PPI0_FS3 (P_DONTCARE)
8#define P_PPI0_D15 (P_DEFINED | P_IDENT(GPIO_PF47))
9#define P_PPI0_D14 (P_DEFINED | P_IDENT(GPIO_PF46))
10#define P_PPI0_D13 (P_DEFINED | P_IDENT(GPIO_PF45))
11#define P_PPI0_D12 (P_DEFINED | P_IDENT(GPIO_PF44))
12#define P_PPI0_D11 (P_DEFINED | P_IDENT(GPIO_PF43))
13#define P_PPI0_D10 (P_DEFINED | P_IDENT(GPIO_PF42))
14#define P_PPI0_D9 (P_DEFINED | P_IDENT(GPIO_PF41))
15#define P_PPI0_D8 (P_DEFINED | P_IDENT(GPIO_PF40))
16#define P_PPI0_D0 (P_DONTCARE)
17#define P_PPI0_D1 (P_DONTCARE)
18#define P_PPI0_D2 (P_DONTCARE)
19#define P_PPI0_D3 (P_DONTCARE)
20#define P_PPI0_D4 (P_DONTCARE)
21#define P_PPI0_D5 (P_DONTCARE)
22#define P_PPI0_D6 (P_DONTCARE)
23#define P_PPI0_D7 (P_DONTCARE)
24#define P_PPI1_CLK (P_DONTCARE)
25#define P_PPI1_FS1 (P_DONTCARE)
26#define P_PPI1_FS2 (P_DONTCARE)
27#define P_PPI1_FS3 (P_DONTCARE)
28#define P_PPI1_D15 (P_DEFINED | P_IDENT(GPIO_PF39))
29#define P_PPI1_D14 (P_DEFINED | P_IDENT(GPIO_PF38))
30#define P_PPI1_D13 (P_DEFINED | P_IDENT(GPIO_PF37))
31#define P_PPI1_D12 (P_DEFINED | P_IDENT(GPIO_PF36))
32#define P_PPI1_D11 (P_DEFINED | P_IDENT(GPIO_PF35))
33#define P_PPI1_D10 (P_DEFINED | P_IDENT(GPIO_PF34))
34#define P_PPI1_D9 (P_DEFINED | P_IDENT(GPIO_PF33))
35#define P_PPI1_D8 (P_DEFINED | P_IDENT(GPIO_PF32))
36#define P_PPI1_D0 (P_DONTCARE)
37#define P_PPI1_D1 (P_DONTCARE)
38#define P_PPI1_D2 (P_DONTCARE)
39#define P_PPI1_D3 (P_DONTCARE)
40#define P_PPI1_D4 (P_DONTCARE)
41#define P_PPI1_D5 (P_DONTCARE)
42#define P_PPI1_D6 (P_DONTCARE)
43#define P_PPI1_D7 (P_DONTCARE)
44#define P_SPORT1_TSCLK (P_DEFINED | P_IDENT(GPIO_PF31))
45#define P_SPORT1_RSCLK (P_DEFINED | P_IDENT(GPIO_PF30))
46#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(GPIO_PF29))
47#define P_SPORT0_RSCLK (P_DEFINED | P_IDENT(GPIO_PF28))
48#define P_UART0_RX (P_DEFINED | P_IDENT(GPIO_PF27))
49#define P_UART0_TX (P_DEFINED | P_IDENT(GPIO_PF26))
50#define P_SPORT1_DRSEC (P_DEFINED | P_IDENT(GPIO_PF25))
51#define P_SPORT1_RFS (P_DEFINED | P_IDENT(GPIO_PF24))
52#define P_SPORT1_DTPRI (P_DEFINED | P_IDENT(GPIO_PF23))
53#define P_SPORT1_DTSEC (P_DEFINED | P_IDENT(GPIO_PF22))
54#define P_SPORT1_TFS (P_DEFINED | P_IDENT(GPIO_PF21))
55#define P_SPORT1_DRPRI (P_DONTCARE)
56#define P_SPORT0_DRSEC (P_DEFINED | P_IDENT(GPIO_PF20))
57#define P_SPORT0_RFS (P_DEFINED | P_IDENT(GPIO_PF19))
58#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(GPIO_PF18))
59#define P_SPORT0_DTSEC (P_DEFINED | P_IDENT(GPIO_PF17))
60#define P_SPORT0_TFS (P_DEFINED | P_IDENT(GPIO_PF16))
61#define P_SPORT0_DRPRI (P_DONTCARE)
62#define P_TMRCLK (P_DEFINED | P_IDENT(GPIO_PF15))
63#define P_SPI0_SSEL7 (P_DEFINED | P_IDENT(GPIO_PF7))
64#define P_SPI0_SSEL6 (P_DEFINED | P_IDENT(GPIO_PF6))
65#define P_SPI0_SSEL5 (P_DEFINED | P_IDENT(GPIO_PF5))
66#define P_SPI0_SSEL4 (P_DEFINED | P_IDENT(GPIO_PF4))
67#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(GPIO_PF3))
68#define P_SPI0_SSEL2 (P_DEFINED | P_IDENT(GPIO_PF2))
69#define P_SPI0_SSEL1 (P_DEFINED | P_IDENT(GPIO_PF1))
70#define P_SPI0_SS (P_DEFINED | P_IDENT(GPIO_PF0))
71#define P_TMR11 (P_DONTCARE)
72#define P_TMR10 (P_DONTCARE)
73#define P_TMR9 (P_DONTCARE)
74#define P_TMR8 (P_DONTCARE)
75#define P_TMR7 (P_DEFINED | P_IDENT(GPIO_PF7))
76#define P_TMR6 (P_DEFINED | P_IDENT(GPIO_PF6))
77#define P_TMR5 (P_DEFINED | P_IDENT(GPIO_PF5))
78#define P_TMR4 (P_DEFINED | P_IDENT(GPIO_PF4))
79#define P_TMR3 (P_DEFINED | P_IDENT(GPIO_PF3))
80#define P_TMR2 (P_DEFINED | P_IDENT(GPIO_PF2))
81#define P_TMR1 (P_DEFINED | P_IDENT(GPIO_PF1))
82#define P_TMR0 (P_DEFINED | P_IDENT(GPIO_PF0))
83#define P_SPI0_MOSI (P_DONTCARE)
84#define P_SPI0_MIS0 (P_DONTCARE)
85#define P_SPI0_SCK (P_DONTCARE)
86
87#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h
new file mode 100644
index 000000000000..9d3681e42111
--- /dev/null
+++ b/include/asm-blackfin/portmux.h
@@ -0,0 +1,1133 @@
1/*
2 * Common header file for blackfin family of processors.
3 *
4 */
5
6#ifndef _PORTMUX_H_
7#define _PORTMUX_H_
8
9#define P_IDENT(x) ((x) & 0x1FF)
10#define P_FUNCT(x) (((x) & 0x3) << 9)
11#define P_FUNCT2MUX(x) (((x) >> 9) & 0x3)
12#define P_DEFINED 0x8000
13#define P_UNDEF 0x4000
14#define P_MAYSHARE 0x2000
15#define P_DONTCARE 0x1000
16
17#include <asm/gpio.h>
18#include <asm/mach/portmux.h>
19
20#ifndef P_SPORT2_TFS
21#define P_SPORT2_TFS P_UNDEF
22#endif
23
24#ifndef P_SPORT2_DTSEC
25#define P_SPORT2_DTSEC P_UNDEF
26#endif
27
28#ifndef P_SPORT2_DTPRI
29#define P_SPORT2_DTPRI P_UNDEF
30#endif
31
32#ifndef P_SPORT2_TSCLK
33#define P_SPORT2_TSCLK P_UNDEF
34#endif
35
36#ifndef P_SPORT2_RFS
37#define P_SPORT2_RFS P_UNDEF
38#endif
39
40#ifndef P_SPORT2_DRSEC
41#define P_SPORT2_DRSEC P_UNDEF
42#endif
43
44#ifndef P_SPORT2_DRPRI
45#define P_SPORT2_DRPRI P_UNDEF
46#endif
47
48#ifndef P_SPORT2_RSCLK
49#define P_SPORT2_RSCLK P_UNDEF
50#endif
51
52#ifndef P_SPORT3_TFS
53#define P_SPORT3_TFS P_UNDEF
54#endif
55
56#ifndef P_SPORT3_DTSEC
57#define P_SPORT3_DTSEC P_UNDEF
58#endif
59
60#ifndef P_SPORT3_DTPRI
61#define P_SPORT3_DTPRI P_UNDEF
62#endif
63
64#ifndef P_SPORT3_TSCLK
65#define P_SPORT3_TSCLK P_UNDEF
66#endif
67
68#ifndef P_SPORT3_RFS
69#define P_SPORT3_RFS P_UNDEF
70#endif
71
72#ifndef P_SPORT3_DRSEC
73#define P_SPORT3_DRSEC P_UNDEF
74#endif
75
76#ifndef P_SPORT3_DRPRI
77#define P_SPORT3_DRPRI P_UNDEF
78#endif
79
80#ifndef P_SPORT3_RSCLK
81#define P_SPORT3_RSCLK P_UNDEF
82#endif
83
84#ifndef P_TMR4
85#define P_TMR4 P_UNDEF
86#endif
87
88#ifndef P_TMR5
89#define P_TMR5 P_UNDEF
90#endif
91
92#ifndef P_TMR6
93#define P_TMR6 P_UNDEF
94#endif
95
96#ifndef P_TMR7
97#define P_TMR7 P_UNDEF
98#endif
99
100#ifndef P_TWI1_SCL
101#define P_TWI1_SCL P_UNDEF
102#endif
103
104#ifndef P_TWI1_SDA
105#define P_TWI1_SDA P_UNDEF
106#endif
107
108#ifndef P_UART3_RTS
109#define P_UART3_RTS P_UNDEF
110#endif
111
112#ifndef P_UART3_CTS
113#define P_UART3_CTS P_UNDEF
114#endif
115
116#ifndef P_UART2_TX
117#define P_UART2_TX P_UNDEF
118#endif
119
120#ifndef P_UART2_RX
121#define P_UART2_RX P_UNDEF
122#endif
123
124#ifndef P_UART3_TX
125#define P_UART3_TX P_UNDEF
126#endif
127
128#ifndef P_UART3_RX
129#define P_UART3_RX P_UNDEF
130#endif
131
132#ifndef P_SPI2_SS
133#define P_SPI2_SS P_UNDEF
134#endif
135
136#ifndef P_SPI2_SSEL1
137#define P_SPI2_SSEL1 P_UNDEF
138#endif
139
140#ifndef P_SPI2_SSEL2
141#define P_SPI2_SSEL2 P_UNDEF
142#endif
143
144#ifndef P_SPI2_SSEL3
145#define P_SPI2_SSEL3 P_UNDEF
146#endif
147
148#ifndef P_SPI2_SCK
149#define P_SPI2_SCK P_UNDEF
150#endif
151
152#ifndef P_SPI2_MOSI
153#define P_SPI2_MOSI P_UNDEF
154#endif
155
156#ifndef P_SPI2_MISO
157#define P_SPI2_MISO P_UNDEF
158#endif
159
160#ifndef P_TMR0
161#define P_TMR0 P_UNDEF
162#endif
163
164#ifndef P_TMR1
165#define P_TMR1 P_UNDEF
166#endif
167
168#ifndef P_TMR2
169#define P_TMR2 P_UNDEF
170#endif
171
172#ifndef P_TMR3
173#define P_TMR3 P_UNDEF
174#endif
175
176#ifndef P_SPORT0_TFS
177#define P_SPORT0_TFS P_UNDEF
178#endif
179
180#ifndef P_SPORT0_DTSEC
181#define P_SPORT0_DTSEC P_UNDEF
182#endif
183
184#ifndef P_SPORT0_DTPRI
185#define P_SPORT0_DTPRI P_UNDEF
186#endif
187
188#ifndef P_SPORT0_TSCLK
189#define P_SPORT0_TSCLK P_UNDEF
190#endif
191
192#ifndef P_SPORT0_RFS
193#define P_SPORT0_RFS P_UNDEF
194#endif
195
196#ifndef P_SPORT0_DRSEC
197#define P_SPORT0_DRSEC P_UNDEF
198#endif
199
200#ifndef P_SPORT0_DRPRI
201#define P_SPORT0_DRPRI P_UNDEF
202#endif
203
204#ifndef P_SPORT0_RSCLK
205#define P_SPORT0_RSCLK P_UNDEF
206#endif
207
208#ifndef P_SD_D0
209#define P_SD_D0 P_UNDEF
210#endif
211
212#ifndef P_SD_D1
213#define P_SD_D1 P_UNDEF
214#endif
215
216#ifndef P_SD_D2
217#define P_SD_D2 P_UNDEF
218#endif
219
220#ifndef P_SD_D3
221#define P_SD_D3 P_UNDEF
222#endif
223
224#ifndef P_SD_CLK
225#define P_SD_CLK P_UNDEF
226#endif
227
228#ifndef P_SD_CMD
229#define P_SD_CMD P_UNDEF
230#endif
231
232#ifndef P_MMCLK
233#define P_MMCLK P_UNDEF
234#endif
235
236#ifndef P_MBCLK
237#define P_MBCLK P_UNDEF
238#endif
239
240#ifndef P_PPI1_D0
241#define P_PPI1_D0 P_UNDEF
242#endif
243
244#ifndef P_PPI1_D1
245#define P_PPI1_D1 P_UNDEF
246#endif
247
248#ifndef P_PPI1_D2
249#define P_PPI1_D2 P_UNDEF
250#endif
251
252#ifndef P_PPI1_D3
253#define P_PPI1_D3 P_UNDEF
254#endif
255
256#ifndef P_PPI1_D4
257#define P_PPI1_D4 P_UNDEF
258#endif
259
260#ifndef P_PPI1_D5
261#define P_PPI1_D5 P_UNDEF
262#endif
263
264#ifndef P_PPI1_D6
265#define P_PPI1_D6 P_UNDEF
266#endif
267
268#ifndef P_PPI1_D7
269#define P_PPI1_D7 P_UNDEF
270#endif
271
272#ifndef P_PPI1_D8
273#define P_PPI1_D8 P_UNDEF
274#endif
275
276#ifndef P_PPI1_D9
277#define P_PPI1_D9 P_UNDEF
278#endif
279
280#ifndef P_PPI1_D10
281#define P_PPI1_D10 P_UNDEF
282#endif
283
284#ifndef P_PPI1_D11
285#define P_PPI1_D11 P_UNDEF
286#endif
287
288#ifndef P_PPI1_D12
289#define P_PPI1_D12 P_UNDEF
290#endif
291
292#ifndef P_PPI1_D13
293#define P_PPI1_D13 P_UNDEF
294#endif
295
296#ifndef P_PPI1_D14
297#define P_PPI1_D14 P_UNDEF
298#endif
299
300#ifndef P_PPI1_D15
301#define P_PPI1_D15 P_UNDEF
302#endif
303
304#ifndef P_HOST_D8
305#define P_HOST_D8 P_UNDEF
306#endif
307
308#ifndef P_HOST_D9
309#define P_HOST_D9 P_UNDEF
310#endif
311
312#ifndef P_HOST_D10
313#define P_HOST_D10 P_UNDEF
314#endif
315
316#ifndef P_HOST_D11
317#define P_HOST_D11 P_UNDEF
318#endif
319
320#ifndef P_HOST_D12
321#define P_HOST_D12 P_UNDEF
322#endif
323
324#ifndef P_HOST_D13
325#define P_HOST_D13 P_UNDEF
326#endif
327
328#ifndef P_HOST_D14
329#define P_HOST_D14 P_UNDEF
330#endif
331
332#ifndef P_HOST_D15
333#define P_HOST_D15 P_UNDEF
334#endif
335
336#ifndef P_HOST_D0
337#define P_HOST_D0 P_UNDEF
338#endif
339
340#ifndef P_HOST_D1
341#define P_HOST_D1 P_UNDEF
342#endif
343
344#ifndef P_HOST_D2
345#define P_HOST_D2 P_UNDEF
346#endif
347
348#ifndef P_HOST_D3
349#define P_HOST_D3 P_UNDEF
350#endif
351
352#ifndef P_HOST_D4
353#define P_HOST_D4 P_UNDEF
354#endif
355
356#ifndef P_HOST_D5
357#define P_HOST_D5 P_UNDEF
358#endif
359
360#ifndef P_HOST_D6
361#define P_HOST_D6 P_UNDEF
362#endif
363
364#ifndef P_HOST_D7
365#define P_HOST_D7 P_UNDEF
366#endif
367
368#ifndef P_SPORT1_TFS
369#define P_SPORT1_TFS P_UNDEF
370#endif
371
372#ifndef P_SPORT1_DTSEC
373#define P_SPORT1_DTSEC P_UNDEF
374#endif
375
376#ifndef P_SPORT1_DTPRI
377#define P_SPORT1_DTPRI P_UNDEF
378#endif
379
380#ifndef P_SPORT1_TSCLK
381#define P_SPORT1_TSCLK P_UNDEF
382#endif
383
384#ifndef P_SPORT1_RFS
385#define P_SPORT1_RFS P_UNDEF
386#endif
387
388#ifndef P_SPORT1_DRSEC
389#define P_SPORT1_DRSEC P_UNDEF
390#endif
391
392#ifndef P_SPORT1_DRPRI
393#define P_SPORT1_DRPRI P_UNDEF
394#endif
395
396#ifndef P_SPORT1_RSCLK
397#define P_SPORT1_RSCLK P_UNDEF
398#endif
399
400#ifndef P_PPI2_D0
401#define P_PPI2_D0 P_UNDEF
402#endif
403
404#ifndef P_PPI2_D1
405#define P_PPI2_D1 P_UNDEF
406#endif
407
408#ifndef P_PPI2_D2
409#define P_PPI2_D2 P_UNDEF
410#endif
411
412#ifndef P_PPI2_D3
413#define P_PPI2_D3 P_UNDEF
414#endif
415
416#ifndef P_PPI2_D4
417#define P_PPI2_D4 P_UNDEF
418#endif
419
420#ifndef P_PPI2_D5
421#define P_PPI2_D5 P_UNDEF
422#endif
423
424#ifndef P_PPI2_D6
425#define P_PPI2_D6 P_UNDEF
426#endif
427
428#ifndef P_PPI2_D7
429#define P_PPI2_D7 P_UNDEF
430#endif
431
432#ifndef P_PPI0_D18
433#define P_PPI0_D18 P_UNDEF
434#endif
435
436#ifndef P_PPI0_D19
437#define P_PPI0_D19 P_UNDEF
438#endif
439
440#ifndef P_PPI0_D20
441#define P_PPI0_D20 P_UNDEF
442#endif
443
444#ifndef P_PPI0_D21
445#define P_PPI0_D21 P_UNDEF
446#endif
447
448#ifndef P_PPI0_D22
449#define P_PPI0_D22 P_UNDEF
450#endif
451
452#ifndef P_PPI0_D23
453#define P_PPI0_D23 P_UNDEF
454#endif
455
456#ifndef P_KEY_ROW0
457#define P_KEY_ROW0 P_UNDEF
458#endif
459
460#ifndef P_KEY_ROW1
461#define P_KEY_ROW1 P_UNDEF
462#endif
463
464#ifndef P_KEY_ROW2
465#define P_KEY_ROW2 P_UNDEF
466#endif
467
468#ifndef P_KEY_ROW3
469#define P_KEY_ROW3 P_UNDEF
470#endif
471
472#ifndef P_KEY_COL0
473#define P_KEY_COL0 P_UNDEF
474#endif
475
476#ifndef P_KEY_COL1
477#define P_KEY_COL1 P_UNDEF
478#endif
479
480#ifndef P_KEY_COL2
481#define P_KEY_COL2 P_UNDEF
482#endif
483
484#ifndef P_KEY_COL3
485#define P_KEY_COL3 P_UNDEF
486#endif
487
488#ifndef P_SPI0_SCK
489#define P_SPI0_SCK P_UNDEF
490#endif
491
492#ifndef P_SPI0_MISO
493#define P_SPI0_MISO P_UNDEF
494#endif
495
496#ifndef P_SPI0_MOSI
497#define P_SPI0_MOSI P_UNDEF
498#endif
499
500#ifndef P_SPI0_SS
501#define P_SPI0_SS P_UNDEF
502#endif
503
504#ifndef P_SPI0_SSEL1
505#define P_SPI0_SSEL1 P_UNDEF
506#endif
507
508#ifndef P_SPI0_SSEL2
509#define P_SPI0_SSEL2 P_UNDEF
510#endif
511
512#ifndef P_SPI0_SSEL3
513#define P_SPI0_SSEL3 P_UNDEF
514#endif
515
516#ifndef P_UART0_TX
517#define P_UART0_TX P_UNDEF
518#endif
519
520#ifndef P_UART0_RX
521#define P_UART0_RX P_UNDEF
522#endif
523
524#ifndef P_UART1_RTS
525#define P_UART1_RTS P_UNDEF
526#endif
527
528#ifndef P_UART1_CTS
529#define P_UART1_CTS P_UNDEF
530#endif
531
532#ifndef P_PPI1_CLK
533#define P_PPI1_CLK P_UNDEF
534#endif
535
536#ifndef P_PPI1_FS1
537#define P_PPI1_FS1 P_UNDEF
538#endif
539
540#ifndef P_PPI1_FS2
541#define P_PPI1_FS2 P_UNDEF
542#endif
543
544#ifndef P_TWI0_SCL
545#define P_TWI0_SCL P_UNDEF
546#endif
547
548#ifndef P_TWI0_SDA
549#define P_TWI0_SDA P_UNDEF
550#endif
551
552#ifndef P_KEY_COL7
553#define P_KEY_COL7 P_UNDEF
554#endif
555
556#ifndef P_KEY_ROW6
557#define P_KEY_ROW6 P_UNDEF
558#endif
559
560#ifndef P_KEY_COL6
561#define P_KEY_COL6 P_UNDEF
562#endif
563
564#ifndef P_KEY_ROW5
565#define P_KEY_ROW5 P_UNDEF
566#endif
567
568#ifndef P_KEY_COL5
569#define P_KEY_COL5 P_UNDEF
570#endif
571
572#ifndef P_KEY_ROW4
573#define P_KEY_ROW4 P_UNDEF
574#endif
575
576#ifndef P_KEY_COL4
577#define P_KEY_COL4 P_UNDEF
578#endif
579
580#ifndef P_KEY_ROW7
581#define P_KEY_ROW7 P_UNDEF
582#endif
583
584#ifndef P_PPI0_D0
585#define P_PPI0_D0 P_UNDEF
586#endif
587
588#ifndef P_PPI0_D1
589#define P_PPI0_D1 P_UNDEF
590#endif
591
592#ifndef P_PPI0_D2
593#define P_PPI0_D2 P_UNDEF
594#endif
595
596#ifndef P_PPI0_D3
597#define P_PPI0_D3 P_UNDEF
598#endif
599
600#ifndef P_PPI0_D4
601#define P_PPI0_D4 P_UNDEF
602#endif
603
604#ifndef P_PPI0_D5
605#define P_PPI0_D5 P_UNDEF
606#endif
607
608#ifndef P_PPI0_D6
609#define P_PPI0_D6 P_UNDEF
610#endif
611
612#ifndef P_PPI0_D7
613#define P_PPI0_D7 P_UNDEF
614#endif
615
616#ifndef P_PPI0_D8
617#define P_PPI0_D8 P_UNDEF
618#endif
619
620#ifndef P_PPI0_D9
621#define P_PPI0_D9 P_UNDEF
622#endif
623
624#ifndef P_PPI0_D10
625#define P_PPI0_D10 P_UNDEF
626#endif
627
628#ifndef P_PPI0_D11
629#define P_PPI0_D11 P_UNDEF
630#endif
631
632#ifndef P_PPI0_D12
633#define P_PPI0_D12 P_UNDEF
634#endif
635
636#ifndef P_PPI0_D13
637#define P_PPI0_D13 P_UNDEF
638#endif
639
640#ifndef P_PPI0_D14
641#define P_PPI0_D14 P_UNDEF
642#endif
643
644#ifndef P_PPI0_D15
645#define P_PPI0_D15 P_UNDEF
646#endif
647
648#ifndef P_ATAPI_D0A
649#define P_ATAPI_D0A P_UNDEF
650#endif
651
652#ifndef P_ATAPI_D1A
653#define P_ATAPI_D1A P_UNDEF
654#endif
655
656#ifndef P_ATAPI_D2A
657#define P_ATAPI_D2A P_UNDEF
658#endif
659
660#ifndef P_ATAPI_D3A
661#define P_ATAPI_D3A P_UNDEF
662#endif
663
664#ifndef P_ATAPI_D4A
665#define P_ATAPI_D4A P_UNDEF
666#endif
667
668#ifndef P_ATAPI_D5A
669#define P_ATAPI_D5A P_UNDEF
670#endif
671
672#ifndef P_ATAPI_D6A
673#define P_ATAPI_D6A P_UNDEF
674#endif
675
676#ifndef P_ATAPI_D7A
677#define P_ATAPI_D7A P_UNDEF
678#endif
679
680#ifndef P_ATAPI_D8A
681#define P_ATAPI_D8A P_UNDEF
682#endif
683
684#ifndef P_ATAPI_D9A
685#define P_ATAPI_D9A P_UNDEF
686#endif
687
688#ifndef P_ATAPI_D10A
689#define P_ATAPI_D10A P_UNDEF
690#endif
691
692#ifndef P_ATAPI_D11A
693#define P_ATAPI_D11A P_UNDEF
694#endif
695
696#ifndef P_ATAPI_D12A
697#define P_ATAPI_D12A P_UNDEF
698#endif
699
700#ifndef P_ATAPI_D13A
701#define P_ATAPI_D13A P_UNDEF
702#endif
703
704#ifndef P_ATAPI_D14A
705#define P_ATAPI_D14A P_UNDEF
706#endif
707
708#ifndef P_ATAPI_D15A
709#define P_ATAPI_D15A P_UNDEF
710#endif
711
712#ifndef P_PPI0_CLK
713#define P_PPI0_CLK P_UNDEF
714#endif
715
716#ifndef P_PPI0_FS1
717#define P_PPI0_FS1 P_UNDEF
718#endif
719
720#ifndef P_PPI0_FS2
721#define P_PPI0_FS2 P_UNDEF
722#endif
723
724#ifndef P_PPI0_D16
725#define P_PPI0_D16 P_UNDEF
726#endif
727
728#ifndef P_PPI0_D17
729#define P_PPI0_D17 P_UNDEF
730#endif
731
732#ifndef P_SPI1_SSEL1
733#define P_SPI1_SSEL1 P_UNDEF
734#endif
735
736#ifndef P_SPI1_SSEL2
737#define P_SPI1_SSEL2 P_UNDEF
738#endif
739
740#ifndef P_SPI1_SSEL3
741#define P_SPI1_SSEL3 P_UNDEF
742#endif
743
744#ifndef P_SPI1_SCK
745#define P_SPI1_SCK P_UNDEF
746#endif
747
748#ifndef P_SPI1_MISO
749#define P_SPI1_MISO P_UNDEF
750#endif
751
752#ifndef P_SPI1_MOSI
753#define P_SPI1_MOSI P_UNDEF
754#endif
755
756#ifndef P_SPI1_SS
757#define P_SPI1_SS P_UNDEF
758#endif
759
760#ifndef P_CAN0_TX
761#define P_CAN0_TX P_UNDEF
762#endif
763
764#ifndef P_CAN0_RX
765#define P_CAN0_RX P_UNDEF
766#endif
767
768#ifndef P_CAN1_TX
769#define P_CAN1_TX P_UNDEF
770#endif
771
772#ifndef P_CAN1_RX
773#define P_CAN1_RX P_UNDEF
774#endif
775
776#ifndef P_ATAPI_A0A
777#define P_ATAPI_A0A P_UNDEF
778#endif
779
780#ifndef P_ATAPI_A1A
781#define P_ATAPI_A1A P_UNDEF
782#endif
783
784#ifndef P_ATAPI_A2A
785#define P_ATAPI_A2A P_UNDEF
786#endif
787
788#ifndef P_HOST_CE
789#define P_HOST_CE P_UNDEF
790#endif
791
792#ifndef P_HOST_RD
793#define P_HOST_RD P_UNDEF
794#endif
795
796#ifndef P_HOST_WR
797#define P_HOST_WR P_UNDEF
798#endif
799
800#ifndef P_MTXONB
801#define P_MTXONB P_UNDEF
802#endif
803
804#ifndef P_PPI2_FS2
805#define P_PPI2_FS2 P_UNDEF
806#endif
807
808#ifndef P_PPI2_FS1
809#define P_PPI2_FS1 P_UNDEF
810#endif
811
812#ifndef P_PPI2_CLK
813#define P_PPI2_CLK P_UNDEF
814#endif
815
816#ifndef P_CNT_CZM
817#define P_CNT_CZM P_UNDEF
818#endif
819
820#ifndef P_UART1_TX
821#define P_UART1_TX P_UNDEF
822#endif
823
824#ifndef P_UART1_RX
825#define P_UART1_RX P_UNDEF
826#endif
827
828#ifndef P_ATAPI_RESET
829#define P_ATAPI_RESET P_UNDEF
830#endif
831
832#ifndef P_HOST_ADDR
833#define P_HOST_ADDR P_UNDEF
834#endif
835
836#ifndef P_HOST_ACK
837#define P_HOST_ACK P_UNDEF
838#endif
839
840#ifndef P_MTX
841#define P_MTX P_UNDEF
842#endif
843
844#ifndef P_MRX
845#define P_MRX P_UNDEF
846#endif
847
848#ifndef P_MRXONB
849#define P_MRXONB P_UNDEF
850#endif
851
852#ifndef P_A4
853#define P_A4 P_UNDEF
854#endif
855
856#ifndef P_A5
857#define P_A5 P_UNDEF
858#endif
859
860#ifndef P_A6
861#define P_A6 P_UNDEF
862#endif
863
864#ifndef P_A7
865#define P_A7 P_UNDEF
866#endif
867
868#ifndef P_A8
869#define P_A8 P_UNDEF
870#endif
871
872#ifndef P_A9
873#define P_A9 P_UNDEF
874#endif
875
876#ifndef P_PPI1_FS3
877#define P_PPI1_FS3 P_UNDEF
878#endif
879
880#ifndef P_PPI2_FS3
881#define P_PPI2_FS3 P_UNDEF
882#endif
883
884#ifndef P_TMR8
885#define P_TMR8 P_UNDEF
886#endif
887
888#ifndef P_TMR9
889#define P_TMR9 P_UNDEF
890#endif
891
892#ifndef P_TMR10
893#define P_TMR10 P_UNDEF
894#endif
895#ifndef P_TMR11
896#define P_TMR11 P_UNDEF
897#endif
898
899#ifndef P_DMAR0
900#define P_DMAR0 P_UNDEF
901#endif
902
903#ifndef P_DMAR1
904#define P_DMAR1 P_UNDEF
905#endif
906
907#ifndef P_PPI0_FS3
908#define P_PPI0_FS3 P_UNDEF
909#endif
910
911#ifndef P_CNT_CDG
912#define P_CNT_CDG P_UNDEF
913#endif
914
915#ifndef P_CNT_CUD
916#define P_CNT_CUD P_UNDEF
917#endif
918
919#ifndef P_A10
920#define P_A10 P_UNDEF
921#endif
922
923#ifndef P_A11
924#define P_A11 P_UNDEF
925#endif
926
927#ifndef P_A12
928#define P_A12 P_UNDEF
929#endif
930
931#ifndef P_A13
932#define P_A13 P_UNDEF
933#endif
934
935#ifndef P_A14
936#define P_A14 P_UNDEF
937#endif
938
939#ifndef P_A15
940#define P_A15 P_UNDEF
941#endif
942
943#ifndef P_A16
944#define P_A16 P_UNDEF
945#endif
946
947#ifndef P_A17
948#define P_A17 P_UNDEF
949#endif
950
951#ifndef P_A18
952#define P_A18 P_UNDEF
953#endif
954
955#ifndef P_A19
956#define P_A19 P_UNDEF
957#endif
958
959#ifndef P_A20
960#define P_A20 P_UNDEF
961#endif
962
963#ifndef P_A21
964#define P_A21 P_UNDEF
965#endif
966
967#ifndef P_A22
968#define P_A22 P_UNDEF
969#endif
970
971#ifndef P_A23
972#define P_A23 P_UNDEF
973#endif
974
975#ifndef P_A24
976#define P_A24 P_UNDEF
977#endif
978
979#ifndef P_A25
980#define P_A25 P_UNDEF
981#endif
982
983#ifndef P_NOR_CLK
984#define P_NOR_CLK P_UNDEF
985#endif
986
987#ifndef P_TMRCLK
988#define P_TMRCLK P_UNDEF
989#endif
990
991#ifndef P_AMC_ARDY_NOR_WAIT
992#define P_AMC_ARDY_NOR_WAIT P_UNDEF
993#endif
994
995#ifndef P_NAND_CE
996#define P_NAND_CE P_UNDEF
997#endif
998
999#ifndef P_NAND_RB
1000#define P_NAND_RB P_UNDEF
1001#endif
1002
1003#ifndef P_ATAPI_DIOR
1004#define P_ATAPI_DIOR P_UNDEF
1005#endif
1006
1007#ifndef P_ATAPI_DIOW
1008#define P_ATAPI_DIOW P_UNDEF
1009#endif
1010
1011#ifndef P_ATAPI_CS0
1012#define P_ATAPI_CS0 P_UNDEF
1013#endif
1014
1015#ifndef P_ATAPI_CS1
1016#define P_ATAPI_CS1 P_UNDEF
1017#endif
1018
1019#ifndef P_ATAPI_DMACK
1020#define P_ATAPI_DMACK P_UNDEF
1021#endif
1022
1023#ifndef P_ATAPI_DMARQ
1024#define P_ATAPI_DMARQ P_UNDEF
1025#endif
1026
1027#ifndef P_ATAPI_INTRQ
1028#define P_ATAPI_INTRQ P_UNDEF
1029#endif
1030
1031#ifndef P_ATAPI_IORDY
1032#define P_ATAPI_IORDY P_UNDEF
1033#endif
1034
1035#ifndef P_AMC_BR
1036#define P_AMC_BR P_UNDEF
1037#endif
1038
1039#ifndef P_AMC_BG
1040#define P_AMC_BG P_UNDEF
1041#endif
1042
1043#ifndef P_AMC_BGH
1044#define P_AMC_BGH P_UNDEF
1045#endif
1046
1047/* EMAC */
1048
1049#ifndef P_MII0_ETxD0
1050#define P_MII0_ETxD0 P_UNDEF
1051#endif
1052
1053#ifndef P_MII0_ETxD1
1054#define P_MII0_ETxD1 P_UNDEF
1055#endif
1056
1057#ifndef P_MII0_ETxD2
1058#define P_MII0_ETxD2 P_UNDEF
1059#endif
1060
1061#ifndef P_MII0_ETxD3
1062#define P_MII0_ETxD3 P_UNDEF
1063#endif
1064
1065#ifndef P_MII0_ETxEN
1066#define P_MII0_ETxEN P_UNDEF
1067#endif
1068
1069#ifndef P_MII0_TxCLK
1070#define P_MII0_TxCLK P_UNDEF
1071#endif
1072
1073#ifndef P_MII0_PHYINT
1074#define P_MII0_PHYINT P_UNDEF
1075#endif
1076
1077#ifndef P_MII0_COL
1078#define P_MII0_COL P_UNDEF
1079#endif
1080
1081#ifndef P_MII0_ERxD0
1082#define P_MII0_ERxD0 P_UNDEF
1083#endif
1084
1085#ifndef P_MII0_ERxD1
1086#define P_MII0_ERxD1 P_UNDEF
1087#endif
1088
1089#ifndef P_MII0_ERxD2
1090#define P_MII0_ERxD2 P_UNDEF
1091#endif
1092
1093#ifndef P_MII0_ERxD3
1094#define P_MII0_ERxD3 P_UNDEF
1095#endif
1096
1097#ifndef P_MII0_ERxDV
1098#define P_MII0_ERxDV P_UNDEF
1099#endif
1100
1101#ifndef P_MII0_ERxCLK
1102#define P_MII0_ERxCLK P_UNDEF
1103#endif
1104
1105#ifndef P_MII0_ERxER
1106#define P_MII0_ERxER P_UNDEF
1107#endif
1108
1109#ifndef P_MII0_CRS
1110#define P_MII0_CRS P_UNDEF
1111#endif
1112
1113#ifndef P_RMII0_REF_CLK
1114#define P_RMII0_REF_CLK P_UNDEF
1115#endif
1116
1117#ifndef P_RMII0_MDINT
1118#define P_RMII0_MDINT P_UNDEF
1119#endif
1120
1121#ifndef P_RMII0_CRS_DV
1122#define P_RMII0_CRS_DV P_UNDEF
1123#endif
1124
1125#ifndef P_MDC
1126#define P_MDC P_UNDEF
1127#endif
1128
1129#ifndef P_MDIO
1130#define P_MDIO P_UNDEF
1131#endif
1132
1133#endif /* _PORTMUX_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 14:46:20 -0500