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-rw-r--r--arch/powerpc/boot/dts/gef_sbc610.dts260
-rw-r--r--arch/powerpc/platforms/86xx/Kconfig9
-rw-r--r--arch/powerpc/platforms/86xx/Makefile1
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc610.c149
4 files changed, 418 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/gef_sbc610.dts b/arch/powerpc/boot/dts/gef_sbc610.dts
new file mode 100644
index 000000000000..80b79e4adc78
--- /dev/null
+++ b/arch/powerpc/boot/dts/gef_sbc610.dts
@@ -0,0 +1,260 @@
1/*
2 * GE Fanuc SBC610 Device Tree Source
3 *
4 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Based on: SBS CM6 Device Tree Source
12 * Copyright 2007 SBS Technologies GmbH & Co. KG
13 * And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17/*
18 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
19 */
20
21/dts-v1/;
22
23/ {
24 model = "GEF_SBC610";
25 compatible = "gef,sbc610";
26 #address-cells = <1>;
27 #size-cells = <1>;
28
29 aliases {
30 ethernet0 = &enet0;
31 ethernet1 = &enet1;
32 serial0 = &serial0;
33 serial1 = &serial1;
34 pci0 = &pci0;
35 };
36
37 cpus {
38 #address-cells = <1>;
39 #size-cells = <0>;
40
41 PowerPC,8641@0 {
42 device_type = "cpu";
43 reg = <0>;
44 d-cache-line-size = <32>; // 32 bytes
45 i-cache-line-size = <32>; // 32 bytes
46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
48 timebase-frequency = <0>; // From uboot
49 bus-frequency = <0>; // From uboot
50 clock-frequency = <0>; // From uboot
51 };
52 PowerPC,8641@1 {
53 device_type = "cpu";
54 reg = <1>;
55 d-cache-line-size = <32>; // 32 bytes
56 i-cache-line-size = <32>; // 32 bytes
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
59 timebase-frequency = <0>; // From uboot
60 bus-frequency = <0>; // From uboot
61 clock-frequency = <0>; // From uboot
62 };
63 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x0 0x40000000>; // set by uboot
68 };
69
70 soc@fef00000 {
71 #address-cells = <1>;
72 #size-cells = <1>;
73 #interrupt-cells = <2>;
74 device_type = "soc";
75 compatible = "simple-bus";
76 ranges = <0x0 0xfef00000 0x00100000>;
77 reg = <0xfef00000 0x100000>; // CCSRBAR 1M
78 bus-frequency = <0>;
79
80 i2c1: i2c@3000 {
81 #address-cells = <1>;
82 #size-cells = <0>;
83 compatible = "fsl-i2c";
84 reg = <0x3000 0x100>;
85 interrupts = <0x2b 0x2>;
86 interrupt-parent = <&mpic>;
87 dfsrr;
88
89 eti@6b {
90 compatible = "dallas,ds1682";
91 reg = <0x6b>;
92 };
93 };
94
95 i2c2: i2c@3100 {
96 #address-cells = <1>;
97 #size-cells = <0>;
98 compatible = "fsl-i2c";
99 reg = <0x3100 0x100>;
100 interrupts = <0x2b 0x2>;
101 interrupt-parent = <&mpic>;
102 dfsrr;
103 };
104
105 dma@21300 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
109 reg = <0x21300 0x4>;
110 ranges = <0x0 0x21100 0x200>;
111 cell-index = <0>;
112 dma-channel@0 {
113 compatible = "fsl,mpc8641-dma-channel",
114 "fsl,eloplus-dma-channel";
115 reg = <0x0 0x80>;
116 cell-index = <0>;
117 interrupt-parent = <&mpic>;
118 interrupts = <20 2>;
119 };
120 dma-channel@80 {
121 compatible = "fsl,mpc8641-dma-channel",
122 "fsl,eloplus-dma-channel";
123 reg = <0x80 0x80>;
124 cell-index = <1>;
125 interrupt-parent = <&mpic>;
126 interrupts = <21 2>;
127 };
128 dma-channel@100 {
129 compatible = "fsl,mpc8641-dma-channel",
130 "fsl,eloplus-dma-channel";
131 reg = <0x100 0x80>;
132 cell-index = <2>;
133 interrupt-parent = <&mpic>;
134 interrupts = <22 2>;
135 };
136 dma-channel@180 {
137 compatible = "fsl,mpc8641-dma-channel",
138 "fsl,eloplus-dma-channel";
139 reg = <0x180 0x80>;
140 cell-index = <3>;
141 interrupt-parent = <&mpic>;
142 interrupts = <23 2>;
143 };
144 };
145
146 mdio@24520 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,gianfar-mdio";
150 reg = <0x24520 0x20>;
151
152 phy0: ethernet-phy@0 {
153 interrupt-parent = <&mpic>;
154 interrupts = <0x0 0x1>;
155 reg = <1>;
156 };
157 phy2: ethernet-phy@2 {
158 interrupt-parent = <&mpic>;
159 interrupts = <0x0 0x1>;
160 reg = <3>;
161 };
162 };
163
164 enet0: ethernet@24000 {
165 device_type = "network";
166 model = "eTSEC";
167 compatible = "gianfar";
168 reg = <0x24000 0x1000>;
169 local-mac-address = [ 00 00 00 00 00 00 ];
170 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
171 interrupt-parent = <&mpic>;
172 phy-handle = <&phy0>;
173 phy-connection-type = "gmii";
174 };
175
176 enet1: ethernet@26000 {
177 device_type = "network";
178 model = "eTSEC";
179 compatible = "gianfar";
180 reg = <0x26000 0x1000>;
181 local-mac-address = [ 00 00 00 00 00 00 ];
182 interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
183 interrupt-parent = <&mpic>;
184 phy-handle = <&phy2>;
185 phy-connection-type = "gmii";
186 };
187
188 serial0: serial@4500 {
189 cell-index = <0>;
190 device_type = "serial";
191 compatible = "ns16550";
192 reg = <0x4500 0x100>;
193 clock-frequency = <0>;
194 interrupts = <0x2a 0x2>;
195 interrupt-parent = <&mpic>;
196 };
197
198 serial1: serial@4600 {
199 cell-index = <1>;
200 device_type = "serial";
201 compatible = "ns16550";
202 reg = <0x4600 0x100>;
203 clock-frequency = <0>;
204 interrupts = <0x1c 0x2>;
205 interrupt-parent = <&mpic>;
206 };
207
208 mpic: pic@40000 {
209 clock-frequency = <0>;
210 interrupt-controller;
211 #address-cells = <0>;
212 #interrupt-cells = <2>;
213 reg = <0x40000 0x40000>;
214 compatible = "chrp,open-pic";
215 device_type = "open-pic";
216 };
217
218 global-utilities@e0000 {
219 compatible = "fsl,mpc8641-guts";
220 reg = <0xe0000 0x1000>;
221 fsl,has-rstcr;
222 };
223 };
224
225 pci0: pcie@fef08000 {
226 compatible = "fsl,mpc8641-pcie";
227 device_type = "pci";
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <0xfef08000 0x1000>;
232 bus-range = <0x0 0xff>;
233 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
234 0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
235 clock-frequency = <33333333>;
236 interrupt-parent = <&mpic>;
237 interrupts = <0x18 0x2>;
238 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
239 interrupt-map = <
240 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
241 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
242 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
243 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1
244 >;
245
246 pcie@0 {
247 reg = <0 0 0 0 0>;
248 #size-cells = <2>;
249 #address-cells = <3>;
250 device_type = "pci";
251 ranges = <0x02000000 0x0 0x80000000
252 0x02000000 0x0 0x80000000
253 0x0 0x40000000
254
255 0x01000000 0x0 0x00000000
256 0x01000000 0x0 0x00000000
257 0x0 0x00400000>;
258 };
259 };
260};
diff --git a/arch/powerpc/platforms/86xx/Kconfig b/arch/powerpc/platforms/86xx/Kconfig
index 9355a5269431..77dd797a2580 100644
--- a/arch/powerpc/platforms/86xx/Kconfig
+++ b/arch/powerpc/platforms/86xx/Kconfig
@@ -31,6 +31,13 @@ config MPC8610_HPCD
31 help 31 help
32 This option enables support for the MPC8610 HPCD board. 32 This option enables support for the MPC8610 HPCD board.
33 33
34config GEF_SBC610
35 bool "GE Fanuc SBC610"
36 select DEFAULT_UIMAGE
37 select HAS_RAPIDIO
38 help
39 This option enables support for GE Fanuc's SBC610.
40
34endif 41endif
35 42
36config MPC8641 43config MPC8641
@@ -39,7 +46,7 @@ config MPC8641
39 select FSL_PCI if PCI 46 select FSL_PCI if PCI
40 select PPC_UDBG_16550 47 select PPC_UDBG_16550
41 select MPIC 48 select MPIC
42 default y if MPC8641_HPCN || SBC8641D 49 default y if MPC8641_HPCN || SBC8641D || GEF_SBC610
43 50
44config MPC8610 51config MPC8610
45 bool 52 bool
diff --git a/arch/powerpc/platforms/86xx/Makefile b/arch/powerpc/platforms/86xx/Makefile
index 8fee37dec795..cb9fc8f4360b 100644
--- a/arch/powerpc/platforms/86xx/Makefile
+++ b/arch/powerpc/platforms/86xx/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_SMP) += mpc86xx_smp.o
7obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o 7obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
8obj-$(CONFIG_SBC8641D) += sbc8641d.o 8obj-$(CONFIG_SBC8641D) += sbc8641d.o
9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o 9obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
10obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
new file mode 100644
index 000000000000..3543a9e67618
--- /dev/null
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -0,0 +1,149 @@
1/*
2 * GE Fanuc SBC610 board support
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 *
6 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Based on: mpc86xx_hpcn.c (MPC86xx HPCN board specific routines)
14 * Copyright 2006 Freescale Semiconductor Inc.
15 */
16
17#include <linux/stddef.h>
18#include <linux/kernel.h>
19#include <linux/pci.h>
20#include <linux/kdev_t.h>
21#include <linux/delay.h>
22#include <linux/seq_file.h>
23#include <linux/of_platform.h>
24
25#include <asm/system.h>
26#include <asm/time.h>
27#include <asm/machdep.h>
28#include <asm/pci-bridge.h>
29#include <asm/mpc86xx.h>
30#include <asm/prom.h>
31#include <mm/mmu_decl.h>
32#include <asm/udbg.h>
33
34#include <asm/mpic.h>
35
36#include <sysdev/fsl_pci.h>
37#include <sysdev/fsl_soc.h>
38
39#include "mpc86xx.h"
40
41#undef DEBUG
42
43#ifdef DEBUG
44#define DBG (fmt...) do { printk(KERN_ERR "SBC610: " fmt); } while (0)
45#else
46#define DBG (fmt...) do { } while (0)
47#endif
48
49static void __init gef_sbc610_setup_arch(void)
50{
51#ifdef CONFIG_PCI
52 struct device_node *np;
53
54 for_each_compatible_node(np, "pci", "fsl,mpc8641-pcie") {
55 fsl_add_bridge(np, 1);
56 }
57#endif
58
59 printk(KERN_INFO "GE Fanuc Intelligent Platforms SBC610 6U VPX SBC\n");
60
61#ifdef CONFIG_SMP
62 mpc86xx_smp_init();
63#endif
64}
65
66
67static void gef_sbc610_show_cpuinfo(struct seq_file *m)
68{
69 struct device_node *root;
70 uint memsize = total_memory;
71 const char *model = "";
72 uint svid = mfspr(SPRN_SVR);
73
74 seq_printf(m, "Vendor\t\t: GE Fanuc Intelligent Platforms\n");
75
76 root = of_find_node_by_path("/");
77 if (root)
78 model = of_get_property(root, "model", NULL);
79 seq_printf(m, "Machine\t\t: %s\n", model);
80 of_node_put(root);
81
82 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
83 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
84}
85
86
87/*
88 * Called very early, device-tree isn't unflattened
89 *
90 * This function is called to determine whether the BSP is compatible with the
91 * supplied device-tree, which is assumed to be the correct one for the actual
92 * board. It is expected thati, in the future, a kernel may support multiple
93 * boards.
94 */
95static int __init gef_sbc610_probe(void)
96{
97 unsigned long root = of_get_flat_dt_root();
98
99 if (of_flat_dt_is_compatible(root, "gef,sbc610"))
100 return 1;
101
102 return 0;
103}
104
105static long __init mpc86xx_time_init(void)
106{
107 unsigned int temp;
108
109 /* Set the time base to zero */
110 mtspr(SPRN_TBWL, 0);
111 mtspr(SPRN_TBWU, 0);
112
113 temp = mfspr(SPRN_HID0);
114 temp |= HID0_TBEN;
115 mtspr(SPRN_HID0, temp);
116 asm volatile("isync");
117
118 return 0;
119}
120
121static __initdata struct of_device_id of_bus_ids[] = {
122 { .compatible = "simple-bus", },
123 {},
124};
125
126static int __init declare_of_platform_devices(void)
127{
128 printk(KERN_DEBUG "Probe platform devices\n");
129 of_platform_bus_probe(NULL, of_bus_ids, NULL);
130
131 return 0;
132}
133machine_device_initcall(gef_sbc610, declare_of_platform_devices);
134
135define_machine(gef_sbc610) {
136 .name = "GE Fanuc SBC610",
137 .probe = gef_sbc610_probe,
138 .setup_arch = gef_sbc610_setup_arch,
139 .init_IRQ = mpc86xx_init_irq,
140 .show_cpuinfo = gef_sbc610_show_cpuinfo,
141 .get_irq = mpic_get_irq,
142 .restart = fsl_rstcr_restart,
143 .time_init = mpc86xx_time_init,
144 .calibrate_decr = generic_calibrate_decr,
145 .progress = udbg_progress,
146#ifdef CONFIG_PCI
147 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
148#endif
149};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 10:44:44 -0500