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-rw-r--r--drivers/gpio/gpio-omap.c47
1 files changed, 25 insertions, 22 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 7cbad8569268..1adc2ec1e383 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -120,10 +120,13 @@ static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
120 void __iomem *reg = bank->base; 120 void __iomem *reg = bank->base;
121 u32 l = GPIO_BIT(bank, gpio); 121 u32 l = GPIO_BIT(bank, gpio);
122 122
123 if (enable) 123 if (enable) {
124 reg += bank->regs->set_dataout; 124 reg += bank->regs->set_dataout;
125 else 125 bank->context.dataout |= l;
126 } else {
126 reg += bank->regs->clr_dataout; 127 reg += bank->regs->clr_dataout;
128 bank->context.dataout &= ~l;
129 }
127 130
128 __raw_writel(l, reg); 131 __raw_writel(l, reg);
129} 132}
@@ -144,18 +147,18 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
144 bank->context.dataout = l; 147 bank->context.dataout = l;
145} 148}
146 149
147static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 150static int _get_gpio_datain(struct gpio_bank *bank, int offset)
148{ 151{
149 void __iomem *reg = bank->base + bank->regs->datain; 152 void __iomem *reg = bank->base + bank->regs->datain;
150 153
151 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; 154 return (__raw_readl(reg) & (1 << offset)) != 0;
152} 155}
153 156
154static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) 157static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
155{ 158{
156 void __iomem *reg = bank->base + bank->regs->dataout; 159 void __iomem *reg = bank->base + bank->regs->dataout;
157 160
158 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; 161 return (__raw_readl(reg) & (1 << offset)) != 0;
159} 162}
160 163
161static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) 164static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
@@ -245,7 +248,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
245} 248}
246 249
247static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio, 250static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
248 int trigger) 251 unsigned trigger)
249{ 252{
250 void __iomem *base = bank->base; 253 void __iomem *base = bank->base;
251 u32 gpio_bit = 1 << gpio; 254 u32 gpio_bit = 1 << gpio;
@@ -327,7 +330,8 @@ static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
327static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} 330static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
328#endif 331#endif
329 332
330static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 333static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
334 unsigned trigger)
331{ 335{
332 void __iomem *reg = bank->base; 336 void __iomem *reg = bank->base;
333 void __iomem *base = bank->base; 337 void __iomem *base = bank->base;
@@ -447,6 +451,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
447 if (bank->regs->set_irqenable) { 451 if (bank->regs->set_irqenable) {
448 reg += bank->regs->set_irqenable; 452 reg += bank->regs->set_irqenable;
449 l = gpio_mask; 453 l = gpio_mask;
454 bank->context.irqenable1 |= gpio_mask;
450 } else { 455 } else {
451 reg += bank->regs->irqenable; 456 reg += bank->regs->irqenable;
452 l = __raw_readl(reg); 457 l = __raw_readl(reg);
@@ -454,10 +459,10 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
454 l &= ~gpio_mask; 459 l &= ~gpio_mask;
455 else 460 else
456 l |= gpio_mask; 461 l |= gpio_mask;
462 bank->context.irqenable1 = l;
457 } 463 }
458 464
459 __raw_writel(l, reg); 465 __raw_writel(l, reg);
460 bank->context.irqenable1 = l;
461} 466}
462 467
463static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 468static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -468,6 +473,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
468 if (bank->regs->clr_irqenable) { 473 if (bank->regs->clr_irqenable) {
469 reg += bank->regs->clr_irqenable; 474 reg += bank->regs->clr_irqenable;
470 l = gpio_mask; 475 l = gpio_mask;
476 bank->context.irqenable1 &= ~gpio_mask;
471 } else { 477 } else {
472 reg += bank->regs->irqenable; 478 reg += bank->regs->irqenable;
473 l = __raw_readl(reg); 479 l = __raw_readl(reg);
@@ -475,15 +481,18 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
475 l |= gpio_mask; 481 l |= gpio_mask;
476 else 482 else
477 l &= ~gpio_mask; 483 l &= ~gpio_mask;
484 bank->context.irqenable1 = l;
478 } 485 }
479 486
480 __raw_writel(l, reg); 487 __raw_writel(l, reg);
481 bank->context.irqenable1 = l;
482} 488}
483 489
484static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 490static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
485{ 491{
486 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); 492 if (enable)
493 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
494 else
495 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
487} 496}
488 497
489/* 498/*
@@ -511,6 +520,7 @@ static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
511 else 520 else
512 bank->suspend_wakeup &= ~gpio_bit; 521 bank->suspend_wakeup &= ~gpio_bit;
513 522
523 __raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
514 spin_unlock_irqrestore(&bank->lock, flags); 524 spin_unlock_irqrestore(&bank->lock, flags);
515 525
516 return 0; 526 return 0;
@@ -855,19 +865,15 @@ static int gpio_is_input(struct gpio_bank *bank, int mask)
855static int gpio_get(struct gpio_chip *chip, unsigned offset) 865static int gpio_get(struct gpio_chip *chip, unsigned offset)
856{ 866{
857 struct gpio_bank *bank; 867 struct gpio_bank *bank;
858 void __iomem *reg;
859 int gpio;
860 u32 mask; 868 u32 mask;
861 869
862 gpio = chip->base + offset;
863 bank = container_of(chip, struct gpio_bank, chip); 870 bank = container_of(chip, struct gpio_bank, chip);
864 reg = bank->base; 871 mask = (1 << offset);
865 mask = GPIO_BIT(bank, gpio);
866 872
867 if (gpio_is_input(bank, mask)) 873 if (gpio_is_input(bank, mask))
868 return _get_gpio_datain(bank, gpio); 874 return _get_gpio_datain(bank, offset);
869 else 875 else
870 return _get_gpio_dataout(bank, gpio); 876 return _get_gpio_dataout(bank, offset);
871} 877}
872 878
873static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) 879static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
@@ -1239,9 +1245,6 @@ static int omap_gpio_runtime_suspend(struct device *dev)
1239 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1245 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1240 * generated. See OMAP2420 Errata item 1.101. 1246 * generated. See OMAP2420 Errata item 1.101.
1241 */ 1247 */
1242 if (!(bank->enabled_non_wakeup_gpios))
1243 goto update_gpio_context_count;
1244
1245 bank->saved_datain = __raw_readl(bank->base + 1248 bank->saved_datain = __raw_readl(bank->base +
1246 bank->regs->datain); 1249 bank->regs->datain);
1247 l1 = __raw_readl(bank->base + bank->regs->fallingdetect); 1250 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
@@ -1290,7 +1293,7 @@ static int omap_gpio_runtime_resume(struct device *dev)
1290 __raw_writel(bank->context.risingdetect, 1293 __raw_writel(bank->context.risingdetect,
1291 bank->base + bank->regs->risingdetect); 1294 bank->base + bank->regs->risingdetect);
1292 1295
1293 if (!bank->enabled_non_wakeup_gpios || !bank->workaround_enabled) { 1296 if (!bank->workaround_enabled) {
1294 spin_unlock_irqrestore(&bank->lock, flags); 1297 spin_unlock_irqrestore(&bank->lock, flags);
1295 return 0; 1298 return 0;
1296 } 1299 }